Merging r258471:

[oota-llvm.git] / test / CodeGen / AArch64 / addsub.ll

diff --git a/test/CodeGen/AArch64/addsub.ll b/test/CodeGen/AArch64/addsub.ll
index 3aa427c352c67b12f68599cde2268875bfff6424..d6350a6db0eeb6a8562ea60f9044bb2d8899733d 100644 (file)
--- a/test/CodeGen/AArch64/addsub.ll
+++ b/test/CodeGen/AArch64/addsub.ll
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs < %s -mtriple=arm64-linux-gnu | FileCheck %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-linux-gnu | FileCheck %s
 
 ; Note that this should be refactored (for efficiency if nothing else)
 ; when the PCS is implemented so we don't have to worry about the
@@ -12,29 +12,57 @@ define void @add_small() {
 ; CHECK-LABEL: add_small:
 
 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #4095
-  %val32 = load i32* @var_i32
+  %val32 = load i32, i32* @var_i32
   %newval32 = add i32 %val32, 4095
   store i32 %newval32, i32* @var_i32
 
 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, #52
-  %val64 = load i64* @var_i64
+  %val64 = load i64, i64* @var_i64
   %newval64 = add i64 %val64, 52
   store i64 %newval64, i64* @var_i64
 
   ret void
 }
 
+; Make sure we grab the imm variant when the register operand
+; can be implicitly zero-extend.
+; We used to generate something horrible like this:
+; wA = ldrb
+; xB = ldimm 12
+; xC = add xB, wA, uxtb
+; whereas this can be achieved with:
+; wA = ldrb
+; xC = add xA, #12 ; <- xA implicitly zero extend wA.
+define void @add_small_imm(i8* %p, i64* %q, i32 %b, i32* %addr) {
+; CHECK-LABEL: add_small_imm:
+entry:
+
+; CHECK: ldrb w[[LOAD32:[0-9]+]], [x0]
+  %t = load i8, i8* %p
+  %promoted = zext i8 %t to i64
+  %zextt = zext i8 %t to i32
+  %add = add nuw i32 %zextt, %b
+
+; CHECK: add [[ADD2:x[0-9]+]], x[[LOAD32]], #12
+  %add2 = add nuw i64 %promoted, 12
+  store i32 %add, i32* %addr
+
+; CHECK: str [[ADD2]], [x1]
+  store i64 %add2, i64* %q
+  ret void
+}
+
 ; Add 12-bit immediates, shifted left by 12 bits
 define void @add_med() {
 ; CHECK-LABEL: add_med:
 
 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{#3567, lsl #12|#14610432}}
-  %val32 = load i32* @var_i32
+  %val32 = load i32, i32* @var_i32
   %newval32 = add i32 %val32, 14610432 ; =0xdef000
   store i32 %newval32, i32* @var_i32
 
 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{#4095, lsl #12|#16773120}}
-  %val64 = load i64* @var_i64
+  %val64 = load i64, i64* @var_i64
   %newval64 = add i64 %val64, 16773120 ; =0xfff000
   store i64 %newval64, i64* @var_i64
 
@@ -46,12 +74,12 @@ define void @sub_small() {
 ; CHECK-LABEL: sub_small:
 
 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, #4095
-  %val32 = load i32* @var_i32
+  %val32 = load i32, i32* @var_i32
   %newval32 = sub i32 %val32, 4095
   store i32 %newval32, i32* @var_i32
 
 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, #52
-  %val64 = load i64* @var_i64
+  %val64 = load i64, i64* @var_i64
   %newval64 = sub i64 %val64, 52
   store i64 %newval64, i64* @var_i64
 
@@ -63,12 +91,12 @@ define void @sub_med() {
 ; CHECK-LABEL: sub_med:
 
 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{#3567, lsl #12|#14610432}}
-  %val32 = load i32* @var_i32
+  %val32 = load i32, i32* @var_i32
   %newval32 = sub i32 %val32, 14610432 ; =0xdef000
   store i32 %newval32, i32* @var_i32
 
 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{#4095, lsl #12|#16773120}}
-  %val64 = load i64* @var_i64
+  %val64 = load i64, i64* @var_i64
   %newval64 = sub i64 %val64, 16773120 ; =0xfff000
   store i64 %newval64, i64* @var_i64
 
@@ -77,7 +105,7 @@ define void @sub_med() {
 
 define void @testing() {
 ; CHECK-LABEL: testing:
-  %val = load i32* @var_i32
+  %val = load i32, i32* @var_i32
 
 ; CHECK: cmp {{w[0-9]+}}, #4095
 ; CHECK: b.ne [[RET:.?LBB[0-9]+_[0-9]+]]