Interchange Dwarf numbers of ESP and EBP on x86 Darwin.

[oota-llvm.git] / lib / Target / X86 / X86RegisterInfo.h

diff --git a/lib/Target/X86/X86RegisterInfo.h b/lib/Target/X86/X86RegisterInfo.h
index 6a2c19e6b63bffa98d7ad9dd13fd4c2c58184553..ec526c1773ba1c985cdf42c6eaf52a85ec59d938 100644 (file)
--- a/lib/Target/X86/X86RegisterInfo.h
+++ b/lib/Target/X86/X86RegisterInfo.h
@@ -46,6 +46,10 @@ private:
   ///
   unsigned SlotSize;
 
+  /// StackAlign - Default stack alignment.
+  ///
+  unsigned StackAlign;
+
   /// StackPtr - X86 physical register used as stack ptr.
   ///
   unsigned StackPtr;
@@ -73,6 +77,10 @@ public:
   /// register identifier.
   unsigned getX86RegNum(unsigned RegNo);
 
+  /// getDwarfRegNum - allows modification of X86GenRegisterInfo::getDwarfRegNum
+  /// (created by TableGen) for target dependencies.
+  int getDwarfRegNum(unsigned RegNum) const;
+
   /// Code Generation virtual methods...
   ///
   bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
@@ -89,9 +97,9 @@ public:
                            const TargetRegisterClass *RC) const;
 
   void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
-                      SmallVector<MachineOperand,4> Addr,
+                      SmallVectorImpl<MachineOperand> &Addr,
                       const TargetRegisterClass *RC,
-                      SmallVector<MachineInstr*,4> &NewMIs) const;
+                      SmallVectorImpl<MachineInstr*> &NewMIs) const;
 
   void loadRegFromStackSlot(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MI,
@@ -99,9 +107,9 @@ public:
                             const TargetRegisterClass *RC) const;
 
   void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
-                       SmallVector<MachineOperand,4> Addr,
+                       SmallVectorImpl<MachineOperand> &Addr,
                        const TargetRegisterClass *RC,
-                       SmallVector<MachineInstr*,4> &NewMIs) const;
+                       SmallVectorImpl<MachineInstr*> &NewMIs) const;
 
   void copyRegToReg(MachineBasicBlock &MBB,
                     MachineBasicBlock::iterator MI,
@@ -132,15 +140,28 @@ public:
                                   unsigned OpNum,
                                   MachineInstr* LoadMI) const;
 
-  /// unfoldMemoryOperand - Separate a single instruction which folded a load or a
+  /// getOpcodeAfterMemoryFold - Returns the opcode of the would be new
+  /// instruction after load / store is folded into an instruction of the
+  /// specified opcode. It returns zero if the specified unfolding is not
+  /// possible.
+  unsigned getOpcodeAfterMemoryFold(unsigned Opc, unsigned OpNum) const;
+
+  /// unfoldMemoryOperand - Separate a single instruction which folded a load or
   /// a store or a load and a store into two or more instruction. If this is
   /// possible, returns true as well as the new instructions by reference.
   bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
                            unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
-                           SmallVector<MachineInstr*, 4> &NewMIs) const;
+                           SmallVectorImpl<MachineInstr*> &NewMIs) const;
 
   bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
-                           SmallVector<SDNode*, 4> &NewNodes) const;
+                           SmallVectorImpl<SDNode*> &NewNodes) const;
+
+  /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
+  /// instruction after load / store are unfolded from an instruction of the
+  /// specified opcode. It returns zero if the specified unfolding is not
+  /// possible.
+  unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
+                                      bool UnfoldLoad, bool UnfoldStore) const;
 
   /// getCalleeSavedRegs - Return a null-terminated list of all of the
   /// callee-save registers on this target.