Add debug support for X86/ELF targets (Linux). This allows llvm-gcc4

[oota-llvm.git] / lib / Target / X86 / X86InstrInfo.td

diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index 27c84341791d9cda0bd7148290ab5b07f2ab251a..359513c9487f900b19f3e58f07601db9a473c5fe 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -135,9 +135,9 @@ def brtarget : Operand<OtherVT>;
 //
 
 // Define X86 specific addressing mode.
-def addr      : ComplexPattern<iPTR, 4, "SelectAddr", []>;
+def addr      : ComplexPattern<iPTR, 4, "SelectAddr", [], []>;
 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
-                               [add, mul, shl, or, frameindex]>;
+                               [add, mul, shl, or, frameindex], []>;
 
 //===----------------------------------------------------------------------===//
 // X86 Instruction Format Definitions.
@@ -228,11 +228,6 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr>
   bits<3> FPFormBits = 0;
 }
 
-class Imp<list<Register> uses, list<Register> defs> {
-  list<Register> Uses = uses;
-  list<Register> Defs = defs;
-}
-
 
 // Prefix byte classes which are used to indicate to the ad-hoc machine code
 // emitter that various prefix bytes are required.
@@ -346,11 +341,15 @@ class Ii32<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
 // Instruction list...
 //
 
+// ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
+// a stack adjustment and the codegen must know that they may modify the stack
+// pointer before prolog-epilog rewriting occurs.
 def ADJCALLSTACKDOWN : I<0, Pseudo, (ops i32imm:$amt), "#ADJCALLSTACKDOWN",
-                         [(X86callseq_start imm:$amt)]>;
+                         [(X86callseq_start imm:$amt)]>, Imp<[ESP],[ESP]>;
 def ADJCALLSTACKUP   : I<0, Pseudo, (ops i32imm:$amt1, i32imm:$amt2),
                          "#ADJCALLSTACKUP",
-                         [(X86callseq_end imm:$amt1, imm:$amt2)]>;
+                         [(X86callseq_end imm:$amt1, imm:$amt2)]>,
+                         Imp<[ESP],[ESP]>;
 def IMPLICIT_USE     : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_USE", []>;
 def IMPLICIT_DEF     : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_DEF", []>;
 def IMPLICIT_DEF_GR8  : I<0, Pseudo, (ops GR8:$dst),
@@ -2452,9 +2451,9 @@ def DWARF_LOC   : I<0, Pseudo, (ops i32imm:$line, i32imm:$col, i32imm:$file),
                     [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
                       (i32 imm:$file))]>;
 
-def DWARF_LABEL : I<0, Pseudo, (ops i32imm:$id),
-                   "\nLdebug_loc${id:debug}:",
-                   [(dwarf_label (i32 imm:$id))]>;
+def DWARF_LABEL : I<0, Pseudo, (ops i32imm:$id), 
+                    "\n${:private}debug_loc${id:debug}:",
+                    [(dwarf_label (i32 imm:$id))]>;
 
 //===----------------------------------------------------------------------===//
 // Non-Instruction Patterns
@@ -2513,9 +2512,9 @@ def : Pat<(subc GR32:$src1, imm:$src2),
 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
           (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
 
-def : Pat<(truncstore (i8 imm:$src), addr:$dst, i1), 
+def : Pat<(truncstorei1 (i8 imm:$src), addr:$dst), 
           (MOV8mi addr:$dst, imm:$src)>;
-def : Pat<(truncstore GR8:$src, addr:$dst, i1), 
+def : Pat<(truncstorei1 GR8:$src, addr:$dst), 
           (MOV8mr addr:$dst, GR8:$src)>;
 
 // Comparisons.