//
//===----------------------------------------------------------------------===//
+// Some 'special' instructions
+let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
+ def FP_TO_INT16_IN_MEM : I<0, Pseudo,
+ (ops i16mem:$dst, RFP:$src),
+ "#FP_TO_INT16_IN_MEM PSEUDO!",
+ [(X86fp_to_i16mem RFP:$src, addr:$dst)]>;
+ def FP_TO_INT32_IN_MEM : I<0, Pseudo,
+ (ops i32mem:$dst, RFP:$src),
+ "#FP_TO_INT32_IN_MEM PSEUDO!",
+ [(X86fp_to_i32mem RFP:$src, addr:$dst)]>;
+ def FP_TO_INT64_IN_MEM : I<0, Pseudo,
+ (ops i64mem:$dst, RFP:$src),
+ "#FP_TO_INT64_IN_MEM PSEUDO!",
+ [(X86fp_to_i64mem RFP:$src, addr:$dst)]>;
+}
+
+let isTerminator = 1 in
+ let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
+ def FP_REG_KILL : I<0, Pseudo, (ops), "#FP_REG_KILL", []>;
+
// All FP Stack operations are represented with two instructions here. The
// first instruction, generated by the instruction selector, uses "RFP"
// registers: a traditional register file to reference floating point values.
(ops i16mem:$dst), "fnstcw $dst", []>;
def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
(ops i16mem:$dst), "fldcw $dst", []>;
+
+//===----------------------------------------------------------------------===//
+// Non-Instruction Patterns
+//===----------------------------------------------------------------------===//
+
+// Required for RET of f32 / f64 values.
+def : Pat<(X86fld addr:$src, f32), (FpLD32m addr:$src)>;
+def : Pat<(X86fld addr:$src, f64), (FpLD64m addr:$src)>;
+
+// Required for CALL which return f32 / f64 values.
+def : Pat<(X86fst RFP:$src, addr:$op, f32), (FpST32m addr:$op, RFP:$src)>;
+def : Pat<(X86fst RFP:$src, addr:$op, f64), (FpST64m addr:$op, RFP:$src)>;
+
+// Floating point constant -0.0 and -1.0
+def : Pat<(f64 fp64immneg0), (FpCHS (FpLD0))>, Requires<[FPStack]>;
+def : Pat<(f64 fp64immneg1), (FpCHS (FpLD1))>, Requires<[FPStack]>;
+
+// Used to conv. i64 to f64 since there isn't a SSE version.
+def : Pat<(X86fildflag addr:$src, i64), (FpILD64m addr:$src)>;