//===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
//
// This file defines a simple peephole instruction selector for the x86 target
//
void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
const std::vector<ValueRecord> &Args);
void visitCallInst(CallInst &I);
- void visitInvokeInst(InvokeInst &II);
void visitIntrinsicCall(LLVMIntrinsic::ID ID, CallInst &I);
// Arithmetic operators
void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI,
unsigned DestReg, const Type *DestTy,
unsigned Op0Reg, unsigned Op1Reg);
+ void doMultiplyConst(MachineBasicBlock *MBB,
+ MachineBasicBlock::iterator &MBBI,
+ unsigned DestReg, const Type *DestTy,
+ unsigned Op0Reg, unsigned Op1Val);
void visitMul(BinaryOperator &B);
void visitDiv(BinaryOperator &B) { visitDivRem(B); }
// Comparison operators...
void visitSetCondInst(SetCondInst &I);
- bool EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1,
- MachineBasicBlock *MBB,
- MachineBasicBlock::iterator &MBBI);
-
+ unsigned EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
+ MachineBasicBlock *MBB,
+ MachineBasicBlock::iterator &MBBI);
+
// Memory Instructions
- MachineInstr *doFPLoad(MachineBasicBlock *MBB,
- MachineBasicBlock::iterator &MBBI,
- const Type *Ty, unsigned DestReg);
void visitLoadInst(LoadInst &I);
- void doFPStore(const Type *Ty, unsigned DestAddrReg, unsigned SrcReg);
void visitStoreInst(StoreInst &I);
void visitGetElementPtrInst(GetElementPtrInst &I);
void visitAllocaInst(AllocaInst &I);
void visitShiftInst(ShiftInst &I);
void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
void visitCastInst(CastInst &I);
- void visitVarArgInst(VarArgInst &I);
+ void visitVANextInst(VANextInst &I);
+ void visitVAArgInst(VAArgInst &I);
void visitInstruction(Instruction &I) {
std::cerr << "Cannot instruction select: " << I;
default:
std::cerr << "Offending expr: " << C << "\n";
- assert(0 && "Constant expressions not yet handled!\n");
+ assert(0 && "Constant expression not yet handled!\n");
}
}
// Otherwise we need to spill the constant to memory...
MachineConstantPool *CP = F->getConstantPool();
unsigned CPI = CP->getConstantPoolIndex(CFP);
- addConstantPoolReference(doFPLoad(MBB, IP, CFP->getType(), R), CPI);
+ const Type *Ty = CFP->getType();
+
+ assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
+ unsigned LoadOpcode = Ty == Type::FloatTy ? X86::FLDr32 : X86::FLDr64;
+ addConstantPoolReference(BMI(MBB, IP, LoadOpcode, 4, R), CPI);
}
} else if (isa<ConstantPointerNull>(C)) {
// Loop over all of the PHI nodes in the LLVM basic block...
unsigned NumPHIs = 0;
for (BasicBlock::const_iterator I = BB->begin();
- PHINode *PN = (PHINode*)dyn_cast<PHINode>(I); ++I) {
+ PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
// Create a new machine instr PHI node, and insert it.
unsigned PHIReg = getReg(*PN);
ValReg = EntryIt->second;
} else {
- // Get the incoming value into a virtual register. If it is not
- // already available in a virtual register, insert the computation
- // code into PredMBB
+ // Get the incoming value into a virtual register.
//
- MachineBasicBlock::iterator PI = PredMBB->end();
- while (PI != PredMBB->begin() &&
- TII.isTerminatorInstr((*(PI-1))->getOpcode()))
- --PI;
- ValReg = getReg(PN->getIncomingValue(i), PredMBB, PI);
+ Value *Val = PN->getIncomingValue(i);
+
+ // If this is a constant or GlobalValue, we may have to insert code
+ // into the basic block to compute it into a virtual register.
+ if (isa<Constant>(Val) || isa<GlobalValue>(Val)) {
+ // Because we don't want to clobber any values which might be in
+ // physical registers with the computation of this constant (which
+ // might be arbitrarily complex if it is a constant expression),
+ // just insert the computation at the top of the basic block.
+ MachineBasicBlock::iterator PI = PredMBB->begin();
+
+ // Skip over any PHI nodes though!
+ while (PI != PredMBB->end() && (*PI)->getOpcode() == X86::PHI)
+ ++PI;
+
+ ValReg = getReg(Val, PredMBB, PI);
+ } else {
+ ValReg = getReg(Val);
+ }
// Remember that we inserted a value for this PHI for this predecessor
PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
//
static SetCondInst *canFoldSetCCIntoBranch(Value *V) {
if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
- if (SCI->use_size() == 1 && isa<BranchInst>(SCI->use_back()) &&
+ if (SCI->hasOneUse() && isa<BranchInst>(SCI->use_back()) &&
SCI->getParent() == cast<BranchInst>(SCI->use_back())->getParent()) {
const Type *Ty = SCI->getOperand(0)->getType();
if (Ty != Type::LongTy && Ty != Type::ULongTy)
// setge -> setge setae
// setgt -> setg seta
// setle -> setle setbe
-static const unsigned SetCCOpcodeTab[2][6] = {
- {X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAEr, X86::SETAr, X86::SETBEr},
- {X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGEr, X86::SETGr, X86::SETLEr},
+// ----
+// sets // Used by comparison with 0 optimization
+// setns
+static const unsigned SetCCOpcodeTab[2][8] = {
+ { X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAEr, X86::SETAr, X86::SETBEr,
+ 0, 0 },
+ { X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGEr, X86::SETGr, X86::SETLEr,
+ X86::SETSr, X86::SETNSr },
};
-bool ISel::EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1,
- MachineBasicBlock *MBB,
- MachineBasicBlock::iterator &IP) {
+// EmitComparison - This function emits a comparison of the two operands,
+// returning the extended setcc code to use.
+unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
+ MachineBasicBlock *MBB,
+ MachineBasicBlock::iterator &IP) {
// The arguments are already supposed to be of the same type.
const Type *CompTy = Op0->getType();
- bool isSigned = CompTy->isSigned();
unsigned Class = getClassB(CompTy);
unsigned Op0r = getReg(Op0, MBB, IP);
// Mask off any upper bits of the constant, if there are any...
Op1v &= (1ULL << (8 << Class)) - 1;
- switch (Class) {
- case cByte: BMI(MBB,IP, X86::CMPri8, 2).addReg(Op0r).addZImm(Op1v);break;
- case cShort: BMI(MBB,IP, X86::CMPri16,2).addReg(Op0r).addZImm(Op1v);break;
- case cInt: BMI(MBB,IP, X86::CMPri32,2).addReg(Op0r).addZImm(Op1v);break;
- default:
- assert(0 && "Invalid class!");
+ // If this is a comparison against zero, emit more efficient code. We
+ // can't handle unsigned comparisons against zero unless they are == or
+ // !=. These should have been strength reduced already anyway.
+ if (Op1v == 0 && (CompTy->isSigned() || OpNum < 2)) {
+ static const unsigned TESTTab[] = {
+ X86::TESTrr8, X86::TESTrr16, X86::TESTrr32
+ };
+ BMI(MBB, IP, TESTTab[Class], 2).addReg(Op0r).addReg(Op0r);
+
+ if (OpNum == 2) return 6; // Map jl -> js
+ if (OpNum == 3) return 7; // Map jg -> jns
+ return OpNum;
}
- return isSigned;
+
+ static const unsigned CMPTab[] = {
+ X86::CMPri8, X86::CMPri16, X86::CMPri32
+ };
+
+ BMI(MBB, IP, CMPTab[Class], 2).addReg(Op0r).addZImm(Op1v);
+ return OpNum;
}
unsigned Op1r = getReg(Op1, MBB, IP);
BMI(MBB, IP, X86::FpUCOM, 2).addReg(Op0r).addReg(Op1r);
BMI(MBB, IP, X86::FNSTSWr8, 0);
BMI(MBB, IP, X86::SAHF, 1);
- isSigned = false; // Compare with unsigned operators
break;
case cLong:
BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r);
BMI(MBB, IP, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r+1).addReg(Op1r+1);
- BMI(MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, X86::BL);
+ BMI(MBB, IP, SetCCOpcodeTab[CompTy->isSigned()][OpNum], 0, X86::BL);
BMI(MBB, IP, X86::IMPLICIT_DEF, 0, X86::BH);
BMI(MBB, IP, X86::IMPLICIT_DEF, 0, X86::AH);
BMI(MBB, IP, X86::CMOVErr16, 2, X86::BX).addReg(X86::BX).addReg(X86::AX);
// NOTE: visitSetCondInst knows that the value is dumped into the BL
// register at this point for long values...
- return isSigned;
+ return OpNum;
}
}
- return isSigned;
+ return OpNum;
}
Value *Op0, Value *Op1, unsigned Opcode,
unsigned TargetReg) {
unsigned OpNum = getSetCCNumber(Opcode);
- bool isSigned = EmitComparisonGetSignedness(OpNum, Op0, Op1, MBB, IP);
+ OpNum = EmitComparison(OpNum, Op0, Op1, MBB, IP);
+
+ const Type *CompTy = Op0->getType();
+ unsigned CompClass = getClassB(CompTy);
+ bool isSigned = CompTy->isSigned() && CompClass != cFP;
- if (getClassB(Op0->getType()) != cLong || OpNum < 2) {
+ if (CompClass != cLong || OpNum < 2) {
// Handle normal comparisons with a setcc instruction...
BMI(MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, TargetReg);
} else {
unsigned OpNum = getSetCCNumber(SCI->getOpcode());
MachineBasicBlock::iterator MII = BB->end();
- bool isSigned = EmitComparisonGetSignedness(OpNum, SCI->getOperand(0),
- SCI->getOperand(1), BB, MII);
+ OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB, MII);
+
+ const Type *CompTy = SCI->getOperand(0)->getType();
+ bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
+
// LLVM -> X86 signed X86 unsigned
// ----- ---------- ------------
// seteq -> je je
// setge -> jge jae
// setgt -> jg ja
// setle -> jle jbe
- static const unsigned OpcodeTab[2][6] = {
- { X86::JE, X86::JNE, X86::JB, X86::JAE, X86::JA, X86::JBE },
- { X86::JE, X86::JNE, X86::JL, X86::JGE, X86::JG, X86::JLE },
+ // ----
+ // js // Used by comparison with 0 optimization
+ // jns
+
+ static const unsigned OpcodeTab[2][8] = {
+ { X86::JE, X86::JNE, X86::JB, X86::JAE, X86::JA, X86::JBE, 0, 0 },
+ { X86::JE, X86::JNE, X86::JL, X86::JGE, X86::JG, X86::JLE,
+ X86::JS, X86::JNS },
};
if (BI.getSuccessor(0) != NextBB) {
}
-// visitInvokeInst - For now, we don't support the llvm.unwind intrinsic, so
-// invoke's are just calls with an unconditional branch after them!
-void ISel::visitInvokeInst(InvokeInst &II) {
- MachineInstr *TheCall;
- if (Function *F = II.getCalledFunction()) {
- // Emit a CALL instruction with PC-relative displacement.
- TheCall = BuildMI(X86::CALLpcrel32, 1).addGlobalAddress(F, true);
- } else { // Emit an indirect call...
- unsigned Reg = getReg(II.getCalledValue());
- TheCall = BuildMI(X86::CALLr32, 1).addReg(Reg);
- }
-
- std::vector<ValueRecord> Args;
- for (unsigned i = 3, e = II.getNumOperands(); i != e; ++i)
- Args.push_back(ValueRecord(II.getOperand(i)));
-
- unsigned DestReg = II.getType() != Type::VoidTy ? getReg(II) : 0;
- doCall(ValueRecord(DestReg, II.getType()), TheCall, Args);
-
- // If the normal destination is not the next basic block, emit a 'jmp'.
- if (II.getNormalDest() != getBlockAfter(II.getParent()))
- BuildMI(BB, X86::JMP, 1).addPCDisp(II.getNormalDest());
-}
-
-
void ISel::visitIntrinsicCall(LLVMIntrinsic::ID ID, CallInst &CI) {
unsigned TmpReg1, TmpReg2;
switch (ID) {
case LLVMIntrinsic::va_start:
// Get the address of the first vararg value...
- TmpReg1 = makeAnotherReg(Type::UIntTy);
+ TmpReg1 = getReg(CI);
addFrameReference(BuildMI(BB, X86::LEAr32, 5, TmpReg1), VarArgsFrameIndex);
- TmpReg2 = getReg(CI.getOperand(1));
- addDirectMem(BuildMI(BB, X86::MOVrm32, 5), TmpReg2).addReg(TmpReg1);
return;
- case LLVMIntrinsic::va_end: return; // Noop on X86
case LLVMIntrinsic::va_copy:
- TmpReg1 = getReg(CI.getOperand(2)); // Get existing va_list
- TmpReg2 = getReg(CI.getOperand(1)); // Get va_list* to store into
- addDirectMem(BuildMI(BB, X86::MOVrm32, 5), TmpReg2).addReg(TmpReg1);
+ TmpReg1 = getReg(CI);
+ TmpReg2 = getReg(CI.getOperand(1));
+ BuildMI(BB, X86::MOVrr32, 1, TmpReg1).addReg(TmpReg2);
return;
+ case LLVMIntrinsic::va_end: return; // Noop on X86
- case LLVMIntrinsic::unwind: // llvm.unwind is not supported yet!
case LLVMIntrinsic::longjmp:
case LLVMIntrinsic::siglongjmp:
BuildMI(BB, X86::CALLpcrel32, 1).addExternalSymbol("abort", true);
OperatorClass, DestReg);
}
-/// visitSimpleBinary - Implement simple binary operators for integral types...
-/// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or,
-/// 4 for Xor.
+/// emitSimpleBinaryOperation - Implement simple binary operators for integral
+/// types... OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for
+/// Or, 4 for Xor.
///
/// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
/// and constant expression support.
-void ISel::emitSimpleBinaryOperation(MachineBasicBlock *BB,
+///
+void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
MachineBasicBlock::iterator &IP,
Value *Op0, Value *Op1,
- unsigned OperatorClass,unsigned TargetReg){
+ unsigned OperatorClass, unsigned DestReg) {
unsigned Class = getClassB(Op0->getType());
+
+ // sub 0, X -> neg X
+ if (OperatorClass == 1 && Class != cLong)
+ if (ConstantInt *CI = dyn_cast<ConstantInt>(Op0))
+ if (CI->isNullValue()) {
+ unsigned op1Reg = getReg(Op1, MBB, IP);
+ switch (Class) {
+ default: assert(0 && "Unknown class for this function!");
+ case cByte:
+ BMI(MBB, IP, X86::NEGr8, 1, DestReg).addReg(op1Reg);
+ return;
+ case cShort:
+ BMI(MBB, IP, X86::NEGr16, 1, DestReg).addReg(op1Reg);
+ return;
+ case cInt:
+ BMI(MBB, IP, X86::NEGr32, 1, DestReg).addReg(op1Reg);
+ return;
+ }
+ }
+
if (!isa<ConstantInt>(Op1) || Class == cLong) {
static const unsigned OpcodeTab[][4] = {
// Arithmetic operators
unsigned Opcode = OpcodeTab[OperatorClass][Class];
assert(Opcode && "Floating point arguments to logical inst?");
- unsigned Op0r = getReg(Op0, BB, IP);
- unsigned Op1r = getReg(Op1, BB, IP);
- BMI(BB, IP, Opcode, 2, TargetReg).addReg(Op0r).addReg(Op1r);
+ unsigned Op0r = getReg(Op0, MBB, IP);
+ unsigned Op1r = getReg(Op1, MBB, IP);
+ BMI(MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
if (isLong) { // Handle the upper 32 bits of long values...
static const unsigned TopTab[] = {
X86::ADCrr32, X86::SBBrr32, X86::ANDrr32, X86::ORrr32, X86::XORrr32
};
- BMI(BB, IP, TopTab[OperatorClass], 2,
- TargetReg+1).addReg(Op0r+1).addReg(Op1r+1);
+ BMI(MBB, IP, TopTab[OperatorClass], 2,
+ DestReg+1).addReg(Op0r+1).addReg(Op1r+1);
}
- } else {
- // Special case: op Reg, <const>
- ConstantInt *Op1C = cast<ConstantInt>(Op1);
+ return;
+ }
- static const unsigned OpcodeTab[][3] = {
- // Arithmetic operators
- { X86::ADDri8, X86::ADDri16, X86::ADDri32 }, // ADD
- { X86::SUBri8, X86::SUBri16, X86::SUBri32 }, // SUB
-
- // Bitwise operators
- { X86::ANDri8, X86::ANDri16, X86::ANDri32 }, // AND
- { X86:: ORri8, X86:: ORri16, X86:: ORri32 }, // OR
- { X86::XORri8, X86::XORri16, X86::XORri32 }, // XOR
- };
+ // Special case: op Reg, <const>
+ ConstantInt *Op1C = cast<ConstantInt>(Op1);
+ unsigned Op0r = getReg(Op0, MBB, IP);
- assert(Class < 3 && "General code handles 64-bit integer types!");
- unsigned Opcode = OpcodeTab[OperatorClass][Class];
- unsigned Op0r = getReg(Op0, BB, IP);
- uint64_t Op1v = cast<ConstantInt>(Op1C)->getRawValue();
+ // xor X, -1 -> not X
+ if (OperatorClass == 4 && Op1C->isAllOnesValue()) {
+ static unsigned const NOTTab[] = { X86::NOTr8, X86::NOTr16, X86::NOTr32 };
+ BMI(MBB, IP, NOTTab[Class], 1, DestReg).addReg(Op0r);
+ return;
+ }
- // Mask off any upper bits of the constant, if there are any...
- Op1v &= (1ULL << (8 << Class)) - 1;
- BMI(BB, IP, Opcode, 2, TargetReg).addReg(Op0r).addZImm(Op1v);
+ // add X, -1 -> dec X
+ if (OperatorClass == 0 && Op1C->isAllOnesValue()) {
+ static unsigned const DECTab[] = { X86::DECr8, X86::DECr16, X86::DECr32 };
+ BMI(MBB, IP, DECTab[Class], 1, DestReg).addReg(Op0r);
+ return;
+ }
+
+ // add X, 1 -> inc X
+ if (OperatorClass == 0 && Op1C->equalsInt(1)) {
+ static unsigned const DECTab[] = { X86::INCr8, X86::INCr16, X86::INCr32 };
+ BMI(MBB, IP, DECTab[Class], 1, DestReg).addReg(Op0r);
+ return;
}
+
+ static const unsigned OpcodeTab[][3] = {
+ // Arithmetic operators
+ { X86::ADDri8, X86::ADDri16, X86::ADDri32 }, // ADD
+ { X86::SUBri8, X86::SUBri16, X86::SUBri32 }, // SUB
+
+ // Bitwise operators
+ { X86::ANDri8, X86::ANDri16, X86::ANDri32 }, // AND
+ { X86:: ORri8, X86:: ORri16, X86:: ORri32 }, // OR
+ { X86::XORri8, X86::XORri16, X86::XORri32 }, // XOR
+ };
+
+ assert(Class < 3 && "General code handles 64-bit integer types!");
+ unsigned Opcode = OpcodeTab[OperatorClass][Class];
+ uint64_t Op1v = cast<ConstantInt>(Op1C)->getRawValue();
+
+ // Mask off any upper bits of the constant, if there are any...
+ Op1v &= (1ULL << (8 << Class)) - 1;
+ BMI(MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addZImm(Op1v);
}
/// doMultiply - Emit appropriate instructions to multiply together the
return;
case cInt:
case cShort:
- BMI(BB, MBBI, Class == cInt ? X86::IMULr32 : X86::IMULr16, 2, DestReg)
+ BMI(BB, MBBI, Class == cInt ? X86::IMULrr32 : X86::IMULrr16, 2, DestReg)
.addReg(op0Reg).addReg(op1Reg);
return;
case cByte:
}
}
+// ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
+// returns zero when the input is not exactly a power of two.
+static unsigned ExactLog2(unsigned Val) {
+ if (Val == 0) return 0;
+ unsigned Count = 0;
+ while (Val != 1) {
+ if (Val & 1) return 0;
+ Val >>= 1;
+ ++Count;
+ }
+ return Count+1;
+}
+
+void ISel::doMultiplyConst(MachineBasicBlock *MBB,
+ MachineBasicBlock::iterator &IP,
+ unsigned DestReg, const Type *DestTy,
+ unsigned op0Reg, unsigned ConstRHS) {
+ unsigned Class = getClass(DestTy);
+
+ // If the element size is exactly a power of 2, use a shift to get it.
+ if (unsigned Shift = ExactLog2(ConstRHS)) {
+ switch (Class) {
+ default: assert(0 && "Unknown class for this function!");
+ case cByte:
+ BMI(MBB, IP, X86::SHLir32, 2, DestReg).addReg(op0Reg).addZImm(Shift-1);
+ return;
+ case cShort:
+ BMI(MBB, IP, X86::SHLir32, 2, DestReg).addReg(op0Reg).addZImm(Shift-1);
+ return;
+ case cInt:
+ BMI(MBB, IP, X86::SHLir32, 2, DestReg).addReg(op0Reg).addZImm(Shift-1);
+ return;
+ }
+ }
+
+ if (Class == cShort) {
+ BMI(MBB, IP, X86::IMULri16, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
+ return;
+ } else if (Class == cInt) {
+ BMI(MBB, IP, X86::IMULri32, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
+ return;
+ }
+
+ // Most general case, emit a normal multiply...
+ static const unsigned MOVirTab[] = {
+ X86::MOVir8, X86::MOVir16, X86::MOVir32
+ };
+
+ unsigned TmpReg = makeAnotherReg(DestTy);
+ BMI(MBB, IP, MOVirTab[Class], 1, TmpReg).addZImm(ConstRHS);
+
+ // Emit a MUL to multiply the register holding the index by
+ // elementSize, putting the result in OffsetReg.
+ doMultiply(MBB, IP, DestReg, DestTy, op0Reg, TmpReg);
+}
+
/// visitMul - Multiplies are not simple binary operators because they must deal
/// with the EAX register explicitly.
///
void ISel::visitMul(BinaryOperator &I) {
unsigned Op0Reg = getReg(I.getOperand(0));
- unsigned Op1Reg = getReg(I.getOperand(1));
unsigned DestReg = getReg(I);
// Simple scalar multiply?
if (I.getType() != Type::LongTy && I.getType() != Type::ULongTy) {
- MachineBasicBlock::iterator MBBI = BB->end();
- doMultiply(BB, MBBI, DestReg, I.getType(), Op0Reg, Op1Reg);
+ if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(1))) {
+ unsigned Val = (unsigned)CI->getRawValue(); // Cannot be 64-bit constant
+ MachineBasicBlock::iterator MBBI = BB->end();
+ doMultiplyConst(BB, MBBI, DestReg, I.getType(), Op0Reg, Val);
+ } else {
+ unsigned Op1Reg = getReg(I.getOperand(1));
+ MachineBasicBlock::iterator MBBI = BB->end();
+ doMultiply(BB, MBBI, DestReg, I.getType(), Op0Reg, Op1Reg);
+ }
} else {
+ unsigned Op1Reg = getReg(I.getOperand(1));
+
// Long value. We have to do things the hard way...
// Multiply the two low parts... capturing carry into EDX
BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(Op0Reg);
MachineBasicBlock::iterator MBBI = BB->end();
unsigned AHBLReg = makeAnotherReg(Type::UIntTy); // AH*BL
- BMI(BB, MBBI, X86::IMULr32, 2, AHBLReg).addReg(Op0Reg+1).addReg(Op1Reg);
+ BMI(BB, MBBI, X86::IMULrr32, 2, AHBLReg).addReg(Op0Reg+1).addReg(Op1Reg);
unsigned AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
BuildMI(BB, X86::ADDrr32, 2, // AH*BL+(AL*BL >> 32)
MBBI = BB->end();
unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
- BMI(BB, MBBI, X86::IMULr32, 2, ALBHReg).addReg(Op0Reg).addReg(Op1Reg+1);
+ BMI(BB, MBBI, X86::IMULrr32, 2, ALBHReg).addReg(Op0Reg).addReg(Op1Reg+1);
BuildMI(BB, X86::ADDrr32, 2, // AL*BH + AH*BL + (AL*BL >> 32)
DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
return;
}
case cByte: case cShort: case cInt:
- break; // Small integerals, handled below...
+ break; // Small integrals, handled below...
default: assert(0 && "Unknown class!");
}
}
-/// doFPLoad - This method is used to load an FP value from memory using the
-/// current endianness. NOTE: This method returns a partially constructed load
-/// instruction which needs to have the memory source filled in still.
-///
-MachineInstr *ISel::doFPLoad(MachineBasicBlock *MBB,
- MachineBasicBlock::iterator &MBBI,
- const Type *Ty, unsigned DestReg) {
- assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
- unsigned LoadOpcode = Ty == Type::FloatTy ? X86::FLDr32 : X86::FLDr64;
-
- if (TM.getTargetData().isLittleEndian()) // fast path...
- return BMI(MBB, MBBI, LoadOpcode, 4, DestReg);
-
- // If we are big-endian, start by creating an LEA instruction to represent the
- // address of the memory location to load from...
- //
- unsigned SrcAddrReg = makeAnotherReg(Type::UIntTy);
- MachineInstr *Result = BMI(MBB, MBBI, X86::LEAr32, 5, SrcAddrReg);
-
- // Allocate a temporary stack slot to transform the value into...
- int FrameIdx = F->getFrameInfo()->CreateStackObject(Ty, TM.getTargetData());
-
- // Perform the bswaps 32 bits at a time...
- unsigned TmpReg1 = makeAnotherReg(Type::UIntTy);
- unsigned TmpReg2 = makeAnotherReg(Type::UIntTy);
- addDirectMem(BMI(MBB, MBBI, X86::MOVmr32, 4, TmpReg1), SrcAddrReg);
- BMI(MBB, MBBI, X86::BSWAPr32, 1, TmpReg2).addReg(TmpReg1);
- unsigned Offset = (Ty == Type::DoubleTy) << 2;
- addFrameReference(BMI(MBB, MBBI, X86::MOVrm32, 5),
- FrameIdx, Offset).addReg(TmpReg2);
-
- if (Ty == Type::DoubleTy) { // Swap the other 32 bits of a double value...
- TmpReg1 = makeAnotherReg(Type::UIntTy);
- TmpReg2 = makeAnotherReg(Type::UIntTy);
-
- addRegOffset(BMI(MBB, MBBI, X86::MOVmr32, 4, TmpReg1), SrcAddrReg, 4);
- BMI(MBB, MBBI, X86::BSWAPr32, 1, TmpReg2).addReg(TmpReg1);
- unsigned Offset = (Ty == Type::DoubleTy) << 2;
- addFrameReference(BMI(MBB, MBBI, X86::MOVrm32,5), FrameIdx).addReg(TmpReg2);
- }
-
- // Now we can reload the final byteswapped result into the final destination.
- addFrameReference(BMI(MBB, MBBI, LoadOpcode, 4, DestReg), FrameIdx);
- return Result;
-}
-
/// EmitByteSwap - Byteswap SrcReg into DestReg.
///
void ISel::EmitByteSwap(unsigned DestReg, unsigned SrcReg, unsigned Class) {
/// need to worry about the memory layout of the target machine.
///
void ISel::visitLoadInst(LoadInst &I) {
- bool isLittleEndian = TM.getTargetData().isLittleEndian();
- bool hasLongPointers = TM.getTargetData().getPointerSize() == 8;
unsigned SrcAddrReg = getReg(I.getOperand(0));
unsigned DestReg = getReg(I);
unsigned Class = getClassB(I.getType());
- switch (Class) {
- case cFP: {
- MachineBasicBlock::iterator MBBI = BB->end();
- addDirectMem(doFPLoad(BB, MBBI, I.getType(), DestReg), SrcAddrReg);
- return;
- }
- case cLong: case cInt: case cShort: case cByte:
- break; // Integers of various sizes handled below
- default: assert(0 && "Unknown memory class!");
- }
- // We need to adjust the input pointer if we are emulating a big-endian
- // long-pointer target. On these systems, the pointer that we are interested
- // in is in the upper part of the eight byte memory image of the pointer. It
- // also happens to be byte-swapped, but this will be handled later.
- //
- if (!isLittleEndian && hasLongPointers && isa<PointerType>(I.getType())) {
- unsigned R = makeAnotherReg(Type::UIntTy);
- BuildMI(BB, X86::ADDri32, 2, R).addReg(SrcAddrReg).addZImm(4);
- SrcAddrReg = R;
- }
-
- unsigned IReg = DestReg;
- if (!isLittleEndian) // If big endian we need an intermediate stage
- DestReg = makeAnotherReg(Class != cLong ? I.getType() : Type::UIntTy);
-
- static const unsigned Opcode[] = {
- X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, 0, X86::MOVmr32
- };
- addDirectMem(BuildMI(BB, Opcode[Class], 4, DestReg), SrcAddrReg);
-
- // Handle long values now...
if (Class == cLong) {
- if (isLittleEndian) {
- addRegOffset(BuildMI(BB, X86::MOVmr32, 4, DestReg+1), SrcAddrReg, 4);
- } else {
- EmitByteSwap(IReg+1, DestReg, cInt);
- unsigned TempReg = makeAnotherReg(Type::IntTy);
- addRegOffset(BuildMI(BB, X86::MOVmr32, 4, TempReg), SrcAddrReg, 4);
- EmitByteSwap(IReg, TempReg, cInt);
- }
- return;
- }
-
- if (!isLittleEndian)
- EmitByteSwap(IReg, DestReg, Class);
-}
-
-
-/// doFPStore - This method is used to store an FP value to memory using the
-/// current endianness.
-///
-void ISel::doFPStore(const Type *Ty, unsigned DestAddrReg, unsigned SrcReg) {
- assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
- unsigned StoreOpcode = Ty == Type::FloatTy ? X86::FSTr32 : X86::FSTr64;
-
- if (TM.getTargetData().isLittleEndian()) { // fast path...
- addDirectMem(BuildMI(BB, StoreOpcode,5), DestAddrReg).addReg(SrcReg);
+ addDirectMem(BuildMI(BB, X86::MOVmr32, 4, DestReg), SrcAddrReg);
+ addRegOffset(BuildMI(BB, X86::MOVmr32, 4, DestReg+1), SrcAddrReg, 4);
return;
}
- // Allocate a temporary stack slot to transform the value into...
- int FrameIdx = F->getFrameInfo()->CreateStackObject(Ty, TM.getTargetData());
- unsigned SrcAddrReg = makeAnotherReg(Type::UIntTy);
- addFrameReference(BuildMI(BB, X86::LEAr32, 5, SrcAddrReg), FrameIdx);
-
- // Store the value into a temporary stack slot...
- addDirectMem(BuildMI(BB, StoreOpcode, 5), SrcAddrReg).addReg(SrcReg);
-
- // Perform the bswaps 32 bits at a time...
- unsigned TmpReg1 = makeAnotherReg(Type::UIntTy);
- unsigned TmpReg2 = makeAnotherReg(Type::UIntTy);
- addDirectMem(BuildMI(BB, X86::MOVmr32, 4, TmpReg1), SrcAddrReg);
- BuildMI(BB, X86::BSWAPr32, 1, TmpReg2).addReg(TmpReg1);
- unsigned Offset = (Ty == Type::DoubleTy) << 2;
- addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
- DestAddrReg, Offset).addReg(TmpReg2);
-
- if (Ty == Type::DoubleTy) { // Swap the other 32 bits of a double value...
- TmpReg1 = makeAnotherReg(Type::UIntTy);
- TmpReg2 = makeAnotherReg(Type::UIntTy);
-
- addRegOffset(BuildMI(BB, X86::MOVmr32, 4, TmpReg1), SrcAddrReg, 4);
- BuildMI(BB, X86::BSWAPr32, 1, TmpReg2).addReg(TmpReg1);
- unsigned Offset = (Ty == Type::DoubleTy) << 2;
- addDirectMem(BuildMI(BB, X86::MOVrm32, 5), DestAddrReg).addReg(TmpReg2);
- }
+ static const unsigned Opcodes[] = {
+ X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FLDr32
+ };
+ unsigned Opcode = Opcodes[Class];
+ if (I.getType() == Type::DoubleTy) Opcode = X86::FLDr64;
+ addDirectMem(BuildMI(BB, Opcode, 4, DestReg), SrcAddrReg);
}
-
/// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
/// instruction.
///
void ISel::visitStoreInst(StoreInst &I) {
- bool isLittleEndian = TM.getTargetData().isLittleEndian();
- bool hasLongPointers = TM.getTargetData().getPointerSize() == 8;
unsigned ValReg = getReg(I.getOperand(0));
unsigned AddressReg = getReg(I.getOperand(1));
+
+ const Type *ValTy = I.getOperand(0)->getType();
+ unsigned Class = getClassB(ValTy);
- unsigned Class = getClassB(I.getOperand(0)->getType());
- switch (Class) {
- case cLong:
- if (isLittleEndian) {
- addDirectMem(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg).addReg(ValReg);
- addRegOffset(BuildMI(BB, X86::MOVrm32, 1+4),
- AddressReg, 4).addReg(ValReg+1);
- } else {
- unsigned T1 = makeAnotherReg(Type::IntTy);
- unsigned T2 = makeAnotherReg(Type::IntTy);
- EmitByteSwap(T1, ValReg , cInt);
- EmitByteSwap(T2, ValReg+1, cInt);
- addDirectMem(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg).addReg(T2);
- addRegOffset(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg, 4).addReg(T1);
- }
- return;
- case cFP:
- doFPStore(I.getOperand(0)->getType(), AddressReg, ValReg);
+ if (Class == cLong) {
+ addDirectMem(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg).addReg(ValReg);
+ addRegOffset(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg,4).addReg(ValReg+1);
return;
- case cInt: case cShort: case cByte:
- break; // Integers of various sizes handled below
- default: assert(0 && "Unknown memory class!");
- }
-
- if (!isLittleEndian && hasLongPointers &&
- isa<PointerType>(I.getOperand(0)->getType())) {
- unsigned R = makeAnotherReg(Type::UIntTy);
- BuildMI(BB, X86::ADDri32, 2, R).addReg(AddressReg).addZImm(4);
- AddressReg = R;
}
- if (!isLittleEndian && Class != cByte) {
- unsigned R = makeAnotherReg(I.getOperand(0)->getType());
- EmitByteSwap(R, ValReg, Class);
- ValReg = R;
- }
-
- static const unsigned Opcode[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
- addDirectMem(BuildMI(BB, Opcode[Class], 1+4), AddressReg).addReg(ValReg);
+ static const unsigned Opcodes[] = {
+ X86::MOVrm8, X86::MOVrm16, X86::MOVrm32, X86::FSTr32
+ };
+ unsigned Opcode = Opcodes[Class];
+ if (ValTy == Type::DoubleTy) Opcode = X86::FSTr64;
+ addDirectMem(BuildMI(BB, Opcode, 1+4), AddressReg).addReg(ValReg);
}
abort();
}
-/// visitVarArgInst - Implement the va_arg instruction...
+/// visitVANextInst - Implement the va_next instruction...
///
-void ISel::visitVarArgInst(VarArgInst &I) {
- unsigned SrcReg = getReg(I.getOperand(0));
+void ISel::visitVANextInst(VANextInst &I) {
+ unsigned VAList = getReg(I.getOperand(0));
unsigned DestReg = getReg(I);
- // Load the va_list into a register...
- unsigned VAList = makeAnotherReg(Type::UIntTy);
- addDirectMem(BuildMI(BB, X86::MOVmr32, 4, VAList), SrcReg);
-
unsigned Size;
- switch (I.getType()->getPrimitiveID()) {
+ switch (I.getArgType()->getPrimitiveID()) {
default:
std::cerr << I;
- assert(0 && "Error: bad type for va_arg instruction!");
+ assert(0 && "Error: bad type for va_next instruction!");
return;
case Type::PointerTyID:
case Type::UIntTyID:
case Type::IntTyID:
Size = 4;
- addDirectMem(BuildMI(BB, X86::MOVmr32, 4, DestReg), VAList);
break;
case Type::ULongTyID:
case Type::LongTyID:
- Size = 8;
- addDirectMem(BuildMI(BB, X86::MOVmr32, 4, DestReg), VAList);
- addRegOffset(BuildMI(BB, X86::MOVmr32, 4, DestReg+1), VAList, 4);
- break;
case Type::DoubleTyID:
Size = 8;
- addDirectMem(BuildMI(BB, X86::FLDr64, 4, DestReg), VAList);
break;
}
// Increment the VAList pointer...
- unsigned NextVAList = makeAnotherReg(Type::UIntTy);
- BuildMI(BB, X86::ADDri32, 2, NextVAList).addReg(VAList).addZImm(Size);
-
- // Update the VAList in memory...
- addDirectMem(BuildMI(BB, X86::MOVrm32, 5), SrcReg).addReg(NextVAList);
+ BuildMI(BB, X86::ADDri32, 2, DestReg).addReg(VAList).addZImm(Size);
}
+void ISel::visitVAArgInst(VAArgInst &I) {
+ unsigned VAList = getReg(I.getOperand(0));
+ unsigned DestReg = getReg(I);
-// ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
-// returns zero when the input is not exactly a power of two.
-static unsigned ExactLog2(unsigned Val) {
- if (Val == 0) return 0;
- unsigned Count = 0;
- while (Val != 1) {
- if (Val & 1) return 0;
- Val >>= 1;
- ++Count;
+ switch (I.getType()->getPrimitiveID()) {
+ default:
+ std::cerr << I;
+ assert(0 && "Error: bad type for va_next instruction!");
+ return;
+ case Type::PointerTyID:
+ case Type::UIntTyID:
+ case Type::IntTyID:
+ addDirectMem(BuildMI(BB, X86::MOVmr32, 4, DestReg), VAList);
+ break;
+ case Type::ULongTyID:
+ case Type::LongTyID:
+ addDirectMem(BuildMI(BB, X86::MOVmr32, 4, DestReg), VAList);
+ addRegOffset(BuildMI(BB, X86::MOVmr32, 4, DestReg+1), VAList, 4);
+ break;
+ case Type::DoubleTyID:
+ addDirectMem(BuildMI(BB, X86::FLDr64, 4, DestReg), VAList);
+ break;
}
- return Count+1;
}
+
void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
unsigned outputReg = getReg(I);
MachineBasicBlock::iterator MI = BB->end();
} else {
unsigned idxReg = getReg(idx, MBB, IP);
unsigned OffsetReg = makeAnotherReg(Type::UIntTy);
- if (unsigned Shift = ExactLog2(elementSize)) {
- // If the element size is exactly a power of 2, use a shift to get it.
- BMI(MBB, IP, X86::SHLir32, 2,
- OffsetReg).addReg(idxReg).addZImm(Shift-1);
- } else {
- // Most general case, emit a multiply...
- unsigned elementSizeReg = makeAnotherReg(Type::LongTy);
- BMI(MBB, IP, X86::MOVir32, 1, elementSizeReg).addZImm(elementSize);
-
- // Emit a MUL to multiply the register holding the index by
- // elementSize, putting the result in OffsetReg.
- doMultiply(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSizeReg);
- }
+
+ doMultiplyConst(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSize);
+
// Emit an ADD to add OffsetReg to the basePtr.
NextReg = makeAnotherReg(Type::UIntTy);
BMI(MBB, IP, X86::ADDrr32, 2,NextReg).addReg(BaseReg).addReg(OffsetReg);
// constant by the variable amount.
unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
unsigned SrcReg1 = getReg(I.getArraySize());
- unsigned SizeReg = makeAnotherReg(Type::UIntTy);
- BuildMI(BB, X86::MOVir32, 1, SizeReg).addZImm(TySize);
// TotalSizeReg = mul <numelements>, <TypeSize>
MachineBasicBlock::iterator MBBI = BB->end();
- doMultiply(BB, MBBI, TotalSizeReg, Type::UIntTy, SrcReg1, SizeReg);
+ doMultiplyConst(BB, MBBI, TotalSizeReg, Type::UIntTy, SrcReg1, TySize);
// AddedSize = add <TotalSizeReg>, 15
unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy);
Arg = getReg(ConstantUInt::get(Type::UIntTy, C->getValue() * AllocSize));
} else {
Arg = makeAnotherReg(Type::UIntTy);
- unsigned Op0Reg = getReg(ConstantUInt::get(Type::UIntTy, AllocSize));
- unsigned Op1Reg = getReg(I.getOperand(0));
+ unsigned Op0Reg = getReg(I.getOperand(0));
MachineBasicBlock::iterator MBBI = BB->end();
- doMultiply(BB, MBBI, Arg, Type::UIntTy, Op0Reg, Op1Reg);
+ doMultiplyConst(BB, MBBI, Arg, Type::UIntTy, Op0Reg, AllocSize);
}
std::vector<ValueRecord> Args;
projects / oota-llvm.git / blobdiff