-//===-- FloatingPoint.cpp - Floating point Reg -> Stack converter ---------===//
-//
+//===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file defines the pass which converts floating point instructions from
#include "llvm/CodeGen/Passes.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
-#include "Support/Debug.h"
-#include "Support/DepthFirstIterator.h"
-#include "Support/Statistic.h"
-#include "Support/STLExtras.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/Compiler.h"
+#include "llvm/ADT/DepthFirstIterator.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/ADT/STLExtras.h"
#include <algorithm>
#include <set>
using namespace llvm;
namespace {
- Statistic<> NumFXCH("x86-codegen", "Number of fxch instructions inserted");
- Statistic<> NumFP ("x86-codegen", "Number of floating point instructions");
+ Statistic NumFXCH("x86-codegen", "Number of fxch instructions inserted");
+ Statistic NumFP ("x86-codegen", "Number of floating point instructions");
- struct FPS : public MachineFunctionPass {
+ struct VISIBILITY_HIDDEN FPS : public MachineFunctionPass {
virtual bool runOnMachineFunction(MachineFunction &MF);
virtual const char *getPassName() const { return "X86 FP Stackifier"; }
MachineFunctionPass::getAnalysisUsage(AU);
}
private:
- LiveVariables *LV; // Live variable info for current function...
- MachineBasicBlock *MBB; // Current basic block
- unsigned Stack[8]; // FP<n> Registers in each stack slot...
- unsigned RegMap[8]; // Track which stack slot contains each register
- unsigned StackTop; // The current top of the FP stack.
+ const TargetInstrInfo *TII; // Machine instruction info.
+ LiveVariables *LV; // Live variable info for current function...
+ MachineBasicBlock *MBB; // Current basic block
+ unsigned Stack[8]; // FP<n> Registers in each stack slot...
+ unsigned RegMap[8]; // Track which stack slot contains each register
+ unsigned StackTop; // The current top of the FP stack.
void dumpStack() const {
- std::cerr << "Stack contents:";
+ cerr << "Stack contents:";
for (unsigned i = 0; i != StackTop; ++i) {
- std::cerr << " FP" << Stack[i];
- assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
+ cerr << " FP" << Stack[i];
+ assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
}
- std::cerr << "\n";
+ cerr << "\n";
}
private:
// getSlot - Return the stack slot number a particular register number is
bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
void moveToTop(unsigned RegNo, MachineBasicBlock::iterator &I) {
if (!isAtTop(RegNo)) {
- unsigned Slot = getSlot(RegNo);
- unsigned STReg = getSTReg(RegNo);
- unsigned RegOnTop = getStackEntry(0);
+ unsigned STReg = getSTReg(RegNo);
+ unsigned RegOnTop = getStackEntry(0);
- // Swap the slots the regs are in
- std::swap(RegMap[RegNo], RegMap[RegOnTop]);
+ // Swap the slots the regs are in
+ std::swap(RegMap[RegNo], RegMap[RegOnTop]);
- // Swap stack slot contents
- assert(RegMap[RegOnTop] < StackTop);
- std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
+ // Swap stack slot contents
+ assert(RegMap[RegOnTop] < StackTop);
+ std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
- // Emit an fxch to update the runtime processors version of the state
- BuildMI(*MBB, I, X86::FXCH, 1).addReg(STReg);
- NumFXCH++;
+ // Emit an fxch to update the runtime processors version of the state
+ BuildMI(*MBB, I, TII->get(X86::FXCH)).addReg(STReg);
+ NumFXCH++;
}
}
unsigned STReg = getSTReg(RegNo);
pushReg(AsReg); // New register on top of stack
- BuildMI(*MBB, I, X86::FLDrr, 1).addReg(STReg);
+ BuildMI(*MBB, I, TII->get(X86::FLDrr)).addReg(STReg);
}
// popStackAfter - Pop the current value off of the top of the FP stack
/// register references into FP stack references.
///
bool FPS::runOnMachineFunction(MachineFunction &MF) {
+ // We only need to run this pass if there are any FP registers used in this
+ // function. If it is all integer, there is nothing for us to do!
+ const bool *PhysRegsUsed = MF.getUsedPhysregs();
+ bool FPIsUsed = false;
+
+ assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!");
+ for (unsigned i = 0; i <= 6; ++i)
+ if (PhysRegsUsed[X86::FP0+i]) {
+ FPIsUsed = true;
+ break;
+ }
+
+ // Early exit.
+ if (!FPIsUsed) return false;
+
+ TII = MF.getTarget().getInstrInfo();
LV = &getAnalysis<LiveVariables>();
StackTop = 0;
/// transforming FP instructions into their stack form.
///
bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
- const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
bool Changed = false;
MBB = &BB;
-
+
for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
MachineInstr *MI = I;
- unsigned Flags = TII.get(MI->getOpcode()).TSFlags;
+ unsigned Flags = MI->getInstrDescriptor()->TSFlags;
if ((Flags & X86II::FPTypeMask) == X86II::NotFP)
continue; // Efficiently ignore non-fp insts!
PrevMI = prior(I);
++NumFP; // Keep track of # of pseudo instrs
- DEBUG(std::cerr << "\nFPInst:\t";
- MI->print(std::cerr, MF.getTarget()));
+ DOUT << "\nFPInst:\t"; MI->print(*cerr.stream(), &(MF.getTarget()));
// Get dead variables list now because the MI pointer may be deleted as part
// of processing!
- LiveVariables::killed_iterator IB = LV->dead_begin(MI);
- LiveVariables::killed_iterator IE = LV->dead_end(MI);
-
- DEBUG(const MRegisterInfo *MRI = MF.getTarget().getRegisterInfo();
- LiveVariables::killed_iterator I = LV->killed_begin(MI);
- LiveVariables::killed_iterator E = LV->killed_end(MI);
- if (I != E) {
- std::cerr << "Killed Operands:";
- for (; I != E; ++I)
- std::cerr << " %" << MRI->getName(I->second);
- std::cerr << "\n";
- });
+ SmallVector<unsigned, 8> DeadRegs;
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ const MachineOperand &MO = MI->getOperand(i);
+ if (MO.isReg() && MO.isDead())
+ DeadRegs.push_back(MO.getReg());
+ }
switch (Flags & X86II::FPTypeMask) {
case X86II::ZeroArgFP: handleZeroArgFP(I); break;
case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0)
case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0))
- case X86II::TwoArgFP: handleTwoArgFP(I); break;
+ case X86II::TwoArgFP: handleTwoArgFP(I); break;
case X86II::CompareFP: handleCompareFP(I); break;
case X86II::CondMovFP: handleCondMovFP(I); break;
case X86II::SpecialFP: handleSpecialFP(I); break;
// Check to see if any of the values defined by this instruction are dead
// after definition. If so, pop them.
- for (; IB != IE; ++IB) {
- unsigned Reg = IB->second;
+ for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
+ unsigned Reg = DeadRegs[i];
if (Reg >= X86::FP0 && Reg <= X86::FP6) {
- DEBUG(std::cerr << "Register FP#" << Reg-X86::FP0 << " is dead!\n");
+ DOUT << "Register FP#" << Reg-X86::FP0 << " is dead!\n";
freeStackSlotAfter(I, Reg-X86::FP0);
}
}
-
+
// Print out all of the instructions expanded to if -debug
DEBUG(
MachineBasicBlock::iterator PrevI(PrevMI);
if (I == PrevI) {
- std::cerr << "Just deleted pseudo instruction\n";
+ cerr << "Just deleted pseudo instruction\n";
} else {
MachineBasicBlock::iterator Start = I;
// Rewind to first instruction newly inserted.
while (Start != BB.begin() && prior(Start) != PrevI) --Start;
- std::cerr << "Inserted instructions:\n\t";
- Start->print(std::cerr, MF.getTarget());
+ cerr << "Inserted instructions:\n\t";
+ Start->print(*cerr.stream(), &MF.getTarget());
while (++Start != next(I));
}
dumpStack();
unsigned from;
unsigned to;
bool operator<(const TableEntry &TE) const { return from < TE.from; }
- bool operator<(unsigned V) const { return from < V; }
+ friend bool operator<(const TableEntry &TE, unsigned V) {
+ return TE.from < V;
+ }
+ friend bool operator<(unsigned V, const TableEntry &TE) {
+ return V < TE.from;
+ }
};
}
#else
#define ASSERT_SORTED(TABLE) \
{ static bool TABLE##Checked = false; \
- if (!TABLE##Checked) \
+ if (!TABLE##Checked) { \
assert(TableIsSorted(TABLE, ARRAY_SIZE(TABLE)) && \
"All lookup tables must be sorted for efficient access!"); \
+ TABLE##Checked = true; \
+ } \
}
#endif
+//===----------------------------------------------------------------------===//
+// Register File -> Register Stack Mapping Methods
+//===----------------------------------------------------------------------===//
+
+// OpcodeTable - Sorted map of register instructions to their stack version.
+// The first element is an register file pseudo instruction, the second is the
+// concrete X86 instruction which uses the register stack.
+//
+static const TableEntry OpcodeTable[] = {
+ { X86::FpABS , X86::FABS },
+ { X86::FpADD32m , X86::FADD32m },
+ { X86::FpADD64m , X86::FADD64m },
+ { X86::FpCHS , X86::FCHS },
+ { X86::FpCMOVB , X86::FCMOVB },
+ { X86::FpCMOVBE , X86::FCMOVBE },
+ { X86::FpCMOVE , X86::FCMOVE },
+ { X86::FpCMOVNB , X86::FCMOVNB },
+ { X86::FpCMOVNBE , X86::FCMOVNBE },
+ { X86::FpCMOVNE , X86::FCMOVNE },
+ { X86::FpCMOVNP , X86::FCMOVNP },
+ { X86::FpCMOVP , X86::FCMOVP },
+ { X86::FpCOS , X86::FCOS },
+ { X86::FpDIV32m , X86::FDIV32m },
+ { X86::FpDIV64m , X86::FDIV64m },
+ { X86::FpDIVR32m , X86::FDIVR32m },
+ { X86::FpDIVR64m , X86::FDIVR64m },
+ { X86::FpIADD16m , X86::FIADD16m },
+ { X86::FpIADD32m , X86::FIADD32m },
+ { X86::FpIDIV16m , X86::FIDIV16m },
+ { X86::FpIDIV32m , X86::FIDIV32m },
+ { X86::FpIDIVR16m, X86::FIDIVR16m},
+ { X86::FpIDIVR32m, X86::FIDIVR32m},
+ { X86::FpILD16m , X86::FILD16m },
+ { X86::FpILD32m , X86::FILD32m },
+ { X86::FpILD64m , X86::FILD64m },
+ { X86::FpIMUL16m , X86::FIMUL16m },
+ { X86::FpIMUL32m , X86::FIMUL32m },
+ { X86::FpIST16m , X86::FIST16m },
+ { X86::FpIST32m , X86::FIST32m },
+ { X86::FpIST64m , X86::FISTP64m },
+ { X86::FpISTT16m , X86::FISTTP16m},
+ { X86::FpISTT32m , X86::FISTTP32m},
+ { X86::FpISTT64m , X86::FISTTP64m},
+ { X86::FpISUB16m , X86::FISUB16m },
+ { X86::FpISUB32m , X86::FISUB32m },
+ { X86::FpISUBR16m, X86::FISUBR16m},
+ { X86::FpISUBR32m, X86::FISUBR32m},
+ { X86::FpLD0 , X86::FLD0 },
+ { X86::FpLD1 , X86::FLD1 },
+ { X86::FpLD32m , X86::FLD32m },
+ { X86::FpLD64m , X86::FLD64m },
+ { X86::FpMUL32m , X86::FMUL32m },
+ { X86::FpMUL64m , X86::FMUL64m },
+ { X86::FpSIN , X86::FSIN },
+ { X86::FpSQRT , X86::FSQRT },
+ { X86::FpST32m , X86::FST32m },
+ { X86::FpST64m , X86::FST64m },
+ { X86::FpSUB32m , X86::FSUB32m },
+ { X86::FpSUB64m , X86::FSUB64m },
+ { X86::FpSUBR32m , X86::FSUBR32m },
+ { X86::FpSUBR64m , X86::FSUBR64m },
+ { X86::FpTST , X86::FTST },
+ { X86::FpUCOMIr , X86::FUCOMIr },
+ { X86::FpUCOMr , X86::FUCOMr },
+};
+
+static unsigned getConcreteOpcode(unsigned Opcode) {
+ ASSERT_SORTED(OpcodeTable);
+ int Opc = Lookup(OpcodeTable, ARRAY_SIZE(OpcodeTable), Opcode);
+ assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!");
+ return Opc;
+}
//===----------------------------------------------------------------------===//
// Helper Methods
// Check to see if there is a popping version of this instruction...
int Opcode = Lookup(PopTable, ARRAY_SIZE(PopTable), I->getOpcode());
if (Opcode != -1) {
- I->setOpcode(Opcode);
+ I->setInstrDescriptor(TII->get(Opcode));
if (Opcode == X86::FUCOMPPr)
I->RemoveOperand(0);
-
} else { // Insert an explicit pop
- I = BuildMI(*MBB, ++I, X86::FSTPrr, 1).addReg(X86::ST0);
+ I = BuildMI(*MBB, ++I, TII->get(X86::FSTPrr)).addReg(X86::ST0);
}
}
RegMap[TopReg] = OldSlot;
RegMap[FPRegNo] = ~0;
Stack[--StackTop] = ~0;
- I = BuildMI(*MBB, ++I, X86::FSTPrr, 1).addReg(STReg);
+ I = BuildMI(*MBB, ++I, TII->get(X86::FSTPrr)).addReg(STReg);
}
void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
MachineInstr *MI = I;
unsigned DestReg = getFPReg(MI->getOperand(0));
- MI->RemoveOperand(0); // Remove the explicit ST(0) operand
- // Result gets pushed on the stack...
+ // Change from the pseudo instruction to the concrete instruction.
+ MI->RemoveOperand(0); // Remove the explicit ST(0) operand
+ MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode())));
+
+ // Result gets pushed on the stack.
pushReg(DestReg);
}
///
void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
MachineInstr *MI = I;
- assert((MI->getNumOperands() == 5 || MI->getNumOperands() == 1) &&
+ unsigned NumOps = MI->getInstrDescriptor()->numOperands;
+ assert((NumOps == 5 || NumOps == 1) &&
"Can only handle fst* & ftst instructions!");
// Is this the last use of the source register?
- unsigned Reg = getFPReg(MI->getOperand(MI->getNumOperands()-1));
- bool KillsSrc = false;
- for (LiveVariables::killed_iterator KI = LV->killed_begin(MI),
- E = LV->killed_end(MI); KI != E; ++KI)
- KillsSrc |= KI->second == X86::FP0+Reg;
+ unsigned Reg = getFPReg(MI->getOperand(NumOps-1));
+ bool KillsSrc = LV->KillsRegister(MI, X86::FP0+Reg);
- // FSTP80r and FISTP64r are strange because there are no non-popping versions.
+ // FISTP64m is strange because there isn't a non-popping versions.
// If we have one _and_ we don't want to pop the operand, duplicate the value
// on the stack instead of moving it. This ensure that popping the value is
// always ok.
+ // Ditto FISTTP16m, FISTTP32m, FISTTP64m.
//
- if ((MI->getOpcode() == X86::FSTP80m ||
- MI->getOpcode() == X86::FISTP64m) && !KillsSrc) {
+ if (!KillsSrc &&
+ (MI->getOpcode() == X86::FpIST64m ||
+ MI->getOpcode() == X86::FpISTT16m ||
+ MI->getOpcode() == X86::FpISTT32m ||
+ MI->getOpcode() == X86::FpISTT64m)) {
duplicateToTop(Reg, 7 /*temp register*/, I);
} else {
moveToTop(Reg, I); // Move to the top of the stack...
}
- MI->RemoveOperand(MI->getNumOperands()-1); // Remove explicit ST(0) operand
- if (MI->getOpcode() == X86::FSTP80m || MI->getOpcode() == X86::FISTP64m) {
+ // Convert from the pseudo instruction to the concrete instruction.
+ MI->RemoveOperand(NumOps-1); // Remove explicit ST(0) operand
+ MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode())));
+
+ if (MI->getOpcode() == X86::FISTP64m ||
+ MI->getOpcode() == X86::FISTTP16m ||
+ MI->getOpcode() == X86::FISTTP32m ||
+ MI->getOpcode() == X86::FISTTP64m) {
assert(StackTop > 0 && "Stack empty??");
--StackTop;
} else if (KillsSrc) { // Last use of operand?
///
void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
MachineInstr *MI = I;
- assert(MI->getNumOperands() >= 2 && "FPRW instructions must have 2 ops!!");
+ unsigned NumOps = MI->getInstrDescriptor()->numOperands;
+ assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
// Is this the last use of the source register?
unsigned Reg = getFPReg(MI->getOperand(1));
- bool KillsSrc = false;
- for (LiveVariables::killed_iterator KI = LV->killed_begin(MI),
- E = LV->killed_end(MI); KI != E; ++KI)
- KillsSrc |= KI->second == X86::FP0+Reg;
+ bool KillsSrc = LV->KillsRegister(MI, X86::FP0+Reg);
if (KillsSrc) {
// If this is the last use of the source register, just make sure it's on
duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I);
}
+ // Change from the pseudo instruction to the concrete instruction.
MI->RemoveOperand(1); // Drop the source operand.
MI->RemoveOperand(0); // Drop the destination operand.
+ MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode())));
}
/// ST(i) = fsub ST(0), ST(i)
/// ST(0) = fsubr ST(0), ST(i)
/// ST(i) = fsubr ST(0), ST(i)
-///
+///
void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
MachineInstr *MI = I;
- unsigned NumOperands = MI->getNumOperands();
+ unsigned NumOperands = MI->getInstrDescriptor()->numOperands;
assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
unsigned Dest = getFPReg(MI->getOperand(0));
unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
- bool KillsOp0 = false, KillsOp1 = false;
-
- for (LiveVariables::killed_iterator KI = LV->killed_begin(MI),
- E = LV->killed_end(MI); KI != E; ++KI) {
- KillsOp0 |= (KI->second == X86::FP0+Op0);
- KillsOp1 |= (KI->second == X86::FP0+Op1);
- }
+ bool KillsOp0 = LV->KillsRegister(MI, X86::FP0+Op0);
+ bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1);
unsigned TOS = getStackEntry(0);
// Now we know that one of our operands is on the top of the stack, and at
// least one of our operands is killed by this instruction.
- assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) &&
- "Stack conditions not set up right!");
+ assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) &&
+ "Stack conditions not set up right!");
// We decide which form to use based on what is on the top of the stack, and
// which operand is killed by this instruction.
else
InstTable = ReverseSTiTable;
}
-
+
int Opcode = Lookup(InstTable, ARRAY_SIZE(ForwardST0Table), MI->getOpcode());
assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
// Replace the old instruction with a new instruction
MBB->remove(I++);
- I = BuildMI(*MBB, I, Opcode, 1).addReg(getSTReg(NotTOS));
+ I = BuildMI(*MBB, I, TII->get(Opcode)).addReg(getSTReg(NotTOS));
// If both operands are killed, pop one off of the stack in addition to
// overwriting the other one.
/// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP
/// register arguments and no explicit destinations.
-///
+///
void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
MachineInstr *MI = I;
- unsigned NumOperands = MI->getNumOperands();
+ unsigned NumOperands = MI->getInstrDescriptor()->numOperands;
assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
- bool KillsOp0 = false, KillsOp1 = false;
-
- for (LiveVariables::killed_iterator KI = LV->killed_begin(MI),
- E = LV->killed_end(MI); KI != E; ++KI) {
- KillsOp0 |= (KI->second == X86::FP0+Op0);
- KillsOp1 |= (KI->second == X86::FP0+Op1);
- }
+ bool KillsOp0 = LV->KillsRegister(MI, X86::FP0+Op0);
+ bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1);
// Make sure the first operand is on the top of stack, the other one can be
// anywhere.
moveToTop(Op0, I);
+ // Change from the pseudo instruction to the concrete instruction.
MI->getOperand(0).setReg(getSTReg(Op1));
MI->RemoveOperand(1);
+ MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode())));
// If any of the operands are killed by this instruction, free them.
if (KillsOp0) freeStackSlotAfter(I, Op0);
MachineInstr *MI = I;
unsigned Op0 = getFPReg(MI->getOperand(0));
- unsigned Op1 = getFPReg(MI->getOperand(1));
+ unsigned Op1 = getFPReg(MI->getOperand(2));
+ bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1);
// The first operand *must* be on the top of the stack.
moveToTop(Op0, I);
// Change the second operand to the stack register that the operand is in.
+ // Change from the pseudo instruction to the concrete instruction.
MI->RemoveOperand(0);
+ MI->RemoveOperand(1);
MI->getOperand(0).setReg(getSTReg(Op1));
-
+ MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode())));
+
// If we kill the second operand, make sure to pop it from the stack.
- if (Op0 != Op1)
- for (LiveVariables::killed_iterator KI = LV->killed_begin(MI),
- E = LV->killed_end(MI); KI != E; ++KI)
- if (KI->second == X86::FP0+Op1) {
- // Get this value off of the register stack.
- freeStackSlotAfter(I, Op1);
- break;
- }
+ if (Op0 != Op1 && KillsOp1) {
+ // Get this value off of the register stack.
+ freeStackSlotAfter(I, Op1);
+ }
}
case X86::FpMOV: {
unsigned SrcReg = getFPReg(MI->getOperand(1));
unsigned DestReg = getFPReg(MI->getOperand(0));
- bool KillsSrc = false;
- for (LiveVariables::killed_iterator KI = LV->killed_begin(MI),
- E = LV->killed_end(MI); KI != E; ++KI)
- KillsSrc |= KI->second == X86::FP0+SrcReg;
- if (KillsSrc) {
+ if (LV->KillsRegister(MI, X86::FP0+SrcReg)) {
// If the input operand is killed, we can just change the owner of the
// incoming stack slot into the result.
unsigned Slot = getSlot(SrcReg);
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