Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix and...

[oota-llvm.git] / lib / Target / X86 / MCTargetDesc / X86BaseInfo.h

diff --git a/lib/Target/X86/MCTargetDesc/X86BaseInfo.h b/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
index 5b1cf5a1a58b85d06faaeac69cbba7b2078aac0c..404a7e80e6ce971e80409d3dafdcc473b6d5bdae 100644 (file)
--- a/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
+++ b/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
@@ -355,6 +355,16 @@ namespace X86II {
     // XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions.
     XOPA = 22 << Op0Shift,
 
     // XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions.
     XOPA = 22 << Op0Shift,
 

+    // PD - Prefix code for packed double precision vector floating point
+    // operations performed in the SSE registers.
+    PD = 23 << Op0Shift,
+
+    // T8PD - Prefix before and after 0x0F. Combination of T8 and PD.
+    T8PD = 24 << Op0Shift,
+
+    // TAPD - Prefix before and after 0x0F. Combination of TA and PD.
+    TAPD = 25 << Op0Shift,
+

     //===------------------------------------------------------------------===//
     // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
     // They are used to specify GPRs and SSE registers, 64-bit operand size,
     //===------------------------------------------------------------------===//
     // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
     // They are used to specify GPRs and SSE registers, 64-bit operand size,