const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
- : LLVMTargetMachine(T, TT.isArch64Bit() ? "e-p:64:64-i64:64-n32:64-S128"
- : "e-p:32:32-i64:64-n32:64-S128",
+ : LLVMTargetMachine(T,
+ TT.isArch64Bit() ? "e-m:e-p:64:64-i64:64-n32:64-S128"
+ : "e-m:e-p:32:32-i64:64-n32:64-S128",
TT, CPU, FS, Options, RM, CM, OL),
TLOF(make_unique<WebAssemblyTargetObjectFile>()) {
// WebAssembly type-checks expressions, but a noreturn function with a return
// Prepare store instructions for register stackifying.
addPass(createWebAssemblyStoreResults());
-
- // Mark registers as representing wasm's expression stack.
- addPass(createWebAssemblyRegStackify());
- // The register coalescing pass has a bad interaction with COPY MIs which have
- // EXPR_STACK as an extra operand
- // disablePass(&RegisterCoalescerID);
}
void WebAssemblyPassConfig::addPostRegAlloc() {
// Fails with: should be run after register allocation.
disablePass(&MachineCopyPropagationID);
+ // Mark registers as representing wasm's expression stack.
+ addPass(createWebAssemblyRegStackify());
+
// Run the register coloring pass to reduce the total number of registers.
addPass(createWebAssemblyRegColoring());