: "e-p:32:32-i64:64-n32:64-S128",
TT, CPU, FS, Options, RM, CM, OL),
TLOF(make_unique<WebAssemblyTargetObjectFile>()) {
+ // WebAssembly type-checks expressions, but a noreturn function with a return
+ // type that doesn't match the context will cause a check failure. So we lower
+ // LLVM 'unreachable' to ISD::TRAP and then lower that to WebAssembly's
+ // 'unreachable' expression which is meant for that case.
+ this->Options.TrapUnreachable = true;
+
initAsmInfo();
// We need a reducible CFG, so disable some optimizations which tend to
}
FunctionPass *createTargetRegisterAllocator(bool) override;
- void addFastRegAlloc(FunctionPass *RegAllocPass) override;
- void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
void addIRPasses() override;
bool addPreISel() override;
bool addInstSelector() override;
bool addILPOpts() override;
void addPreRegAlloc() override;
- void addRegAllocPasses(bool Optimized);
void addPostRegAlloc() override;
void addPreSched2() override;
void addPreEmitPass() override;
} // end anonymous namespace
TargetIRAnalysis WebAssemblyTargetMachine::getTargetIRAnalysis() {
- return TargetIRAnalysis([this](Function &F) {
+ return TargetIRAnalysis([this](const Function &F) {
return TargetTransformInfo(WebAssemblyTTIImpl(this, F));
});
}
return nullptr; // No reg alloc
}
-void WebAssemblyPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
- assert(!RegAllocPass && "WebAssembly uses no regalloc!");
- addRegAllocPasses(false);
-}
-
-void WebAssemblyPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
- assert(!RegAllocPass && "WebAssembly uses no regalloc!");
- addRegAllocPasses(true);
-}
-
//===----------------------------------------------------------------------===//
// The following functions are called from lib/CodeGen/Passes.cpp to modify
// the CodeGen pass sequence.
void WebAssemblyPassConfig::addPreRegAlloc() {}
-void WebAssemblyPassConfig::addRegAllocPasses(bool Optimized) {
- // This is list is derived from the regalloc pass list used in
- // addFastRegAlloc and addOptimizedRegAlloc in lib/CodeGen/Passes.cpp. We
- // don't run the actual register allocator, but we do run the passes which
- // lower SSA form, so after these passes are complete, we have non-SSA
- // virtual registers.
-
- if (Optimized) {
- addPass(&ProcessImplicitDefsID);
- addPass(&LiveVariablesID);
- addPass(&MachineLoopInfoID);
- }
-
- addPass(&PHIEliminationID);
- addPass(&TwoAddressInstructionPassID, false);
-
- if (Optimized) {
- addPass(&RegisterCoalescerID);
- addPass(&MachineSchedulerID);
- }
-}
-
void WebAssemblyPassConfig::addPostRegAlloc() {
// FIXME: the following passes dislike virtual registers. Disable them for now
// so that basic tests can pass. Future patches will remedy this.
disablePass(&PrologEpilogCodeInserterID);
// Fails with: should be run after register allocation.
disablePass(&MachineCopyPropagationID);
+
+ // TODO: Until we get ReverseBranchCondition support, MachineBlockPlacement
+ // can create ugly-looking control flow.
+ disablePass(&MachineBlockPlacementID);
}
void WebAssemblyPassConfig::addPreSched2() {}
-void WebAssemblyPassConfig::addPreEmitPass() {}
+void WebAssemblyPassConfig::addPreEmitPass() {
+ addPass(createWebAssemblyCFGStackify());
+ addPass(createWebAssemblyRegNumbering());
+}