[WebAssembly] Initial varargs support.

[oota-llvm.git] / lib / Target / WebAssembly / WebAssemblyInstrInfo.cpp

diff --git a/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp b/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
index 19a65dc2a2f0f26c2951dec96720d13a62a22aa8..bd06bc396dcdd039a45ce16de287dc17ecbc8dfa 100644 (file)
--- a/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
+++ b/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
@@ -28,13 +28,30 @@ using namespace llvm;
 #include "WebAssemblyGenInstrInfo.inc"
 
 WebAssemblyInstrInfo::WebAssemblyInstrInfo(const WebAssemblySubtarget &STI)
-    : RI(STI.getTargetTriple()) {}
+    : WebAssemblyGenInstrInfo(WebAssembly::ADJCALLSTACKDOWN,
+                              WebAssembly::ADJCALLSTACKUP),
+      RI(STI.getTargetTriple()) {}
 
 void WebAssemblyInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                        MachineBasicBlock::iterator I,
                                        DebugLoc DL, unsigned DestReg,
                                        unsigned SrcReg, bool KillSrc) const {
-  BuildMI(MBB, I, DL, get(WebAssembly::COPY), DestReg)
+  const TargetRegisterClass *RC =
+      MBB.getParent()->getRegInfo().getRegClass(SrcReg);
+
+  unsigned CopyLocalOpcode;
+  if (RC == &WebAssembly::I32RegClass)
+    CopyLocalOpcode = WebAssembly::COPY_LOCAL_I32;
+  else if (RC == &WebAssembly::I64RegClass)
+    CopyLocalOpcode = WebAssembly::COPY_LOCAL_I64;
+  else if (RC == &WebAssembly::F32RegClass)
+    CopyLocalOpcode = WebAssembly::COPY_LOCAL_F32;
+  else if (RC == &WebAssembly::F64RegClass)
+    CopyLocalOpcode = WebAssembly::COPY_LOCAL_F64;
+  else
+    llvm_unreachable("Unexpected register class");
+
+  BuildMI(MBB, I, DL, get(CopyLocalOpcode), DestReg)
       .addReg(SrcReg, KillSrc ? RegState::Kill : 0);
 }
 
@@ -43,7 +60,7 @@ bool WebAssemblyInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
                                          MachineBasicBlock *&TBB,
                                          MachineBasicBlock *&FBB,
                                          SmallVectorImpl<MachineOperand> &Cond,
-                                         bool AllowModify) const {
+                                         bool /*AllowModify*/) const {
   bool HaveCond = false;
   for (MachineInstr &MI : iterator_range<MachineBasicBlock::instr_iterator>(
            MBB.getFirstInstrTerminator(), MBB.instr_end())) {
@@ -51,11 +68,11 @@ bool WebAssemblyInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
     default:
       // Unhandled instruction; bail out.
       return true;
-    case WebAssembly::BRIF:
+    case WebAssembly::BR_IF:
       if (HaveCond)
         return true;
-      Cond.push_back(MI.getOperand(1));
-      TBB = MI.getOperand(0).getMBB();
+      Cond.push_back(MI.getOperand(0));
+      TBB = MI.getOperand(1).getMBB();
       HaveCond = true;
       break;
     case WebAssembly::BR:
@@ -91,9 +108,11 @@ unsigned WebAssemblyInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
   return Count;
 }
 
-unsigned WebAssemblyInstrInfo::InsertBranch(
-    MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
-    ArrayRef<MachineOperand> Cond, DebugLoc DL) const {
+unsigned WebAssemblyInstrInfo::InsertBranch(MachineBasicBlock &MBB,
+                                            MachineBasicBlock *TBB,
+                                            MachineBasicBlock *FBB,
+                                            ArrayRef<MachineOperand> Cond,
+                                            DebugLoc DL) const {
   assert(Cond.size() <= 1);
 
   if (Cond.empty()) {
@@ -104,9 +123,7 @@ unsigned WebAssemblyInstrInfo::InsertBranch(
     return 1;
   }
 
-  BuildMI(&MBB, DL, get(WebAssembly::BRIF))
-      .addMBB(TBB)
-      .addOperand(Cond[0]);
+  BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addOperand(Cond[0]).addMBB(TBB);
   if (!FBB)
     return 1;