namespace {
// Diagnostic information for unimplemented or unsupported feature reporting.
-// FIXME copied from BPF and AMDGPU.
+// TODO: This code is copied from BPF and AMDGPU; consider factoring it out
+// and sharing code.
class DiagnosticInfoUnsupported final : public DiagnosticInfo {
private:
// Debug location where this diagnostic is triggered.
setOperationAction(Op, T, Expand);
// Note supported floating-point library function operators that otherwise
// default to expand.
- for (auto Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT,
- ISD::FRINT})
+ for (auto Op :
+ {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT})
setOperationAction(Op, T, Legal);
// Support minnan and maxnan, which otherwise default to expand.
setOperationAction(ISD::FMINNAN, T, Legal);
for (auto T : {MVT::i32, MVT::i64}) {
// Expand unavailable integer operations.
- for (auto Op : {ISD::BSWAP, ISD::ROTL, ISD::ROTR,
- ISD::SMUL_LOHI, ISD::UMUL_LOHI,
- ISD::MULHS, ISD::MULHU, ISD::SDIVREM, ISD::UDIVREM,
- ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS,
- ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) {
+ for (auto Op :
+ {ISD::BSWAP, ISD::ROTL, ISD::ROTR, ISD::SMUL_LOHI, ISD::UMUL_LOHI,
+ ISD::MULHS, ISD::MULHU, ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS,
+ ISD::SRA_PARTS, ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC,
+ ISD::SUBE}) {
setOperationAction(Op, T, Expand);
}
}
}
bool WebAssemblyTargetLowering::isOffsetFoldingLegal(
- const GlobalAddressSDNode *GA) const {
+ const GlobalAddressSDNode * /*GA*/) const {
// The WebAssembly target doesn't support folding offsets into global
// addresses.
return false;
}
-MVT WebAssemblyTargetLowering::getScalarShiftAmountTy(const DataLayout &DL,
+MVT WebAssemblyTargetLowering::getScalarShiftAmountTy(const DataLayout & /*DL*/,
EVT VT) const {
return VT.getSimpleVT();
}
if (Constraint.size() == 1) {
switch (Constraint[0]) {
case 'r':
- return std::make_pair(0U, &WebAssembly::I32RegClass);
+ if (VT == MVT::i32)
+ return std::make_pair(0U, &WebAssembly::I32RegClass);
+ if (VT == MVT::i64)
+ return std::make_pair(0U, &WebAssembly::I64RegClass);
+ break;
default:
break;
}
MachineFunction &MF = DAG.getMachineFunction();
CallingConv::ID CallConv = CLI.CallConv;
- if (CallConv != CallingConv::C &&
- CallConv != CallingConv::Fast &&
+ if (CallConv != CallingConv::C && CallConv != CallingConv::Fast &&
CallConv != CallingConv::Cold)
fail(DL, DAG,
"WebAssembly doesn't support language-specific or target-specific "
}
bool WebAssemblyTargetLowering::CanLowerReturn(
- CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
- const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
+ CallingConv::ID /*CallConv*/, MachineFunction & /*MF*/, bool /*IsVarArg*/,
+ const SmallVectorImpl<ISD::OutputArg> &Outs,
+ LLVMContext & /*Context*/) const {
// WebAssembly can't currently handle returning tuples.
return Outs.size() <= 1;
}
// Record the number and types of the return values.
for (const ISD::OutputArg &Out : Outs) {
- if (Out.Flags.isByVal())
- fail(DL, DAG, "WebAssembly hasn't implemented byval results");
+ assert(!Out.Flags.isByVal() && "byval is not valid for return values");
+ assert(!Out.Flags.isNest() && "nest is not valid for return values");
if (Out.Flags.isInAlloca())
fail(DL, DAG, "WebAssembly hasn't implemented inalloca results");
- if (Out.Flags.isNest())
- fail(DL, DAG, "WebAssembly hasn't implemented nest results");
if (Out.Flags.isInConsecutiveRegs())
fail(DL, DAG, "WebAssembly hasn't implemented cons regs results");
if (Out.Flags.isInConsecutiveRegsLast())
if (IsVarArg)
fail(DL, DAG, "WebAssembly doesn't support varargs yet");
+ // Set up the incoming ARGUMENTS value, which serves to represent the liveness
+ // of the incoming values before they're represented by virtual registers.
+ MF.getRegInfo().addLiveIn(WebAssembly::ARGUMENTS);
+
for (const ISD::InputArg &In : Ins) {
if (In.Flags.isByVal())
fail(DL, DAG, "WebAssembly hasn't implemented byval arguments");
fail(DL, DAG, "WebAssembly hasn't implemented cons regs arguments");
if (In.Flags.isInConsecutiveRegsLast())
fail(DL, DAG, "WebAssembly hasn't implemented cons regs last arguments");
- // FIXME Do something with In.getOrigAlign()?
+ // Ignore In.getOrigAlign() because all our arguments are passed in
+ // registers.
InVals.push_back(
In.Used
? DAG.getNode(WebAssemblyISD::ARGUMENT, DL, In.VT,
DAG.getTargetGlobalAddress(GA->getGlobal(), DL, VT));
}
-SDValue WebAssemblyTargetLowering::LowerExternalSymbol(SDValue Op,
- SelectionDAG &DAG) const {
+SDValue
+WebAssemblyTargetLowering::LowerExternalSymbol(SDValue Op,
+ SelectionDAG &DAG) const {
SDLoc DL(Op);
const auto *ES = cast<ExternalSymbolSDNode>(Op);
EVT VT = Op.getValueType();
//===----------------------------------------------------------------------===//
MCSection *WebAssemblyTargetObjectFile::SelectSectionForGlobal(
- const GlobalValue *GV, SectionKind Kind, Mangler &Mang,
- const TargetMachine &TM) const {
+ const GlobalValue *GV, SectionKind /*Kind*/, Mangler & /*Mang*/,
+ const TargetMachine & /*TM*/) const {
// TODO: Be more sophisticated than this.
return isa<Function>(GV) ? getTextSection() : getDataSection();
}