return MI;
}
-void TargetInstrInfo::PredicateInstruction(MachineInstr *MI,
- std::vector<MachineOperand> &Cond) const {
+bool TargetInstrInfo::PredicateInstruction(MachineInstr *MI,
+ const std::vector<MachineOperand> &Pred) const {
+ bool MadeChange = false;
const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
- assert((TID->Flags & M_PREDICABLE) &&
- "Predicating an unpredicable instruction!");
-
- for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
- if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
- MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg())
- MO.setReg(Cond[j].getReg());
- else if (MO.isImm())
- MO.setImm(Cond[j].getImmedValue());
- else if (MO.isMBB())
- MO.setMachineBasicBlock(Cond[j].getMachineBasicBlock());
- ++j;
+ if (TID->Flags & M_PREDICABLE) {
+ for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
+ MachineOperand &MO = MI->getOperand(i);
+ if (MO.isRegister()) {
+ MO.setReg(Pred[j].getReg());
+ MadeChange = true;
+ } else if (MO.isImmediate()) {
+ MO.setImm(Pred[j].getImmedValue());
+ MadeChange = true;
+ } else if (MO.isMachineBasicBlock()) {
+ MO.setMachineBasicBlock(Pred[j].getMachineBasicBlock());
+ MadeChange = true;
+ }
+ ++j;
+ }
}
}
+ return MadeChange;
+}
+
+bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
+ const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
+ if (TID->Flags & M_TERMINATOR_FLAG) {
+ // Conditional branch is a special case.
+ if ((TID->Flags & M_BRANCH_FLAG) != 0 && (TID->Flags & M_BARRIER_FLAG) == 0)
+ return true;
+ if ((TID->Flags & M_PREDICABLE) == 0)
+ return true;
+ return !isPredicated(MI);
+ }
+ return false;
}