for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg()) {
+ if (MO.isRegister()) {
MO.setReg(Pred[j].getReg());
MadeChange = true;
- } else if (MO.isImm()) {
+ } else if (MO.isImmediate()) {
MO.setImm(Pred[j].getImmedValue());
MadeChange = true;
- } else if (MO.isMBB()) {
+ } else if (MO.isMachineBasicBlock()) {
MO.setMachineBasicBlock(Pred[j].getMachineBasicBlock());
MadeChange = true;
}
}
return MadeChange;
}
+
+bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
+ const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
+ if (TID->Flags & M_TERMINATOR_FLAG) {
+ // Conditional branch is a special case.
+ if ((TID->Flags & M_BRANCH_FLAG) != 0 && (TID->Flags & M_BARRIER_FLAG) == 0)
+ return true;
+ if ((TID->Flags & M_PREDICABLE) == 0)
+ return true;
+ return !isPredicated(MI);
+ }
+ return false;
+}