//
//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-//
-// Value types - These values correspond to the register types defined in the
-// ValueTypes.h file. If you update anything here, you must update it there as
-// well!
-//
-class ValueType<int size, int value> {
- string Namespace = "MVT";
- int Size = size;
- int Value = value;
-}
-
-def OtherVT: ValueType<0 , 0>; // "Other" value
-def i1 : ValueType<1 , 1>; // One bit boolean value
-def i8 : ValueType<8 , 2>; // 8-bit integer value
-def i16 : ValueType<16 , 3>; // 16-bit integer value
-def i32 : ValueType<32 , 4>; // 32-bit integer value
-def i64 : ValueType<64 , 5>; // 64-bit integer value
-def i128 : ValueType<128, 6>; // 128-bit integer value
-def f32 : ValueType<32 , 7>; // 32-bit floating point value
-def f64 : ValueType<64 , 8>; // 64-bit floating point value
-def f80 : ValueType<80 , 9>; // 80-bit floating point value
-def f128 : ValueType<128, 10>; // 128-bit floating point value
-def FlagVT : ValueType<0 , 11>; // Condition code or machine flag
-def isVoid : ValueType<0 , 12>; // Produces no value
-def Vector : ValueType<0 , 13>; // Abstract vector type
+// Include all information about LLVM intrinsics.
+include "llvm/Intrinsics.td"
//===----------------------------------------------------------------------===//
// Register file description - These classes are used to fill in the target
int SpillAlignment = 0;
// Aliases - A list of registers that this register overlaps with. A read or
- // modification of this register can potentially read or modifie the aliased
+ // modification of this register can potentially read or modify the aliased
// registers.
- //
list<Register> Aliases = [];
+
+ // SubRegs - A list of registers that are parts of this register. Note these
+ // are "immediate" sub-registers and the registers within the list do not
+ // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
+ // not [AX, AH, AL].
+ list<Register> SubRegs = [];
+
+ // DwarfNumber - Number used internally by gcc/gdb to identify the register.
+ // These values can be determined by locating the <target>.h file in the
+ // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
+ // order of these names correspond to the enumeration used by gcc. A value of
+ // -1 indicates that the gcc number is undefined.
+ int DwarfNumber = -1;
}
-// RegisterGroup - This can be used to define instances of Register which
-// need to specify aliases.
-// List "aliases" specifies which registers are aliased to this one. This
-// allows the code generator to be careful not to put two values with
+// RegisterWithSubRegs - This can be used to define instances of Register which
+// need to specify sub-registers.
+// List "subregs" specifies which registers are sub-registers to this one. This
+// is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
+// This allows the code generator to be careful not to put two values with
// overlapping live ranges into registers which alias.
-class RegisterGroup<string n, list<Register> aliases> : Register<n> {
- let Aliases = aliases;
+class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
+ let SubRegs = subregs;
+}
+
+// SubRegSet - This can be used to define a specific mapping of registers to
+// indices, for use as named subregs of a particular physical register. Each
+// register in 'subregs' becomes an addressable subregister at index 'n' of the
+// corresponding register in 'regs'.
+class SubRegSet<int n, list<Register> regs, list<Register> subregs> {
+ int index = n;
+
+ list<Register> From = regs;
+ list<Register> To = subregs;
}
// RegisterClass - Now that all of the registers are defined, and aliases
// register classes. This also defines the default allocation order of
// registers by register allocators.
//
-class RegisterClass<string namespace, ValueType regType, int alignment,
+class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
list<Register> regList> {
string Namespace = namespace;
- // RegType - Specify the ValueType of the registers in this register class.
- // Note that all registers in a register class must have the same ValueType.
+ // RegType - Specify the list ValueType of the registers in this register
+ // class. Note that all registers in a register class must have the same
+ // ValueTypes. This is a list because some targets permit storing different
+ // types in same register, for example vector values with 128-bit total size,
+ // but different count/size of items, like SSE on x86.
//
- ValueType RegType = regType;
+ list<ValueType> RegTypes = regTypes;
+
+ // Size - Specify the spill size in bits of the registers. A default value of
+ // zero lets tablgen pick an appropriate size.
+ int Size = 0;
// Alignment - Specify the alignment required of the registers when they are
// stored or loaded to memory.
//
- int Size = RegType.Size;
int Alignment = alignment;
+ // CopyCost - This value is used to specify the cost of copying a value
+ // between two registers in this register class. The default value is one
+ // meaning it takes a single instruction to perform the copying. A negative
+ // value means copying is extremely expensive or impossible.
+ int CopyCost = 1;
+
// MemberList - Specify which registers are in this class. If the
// allocation_order_* method are not specified, this also defines the order of
// allocation used by the register allocator.
//
list<Register> MemberList = regList;
+
+ // SubClassList - Specify which register classes correspond to subregisters
+ // of this class. The order should be by subregister set index.
+ list<RegisterClass> SubRegClassList = [];
// MethodProtos/MethodBodies - These members can be used to insert arbitrary
// code into a generated register class. The normal usage of this is to
}
+//===----------------------------------------------------------------------===//
+// DwarfRegNum - This class provides a mapping of the llvm register enumeration
+// to the register numbering used by gcc and gdb. These values are used by a
+// debug information writer (ex. DwarfWriter) to describe where values may be
+// located during execution.
+class DwarfRegNum<int N> {
+ // DwarfNumber - Number used internally by gcc/gdb to identify the register.
+ // These values can be determined by locating the <target>.h file in the
+ // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
+ // order of these names correspond to the enumeration used by gcc. A value of
+ // -1 indicates that the gcc number is undefined.
+ int DwarfNumber = N;
+}
+
//===----------------------------------------------------------------------===//
// Pull in the common support for scheduling
//
-include "../TargetSchedule.td"
+include "TargetSchedule.td"
+class Predicate; // Forward def
//===----------------------------------------------------------------------===//
// Instruction set description - These classes correspond to the C++ classes in
string Name = ""; // The opcode string for this instruction
string Namespace = "";
- dag OperandList; // An dag containing the MI operand list.
+ dag OutOperandList; // An dag containing the MI def operand list.
+ dag InOperandList; // An dag containing the MI use operand list.
string AsmString = ""; // The .s format to print the instruction with.
// Pattern - Set to the DAG pattern for this instruction, if we know of one,
list<Register> Uses = []; // Default to using no non-operand registers
list<Register> Defs = []; // Default to modifying no non-operand registers
+ // Predicates - List of predicates which will be turned into isel matching
+ // code.
+ list<Predicate> Predicates = [];
+
+ // Code size.
+ int CodeSize = 0;
+
+ // Added complexity passed onto matching pattern.
+ int AddedComplexity = 0;
+
// These bits capture information about the high-level semantics of the
// instruction.
bit isReturn = 0; // Is this instruction a return instruction?
bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
bit isCommutable = 0; // Is this 3 operand instruction commutable?
bit isTerminator = 0; // Is this part of the terminator for a basic block?
+ bit isReMaterializable = 0; // Is this instruction re-materializable?
+ bit isPredicable = 0; // Is this instruction predicable?
bit hasDelaySlot = 0; // Does this instruction have an delay slot?
bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
+ bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
+ bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
+
+ InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
+
+ string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
- InstrItinClass Itinerary; // Execution steps used for scheduling.
+ /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
+ /// be encoded into the output machineinstr.
+ string DisableEncoding = "";
}
+/// Predicates - These are extra conditionals which are turned into instruction
+/// selector matching code. Currently each predicate is just a string.
+class Predicate<string cond> {
+ string CondString = cond;
+}
+
+/// NoHonorSignDependentRounding - This predicate is true if support for
+/// sign-dependent-rounding is not enabled.
+def NoHonorSignDependentRounding
+ : Predicate<"!HonorSignDependentRoundingFPMath()">;
+
+class Requires<list<Predicate> preds> {
+ list<Predicate> Predicates = preds;
+}
/// ops definition - This is just a simple marker used to identify the operands
-/// list for an instruction. This should be used like this:
-/// (ops R32:$dst, R32:$src) or something similar.
+/// list for an instruction. outs and ins are identical both syntatically and
+/// semantically, they are used to define def operands and use operands to
+/// improve readibility. This should be used like this:
+/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
def ops;
+def outs;
+def ins;
/// variable_ops definition - Mark this instruction as taking a variable number
/// of operands.
def variable_ops;
+/// ptr_rc definition - Mark this operand as being a pointer value whose
+/// register class is resolved dynamically via a callback to TargetInstrInfo.
+/// FIXME: We should probably change this to a class which contain a list of
+/// flags. But currently we have but one flag.
+def ptr_rc;
+
/// Operand Types - These provide the built-in operand types that may be used
/// by a target. Targets can optionally provide their own operand types as
/// needed, though this should not be needed for RISC targets.
class Operand<ValueType ty> {
ValueType Type = ty;
string PrintMethod = "printOperand";
- int NumMIOperands = 1;
dag MIOperandInfo = (ops);
}
def i32imm : Operand<i32>;
def i64imm : Operand<i64>;
+/// zero_reg definition - Special node to stand for the zero register.
+///
+def zero_reg;
+
+/// PredicateOperand - This can be used to define a predicate operand for an
+/// instruction. OpTypes specifies the MIOperandInfo for the operand, and
+/// AlwaysVal specifies the value of this predicate when set to "always
+/// execute".
+class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
+ : Operand<ty> {
+ let MIOperandInfo = OpTypes;
+ dag DefaultOps = AlwaysVal;
+}
+
+/// OptionalDefOperand - This is used to define a optional definition operand
+/// for an instruction. DefaultOps is the register the operand represents if none
+/// is supplied, e.g. zero_reg.
+class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
+ : Operand<ty> {
+ let MIOperandInfo = OpTypes;
+ dag DefaultOps = defaultops;
+}
+
+
// InstrInfo - This class should only be instantiated once to provide parameters
// which are global to the the target machine.
//
class InstrInfo {
- Instruction PHIInst;
-
// If the target wants to associate some target-specific information with each
// instruction, it should provide these two lists to indicate how to assemble
// the target specific information into the 32 bits available.
bit isLittleEndianEncoding = 0;
}
+// Standard Instructions.
+def PHI : Instruction {
+ let OutOperandList = (ops);
+ let InOperandList = (ops variable_ops);
+ let AsmString = "PHINODE";
+ let Namespace = "TargetInstrInfo";
+}
+def INLINEASM : Instruction {
+ let OutOperandList = (ops);
+ let InOperandList = (ops variable_ops);
+ let AsmString = "";
+ let Namespace = "TargetInstrInfo";
+}
+def LABEL : Instruction {
+ let OutOperandList = (ops);
+ let InOperandList = (ops i32imm:$id);
+ let AsmString = "";
+ let Namespace = "TargetInstrInfo";
+ let hasCtrlDep = 1;
+}
+def EXTRACT_SUBREG : Instruction {
+ let OutOperandList = (ops variable_ops);
+ let InOperandList = (ops variable_ops);
+ let AsmString = "";
+ let Namespace = "TargetInstrInfo";
+}
+def INSERT_SUBREG : Instruction {
+ let OutOperandList = (ops variable_ops);
+ let InOperandList = (ops variable_ops);
+ let AsmString = "";
+ let Namespace = "TargetInstrInfo";
+}
+
//===----------------------------------------------------------------------===//
// AsmWriter - This class can be implemented by targets that need to customize
// the format of the .s file writer.
// Target - This class contains the "global" target information
//
class Target {
- // CalleeSavedRegisters - As you might guess, this is a list of the callee
- // saved registers for a target.
- list<Register> CalleeSavedRegisters = [];
-
- // PointerType - Specify the value type to be used to represent pointers in
- // this target. Typically this is an i32 or i64 type.
- ValueType PointerType;
-
// InstructionSet - Instruction set description for this target.
InstrInfo InstructionSet;
//===----------------------------------------------------------------------===//
// SubtargetFeature - A characteristic of the chip set.
//
-class SubtargetFeature<string n, string t, string a, string d> {
+class SubtargetFeature<string n, string a, string v, string d,
+ list<SubtargetFeature> i = []> {
// Name - Feature name. Used by command line (-mattr=) to determine the
// appropriate target chip.
//
string Name = n;
- // Type - Type of attribute to be set by feature.
- //
- string Type = t;
-
// Attribute - Attribute to be set by feature.
//
string Attribute = a;
+ // Value - Value the attribute to be set to by feature.
+ //
+ string Value = v;
+
// Desc - Feature description. Used by command line (-mattr=) to display help
// information.
//
string Desc = d;
+
+ // Implies - Features that this feature implies are present. If one of those
+ // features isn't set, then this one shouldn't be set either.
+ //
+ list<SubtargetFeature> Implies = i;
}
//===----------------------------------------------------------------------===//
}
//===----------------------------------------------------------------------===//
-// Pull in the common support for DAG isel generation
+// Pull in the common support for calling conventions.
+//
+include "TargetCallingConv.td"
+
+//===----------------------------------------------------------------------===//
+// Pull in the common support for DAG isel generation.
//
-include "../TargetSelectionDAG.td"
+include "TargetSelectionDAG.td"
projects / oota-llvm.git / blobdiff