Fix imm printing for logical instructions.

[oota-llvm.git] / lib / Target / SystemZ / SystemZOperands.td

diff --git a/lib/Target/SystemZ/SystemZOperands.td b/lib/Target/SystemZ/SystemZOperands.td
index 446e426abfea58d419be915a54f0e64dc8ae34ea..8b835cc26e299e9fc072753463ea6fcb376d1a56 100644 (file)
--- a/lib/Target/SystemZ/SystemZOperands.td
+++ b/lib/Target/SystemZ/SystemZOperands.td
@@ -17,12 +17,25 @@
 
 // SystemZ specific condition code. These correspond to CondCode in
 // SystemZ.h. They must be kept in synch.
-def SYSTEMZ_COND_E  : PatLeaf<(i8 0)>;
-def SYSTEMZ_COND_NE : PatLeaf<(i8 1)>;
-def SYSTEMZ_COND_H  : PatLeaf<(i8 2)>;
-def SYSTEMZ_COND_L  : PatLeaf<(i8 3)>;
-def SYSTEMZ_COND_HE : PatLeaf<(i8 4)>;
-def SYSTEMZ_COND_LE : PatLeaf<(i8 5)>;
+def SYSTEMZ_COND_O   : PatLeaf<(i8 0)>;
+def SYSTEMZ_COND_H   : PatLeaf<(i8 1)>;
+def SYSTEMZ_COND_NLE : PatLeaf<(i8 2)>;
+def SYSTEMZ_COND_L   : PatLeaf<(i8 3)>;
+def SYSTEMZ_COND_NHE : PatLeaf<(i8 4)>;
+def SYSTEMZ_COND_LH  : PatLeaf<(i8 5)>;
+def SYSTEMZ_COND_NE  : PatLeaf<(i8 6)>;
+def SYSTEMZ_COND_E   : PatLeaf<(i8 7)>;
+def SYSTEMZ_COND_NLH : PatLeaf<(i8 8)>;
+def SYSTEMZ_COND_HE  : PatLeaf<(i8 9)>;
+def SYSTEMZ_COND_NL  : PatLeaf<(i8 10)>;
+def SYSTEMZ_COND_LE  : PatLeaf<(i8 11)>;
+def SYSTEMZ_COND_NH  : PatLeaf<(i8 12)>;
+def SYSTEMZ_COND_NO  : PatLeaf<(i8 13)>;
+
+def LO8 : SDNodeXForm<imm, [{
+  // Transformation function: return low 8 bits.
+  return getI8Imm(N->getZExtValue() & 0x00000000000000FFULL);
+}]>;
 
 def LL16 : SDNodeXForm<imm, [{
   // Transformation function: return low 16 bits.
@@ -54,6 +67,10 @@ def HI32 : SDNodeXForm<imm, [{
   return getI32Imm(N->getZExtValue() >> 32);
 }]>;
 
+def GetI64FromI32 : SDNodeXForm<imm, [{
+  return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i64);
+}]>;
+
 def i32ll16 : PatLeaf<(i32 imm), [{
   // i32ll16 predicate - true if the 32-bit immediate has only rightmost 16
   // bits set.
@@ -130,14 +147,14 @@ def immSExt16 : PatLeaf<(imm), [{
   }
 
   return false;
-}]>;
+}], LL16>;
 
 def immSExt32 : PatLeaf<(i64 imm), [{
   // immSExt32 predicate - true if the immediate fits in a 32-bit sign extended
   // field.
   uint64_t val = N->getZExtValue();
   return ((int64_t)val == (int32_t)val);
-}]>;
+}], LO32>;
 
 def i64lo32 : PatLeaf<(i64 imm), [{
   // i64lo32 predicate - true if the 64-bit immediate has only rightmost 32
@@ -165,25 +182,25 @@ def i32immSExt8  : PatLeaf<(i32 imm), [{
   // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
   // sign extended field.
   return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
-}]>;
+}], LO8>;
 
 def i32immSExt16 : PatLeaf<(i32 imm), [{
   // i32immSExt16 predicate - True if the 32-bit immediate fits in a 16-bit
   // sign extended field.
   return (int32_t)N->getZExtValue() == (int16_t)N->getZExtValue();
-}]>;
+}], LL16>;
 
 def i64immSExt32 : PatLeaf<(i64 imm), [{
   // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
   // sign extended field.
   return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
-}]>;
+}], LO32>;
 
 def i64immZExt32 : PatLeaf<(i64 imm), [{
   // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
   // zero extended field.
   return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
-}]>;
+}], LO32>;
 
 // extloads
 def extloadi32i8   : PatFrag<(ops node:$ptr), (i32 (extloadi8  node:$ptr))>;
@@ -214,10 +231,14 @@ def i64i32imm : Operand<i64>;
 // Branch targets have OtherVT type.
 def brtarget : Operand<OtherVT>;
 
-// Unigned i12
+// Unsigned i12
 def u12imm : Operand<i32> {
-  let PrintMethod = "printU16ImmOperand";
+  let PrintMethod = "printU12ImmOperand";
+}
+def u12imm64 : Operand<i64> {
+  let PrintMethod = "printU12ImmOperand";
 }
+
 // Signed i16
 def s16imm : Operand<i32> {
   let PrintMethod = "printS16ImmOperand";
@@ -225,6 +246,14 @@ def s16imm : Operand<i32> {
 def s16imm64 : Operand<i64> {
   let PrintMethod = "printS16ImmOperand";
 }
+// Unsigned i16
+def u16imm : Operand<i32> {
+  let PrintMethod = "printU16ImmOperand";
+}
+def u16imm64 : Operand<i64> {
+  let PrintMethod = "printU16ImmOperand";
+}
+
 // Signed i20
 def s20imm : Operand<i32> {
   let PrintMethod = "printS20ImmOperand";
@@ -239,6 +268,17 @@ def s32imm : Operand<i32> {
 def s32imm64 : Operand<i64> {
   let PrintMethod = "printS32ImmOperand";
 }
+// Unsigned i32
+def u32imm : Operand<i32> {
+  let PrintMethod = "printU32ImmOperand";
+}
+def u32imm64 : Operand<i64> {
+  let PrintMethod = "printU32ImmOperand";
+}
+
+def imm_pcrel : Operand<i64> {
+  let PrintMethod = "printPCRelImmOperand";
+}
 
 //===----------------------------------------------------------------------===//
 // SystemZ Operand Definitions.
@@ -247,10 +287,16 @@ def s32imm64 : Operand<i64> {
 // Address operands
 
 // riaddr := reg + imm
-def riaddr32 : Operand<i32>,
-               ComplexPattern<i32, 2, "SelectAddrRI32", []> {
+def riaddr32 : Operand<i64>,
+               ComplexPattern<i64, 2, "SelectAddrRI12Only", []> {
   let PrintMethod = "printRIAddrOperand";
-  let MIOperandInfo = (ops ADDR32:$base, u12imm:$disp);
+  let MIOperandInfo = (ops ADDR64:$base, u12imm:$disp);
+}
+
+def riaddr12 : Operand<i64>,
+               ComplexPattern<i64, 2, "SelectAddrRI12", []> {
+  let PrintMethod = "printRIAddrOperand";
+  let MIOperandInfo = (ops ADDR64:$base, u12imm64:$disp);
 }
 
 def riaddr : Operand<i64>,
@@ -262,8 +308,13 @@ def riaddr : Operand<i64>,
 //===----------------------------------------------------------------------===//
 
 // rriaddr := reg + reg + imm
+def rriaddr12 : Operand<i64>,
+                ComplexPattern<i64, 3, "SelectAddrRRI12", [], []> {
+  let PrintMethod = "printRRIAddrOperand";
+  let MIOperandInfo = (ops ADDR64:$base, u12imm64:$disp, ADDR64:$index);
+}
 def rriaddr : Operand<i64>,
-              ComplexPattern<i64, 3, "SelectAddrRRI", [], []> {
+              ComplexPattern<i64, 3, "SelectAddrRRI20", [], []> {
   let PrintMethod = "printRRIAddrOperand";
   let MIOperandInfo = (ops ADDR64:$base, s20imm64:$disp, ADDR64:$index);
 }