Add infrastructure for support of multiple memory constraints.

[oota-llvm.git] / lib / Target / SystemZ / SystemZISelDAGToDAG.cpp

diff --git a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
index b8b0db9e8c712dc4677f9ceb26d8f8a2756ae6f9..cd0cac69c9bee4929116919937c747239e249d52 100644 (file)
--- a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
+++ b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
@@ -328,7 +328,7 @@ public:
 
   // Override SelectionDAGISel.
   SDNode *Select(SDNode *Node) override;
-  bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
+  bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
                                     std::vector<SDValue> &OutOps) override;
 
   // Include the pieces autogenerated from the target description.
@@ -1129,9 +1129,10 @@ SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) {
 
 bool SystemZDAGToDAGISel::
 SelectInlineAsmMemoryOperand(const SDValue &Op,
-                             char ConstraintCode,
+                             unsigned ConstraintID,
                              std::vector<SDValue> &OutOps) {
-  assert(ConstraintCode == 'm' && "Unexpected constraint code");
+  assert(ConstraintID == InlineAsm::Constraint_m &&
+         "Unexpected constraint code");
   // Accept addresses with short displacements, which are compatible
   // with Q, R, S and T.  But keep the index operand for future expansion.
   SDValue Base, Disp, Index;