-/* Title: SparcRegClassInfo.h -*- C++ -*-
- Author: Ruchira Sasanka
- Date: Aug 20, 01
- Purpose: Contains the description of integer register class of Sparc
-*/
-
-
-#ifndef SPARC_REG_INFO_CLASS_H
-#define SPARC_REG_INFO_CLASS_H
-
-#include "llvm/Target/MachineRegInfo.h"
-#include "llvm/CodeGen/IGNode.h"
+//===-- SparcRegClassInfo.h - Register class def'ns for Sparc ---*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the register classes used by the Sparc target description.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef SPARC_REG_CLASS_INFO_H
+#define SPARC_REG_CLASS_INFO_H
+
+#include "llvm/Target/TargetRegInfo.h"
//-----------------------------------------------------------------------------
// Integer Register Class
//-----------------------------------------------------------------------------
+struct SparcIntRegClass : public TargetRegClassInfo {
+ SparcIntRegClass(unsigned ID)
+ : TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) { }
-// Int register names in same order as enum in class SparcIntRegOrder
-
-static string const IntRegNames[] =
- {
- "o0", "o1", "o2", "o3", "o4", "o5", "o7",
- "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
- "i0", "i1", "i2", "i3", "i4", "i5",
- "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
- "i6", "i7", "o6" };
-
-
+ void colorIGNode(IGNode *Node,
+ const std::vector<bool> &IsColorUsedArr) const;
-class SparcIntRegOrder{
+ inline bool isRegVolatile(int Reg) const {
+ return (Reg < (int)StartOfNonVolatileRegs);
+ }
- public:
+ inline bool modifiedByCall(int Reg) const {
+ return Reg==(int)ModifiedByCall;
+ }
- enum RegsInPrefOrder // colors possible for a LR (in preferred order)
- {
+ enum { // colors possible for a LR (in preferred order)
// --- following colors are volatile across function calls
// %g0 can't be used for coloring - always 0
-
- //%g1-%g5 (g6-7 are reserved for system)
o0, o1, o2, o3, o4, o5, o7, // %o0-%o5,
// %o6 is sp,
// all %0's can get modified by a call
// --- following colors are NON-volatile across function calls
-
l0, l1, l2, l3, l4, l5, l6, l7, // %l0-%l7
i0, i1, i2, i3, i4, i5, // %i0-%i5: i's need not be preserved
// --- following colors are not available for allocation within this phase
// --- but can appear for pre-colored ranges
- g0, g1, g2, g3, g4, g5, g6, g7, i6, i7, o6
+ i6, i7, g0, g1, g2, g3, g4, g5, g6, g7, o6,
-
+ NumOfAllRegs, // Must be first AFTER registers...
+
+ //*** NOTE: If we decide to use some %g regs, they are volatile
+ // (see sparc64ABI)
+ // Move the %g regs from the end of the enumeration to just above the
+ // enumeration of %o0 (change StartOfAllRegs below)
+ // change isRegVloatile method below
+ // Also change IntRegNames above.
- };
+ // max # of colors reg coloring can allocate
+ NumOfAvailRegs = i6,
- // max # of colors reg coloring can allocate
- static unsigned int const NumOfAvailRegs = g0;
-
- static unsigned int const StartOfNonVolatileRegs = l0;
- static unsigned int const StartOfAllRegs = o0;
- static unsigned int const NumOfAllRegs = o6 + 1;
-
-
- static const string getRegName(const unsigned reg) {
- assert( reg < NumOfAllRegs );
- return IntRegNames[reg];
- }
+ StartOfNonVolatileRegs = l0,
+ StartOfAllRegs = o0,
+
+ ModifiedByCall = o7,
+ };
+ const char * const getRegName(unsigned reg) const;
};
-class SparcIntRegClass : public MachineRegClassInfo
-{
- public:
-
- SparcIntRegClass(unsigned ID)
- : MachineRegClassInfo(ID,
- SparcIntRegOrder::NumOfAvailRegs,
- SparcIntRegOrder::NumOfAllRegs)
- { }
-
- void colorIGNode(IGNode * Node, bool IsColorUsedArr[] ) const;
-
-};
//-----------------------------------------------------------------------------
// Float Register Class
//-----------------------------------------------------------------------------
-static string const FloatRegNames[] =
- {
- "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",
- "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19",
- "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29",
- "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
- "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49",
- "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59",
- "f60", "f61", "f62", "f63"
- };
-
-
-class SparcFloatRegOrder{
-
- public:
-
- enum RegsInPrefOrder {
-
+class SparcFloatRegClass : public TargetRegClassInfo {
+ int findFloatColor(const LiveRange *LR, unsigned Start,
+ unsigned End,
+ const std::vector<bool> &IsColorUsedArr) const;
+public:
+ SparcFloatRegClass(unsigned ID)
+ : TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) {}
+
+ // This method marks the registers used for a given register number.
+ // This marks a single register for Float regs, but the R,R+1 pair
+ // for double-precision registers.
+ //
+ virtual void markColorsUsed(unsigned RegInClass,
+ int UserRegType,
+ int RegTypeWanted,
+ std::vector<bool> &IsColorUsedArr) const;
+
+ // This method finds unused registers of the specified register type,
+ // using the given "used" flag array IsColorUsedArr. It checks a single
+ // entry in the array directly for float regs, and checks the pair [R,R+1]
+ // for double-precision registers
+ // It returns -1 if no unused color is found.
+ //
+ virtual int findUnusedColor(int RegTypeWanted,
+ const std::vector<bool> &IsColorUsedArr) const;
+
+ void colorIGNode(IGNode *Node,
+ const std::vector<bool> &IsColorUsedArr) const;
+
+ // according to Sparc 64 ABI, all %fp regs are volatile
+ inline bool isRegVolatile(int Reg) const { return true; }
+
+ enum {
f0, f1, f2, f3, f4, f5, f6, f7, f8, f9,
f10, f11, f12, f13, f14, f15, f16, f17, f18, f19,
f20, f21, f22, f23, f24, f25, f26, f27, f28, f29,
f30, f31, f32, f33, f34, f35, f36, f37, f38, f39,
f40, f41, f42, f43, f44, f45, f46, f47, f48, f49,
f50, f51, f52, f53, f54, f55, f56, f57, f58, f59,
- f60, f61, f62, f63
-
- };
-
- // there are 64 regs alltogether but only 32 regs can be allocated at
- // a time.
-
- static unsigned int const NumOfAvailRegs = 32;
- static unsigned int const NumOfAllRegs = 64;
-
- static unsigned int const StartOfNonVolatileRegs = f32;
- static unsigned int const StartOfAllRegs = f0;
-
-
- static const string getRegName(const unsigned reg) {
- assert( reg < NumOfAllRegs );
- return FloatRegNames[reg];
- }
-
+ f60, f61, f62, f63,
+ // there are 64 regs alltogether but only 32 regs can be allocated at
+ // a time.
+ //
+ NumOfAvailRegs = 32,
+ NumOfAllRegs = 64,
-};
-
-
-
-class SparcFloatRegClass : public MachineRegClassInfo
-{
- private:
-
- int findFloatColor(const LiveRange *const LR, unsigned Start,
- unsigned End, bool IsColorUsedArr[] ) const;
-
- public:
-
- SparcFloatRegClass(unsigned ID)
- : MachineRegClassInfo(ID,
- SparcFloatRegOrder::NumOfAvailRegs,
- SparcFloatRegOrder::NumOfAllRegs)
- { }
-
- void colorIGNode(IGNode * Node, bool IsColorUsedArr[] ) const;
+ StartOfNonVolatileRegs = f32,
+ StartOfAllRegs = f0,
+ };
+ const char * const getRegName(unsigned reg) const;
};
//-----------------------------------------------------------------------------
// Int CC Register Class
-// Only one integer cc register is available
+// Only one integer cc register is available. However, this register is
+// referred to as %xcc or %icc when instructions like subcc are executed but
+// referred to as %ccr (i.e., %xcc . %icc") when this register is moved
+// into an integer register using RD or WR instrcutions. So, three ids are
+// allocated for the three names.
//-----------------------------------------------------------------------------
-
-class SparcIntCCRegClass : public MachineRegClassInfo
-{
-public:
-
+struct SparcIntCCRegClass : public TargetRegClassInfo {
SparcIntCCRegClass(unsigned ID)
- : MachineRegClassInfo(ID,1, 1) { }
+ : TargetRegClassInfo(ID, 1, 3) { }
+
+ void colorIGNode(IGNode *Node,
+ const std::vector<bool> &IsColorUsedArr) const;
- inline void colorIGNode(IGNode * Node, bool IsColorUsedArr[] ) const {
- Node->setColor(0); // only one int cc reg is available
- }
+ // according to Sparc 64 ABI, %ccr is volatile
+ //
+ inline bool isRegVolatile(int Reg) const { return true; }
-};
+ enum {
+ xcc, icc, ccr // only one is available - see the note above
+ };
+ const char * const getRegName(unsigned reg) const;
+};
//-----------------------------------------------------------------------------
// Float CC Register Class
-// Only 4 Float CC registers are available
+// Only 4 Float CC registers are available for allocation.
//-----------------------------------------------------------------------------
+struct SparcFloatCCRegClass : public TargetRegClassInfo {
+ SparcFloatCCRegClass(unsigned ID)
+ : TargetRegClassInfo(ID, 4, 5) { }
-static string const FloatCCRegNames[] =
- {
- "fcc0", "fcc1", "fcc2", "fcc3"
- };
-
-
-class SparcFloatCCRegOrder{
-
- public:
-
- enum RegsInPrefOrder {
+ void colorIGNode(IGNode *Node,
+ const std::vector<bool> &IsColorUsedArr) const;
+
+ // according to Sparc 64 ABI, all %fp CC regs are volatile
+ //
+ inline bool isRegVolatile(int Reg) const { return true; }
- fcc0, fcc1, fcc2, fcc3
- };
-
- static const string getRegName(const unsigned reg) {
- assert( reg < 4 );
- return FloatCCRegNames[reg];
- }
+ enum {
+ fcc0, fcc1, fcc2, fcc3, fsr // fsr is not used in allocation
+ }; // but has a name in getRegName()
+ const char * const getRegName(unsigned reg) const;
};
+//-----------------------------------------------------------------------------
+// Sparc special register class. These registers are not used for allocation
+// but are used as arguments of some instructions.
+//-----------------------------------------------------------------------------
+struct SparcSpecialRegClass : public TargetRegClassInfo {
+ SparcSpecialRegClass(unsigned ID)
+ : TargetRegClassInfo(ID, 0, 1) { }
-class SparcFloatCCRegClass : public MachineRegClassInfo
-{
-public:
-
- SparcFloatCCRegClass(unsigned ID)
- : MachineRegClassInfo(ID, 4, 4) { }
-
- void colorIGNode(IGNode * Node, bool IsColorUsedArr[] ) const {
- int c;
- for(c=0; c < 4 && IsColorUsedArr[c] ; ++c) ; // find color
- assert( (c < 4) && "Can allocate only 4 float cc registers");
- Node->setColor(c);
+ void colorIGNode(IGNode *Node,
+ const std::vector<bool> &IsColorUsedArr) const {
+ assert(0 && "SparcSpecialRegClass should never be used for allocation");
}
+
+ // all currently included special regs are volatile
+ inline bool isRegVolatile(int Reg) const { return true; }
-};
-
-
+ enum {
+ fsr // floating point state register
+ };
+ const char * const getRegName(unsigned reg) const;
+};
#endif
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