Introduce MCCodeGenInfo, which keeps information that can affect codegen
[oota-llvm.git] / lib / Target / Sparc / SparcTargetMachine.cpp
index cbe6d8754efd27c11ab8e7f6f0eda44f62105dee..218c4bc9bca3900dbb1e743948e1256bf94c62f2 100644 (file)
@@ -24,10 +24,10 @@ extern "C" void LLVMInitializeSparcTarget() {
 
 /// SparcTargetMachine ctor - Create an ILP32 architecture model
 ///
-SparcTargetMachine::SparcTargetMachine(const Target &T, const std::string &TT, 
-                                       const std::string &CPU,
-                                       const std::string &FS, bool is64bit)
-  : LLVMTargetMachine(T, TT, CPU, FS),
+SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, 
+                                       StringRef CPU, StringRef FS,
+                                       Reloc::Model RM, bool is64bit)
+  : LLVMTargetMachine(T, TT, CPU, FS, RM),
     Subtarget(TT, CPU, FS, is64bit),
     DataLayout(Subtarget.getDataLayout()),
     TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget),
@@ -51,15 +51,15 @@ bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM,
 }
 
 SparcV8TargetMachine::SparcV8TargetMachine(const Target &T,
-                                           const std::string &TT, 
-                                           const std::string &CPU,
-                                           const std::string &FS)
-  : SparcTargetMachine(T, TT, CPU, FS, false) {
+                                           StringRef TT, 
+                                           StringRef CPU,
+                                           StringRef FS, Reloc::Model RM)
+  : SparcTargetMachine(T, TT, CPU, FS, RM, false) {
 }
 
 SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, 
-                                           const std::string &TT, 
-                                           const std::string &CPU,
-                                           const std::string &FS)
-  : SparcTargetMachine(T, TT, CPU, FS, true) {
+                                           StringRef TT, 
+                                           StringRef CPU,
+                                           StringRef FS, Reloc::Model RM)
+  : SparcTargetMachine(T, TT, CPU, FS, RM, true) {
 }