-//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===//
-//
+//===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===//
+//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
//===----------------------------------------------------------------------===//
//
-// This file describes the SparcV8 instructions in TableGen format.
+// This file describes the Sparc instructions in TableGen format.
//
//===----------------------------------------------------------------------===//
// Instruction format superclass
//===----------------------------------------------------------------------===//
-include "SparcV8InstrFormats.td"
+include "SparcInstrFormats.td"
//===----------------------------------------------------------------------===//
// Feature predicates.
//===----------------------------------------------------------------------===//
+// True when generating 32-bit code.
+def Is32Bit : Predicate<"!Subtarget.is64Bit()">;
+
+// True when generating 64-bit code. This also implies HasV9.
+def Is64Bit : Predicate<"Subtarget.is64Bit()">;
+
// HasV9 - This predicate is true when the target processor supports V9
// instructions. Note that the machine may be running in 32-bit mode.
def HasV9 : Predicate<"Subtarget.isV9()">;
// Instruction Pattern Stuff
//===----------------------------------------------------------------------===//
-def simm11 : PatLeaf<(imm), [{
- // simm11 predicate - True if the imm fits in a 11-bit sign extended field.
- return (((int)N->getValue() << (32-11)) >> (32-11)) == (int)N->getValue();
-}]>;
+def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>;
-def simm13 : PatLeaf<(imm), [{
- // simm13 predicate - True if the imm fits in a 13-bit sign extended field.
- return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue();
-}]>;
+def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>;
def LO10 : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32);
+ return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023,
+ MVT::i32);
}]>;
def HI22 : SDNodeXForm<imm, [{
// Transformation function: shift the immediate value down into the low bits.
- return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32);
+ return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32);
}]>;
def SETHIimm : PatLeaf<(imm), [{
- return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue();
+ return isShiftedUInt<22, 10>(N->getZExtValue());
}], HI22>;
// Addressing modes.
-def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>;
-def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", []>;
+def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>;
+def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;
// Address operands
-def MEMrr : Operand<i32> {
+def MEMrr : Operand<iPTR> {
let PrintMethod = "printMemOperand";
- let NumMIOperands = 2;
- let MIOperandInfo = (ops IntRegs, IntRegs);
+ let MIOperandInfo = (ops ptr_rc, ptr_rc);
}
-def MEMri : Operand<i32> {
+def MEMri : Operand<iPTR> {
let PrintMethod = "printMemOperand";
- let NumMIOperands = 2;
- let MIOperandInfo = (ops IntRegs, i32imm);
+ let MIOperandInfo = (ops ptr_rc, i32imm);
}
// Branch targets have OtherVT type.
def calltarget : Operand<i32>;
// Operand for printing out a condition code.
-let PrintMethod = "printV8CCOperand" in
- def V8CC : Operand<i32>;
-
-def SDTV8cmpfcc :
-SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>;
-def SDTV8brcc :
-SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
- SDTCisVT<2, FlagVT>]>;
-def SDTV8selectcc :
-SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
- SDTCisVT<3, i32>, SDTCisVT<4, FlagVT>]>;
-def SDTV8FTOI :
+let PrintMethod = "printCCOperand" in
+ def CCOp : Operand<i32>;
+
+def SDTSPcmpfcc :
+SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
+def SDTSPbrcc :
+SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
+def SDTSPselectcc :
+SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>;
+def SDTSPFTOI :
SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
-def SDTV8ITOF :
+def SDTSPITOF :
SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
-def V8cmpicc : SDNode<"V8ISD::CMPICC", SDTIntBinOp, [SDNPOutFlag]>;
-def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc, [SDNPOutFlag]>;
-def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>;
-def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>;
+def SPcmpicc : SDNode<"SPISD::CMPICC", SDTIntBinOp, [SDNPOutGlue]>;
+def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>;
+def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
+def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
+def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
+
+def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
+def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
+
+def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>;
+def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>;
+
+def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>;
+def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>;
+def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>;
-def V8hi : SDNode<"V8ISD::Hi", SDTIntUnaryOp>;
-def V8lo : SDNode<"V8ISD::Lo", SDTIntUnaryOp>;
+// These are target-independent nodes, but have target-specific formats.
+def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
+def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
+ SDTCisVT<1, i32> ]>;
-def V8ftoi : SDNode<"V8ISD::FTOI", SDTV8FTOI>;
-def V8itof : SDNode<"V8ISD::ITOF", SDTV8ITOF>;
+def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
+ [SDNPHasChain, SDNPOutGlue]>;
+def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
+ [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
-def V8selecticc : SDNode<"V8ISD::SELECT_ICC", SDTV8selectcc>;
-def V8selectfcc : SDNode<"V8ISD::SELECT_FCC", SDTV8selectcc>;
+def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
+def call : SDNode<"SPISD::CALL", SDT_SPCall,
+ [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
+ SDNPVariadic]>;
-// These are target-independent nodes, but have target-specific formats.
-def SDT_V8CallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
-def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_V8CallSeq, [SDNPHasChain]>;
-def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_V8CallSeq, [SDNPHasChain]>;
+def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
+def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRet,
+ [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
-def SDT_V8Call : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
-def call : SDNode<"V8ISD::CALL", SDT_V8Call,
- [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
+def flushw : SDNode<"SPISD::FLUSHW", SDTNone,
+ [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>;
-def SDT_V8RetFlag : SDTypeProfile<0, 0, []>;
-def retflag : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag,
- [SDNPHasChain, SDNPOptInFlag]>;
+def getPCX : Operand<i32> {
+ let PrintMethod = "printGetPCX";
+}
//===----------------------------------------------------------------------===//
// SPARC Flag Conditions
//===----------------------------------------------------------------------===//
-// Note that these values must be kept in sync with the V8CC::CondCode enum
+// Note that these values must be kept in sync with the CCOp::CondCode enum
// values.
class ICC_VAL<int N> : PatLeaf<(i32 N)>;
def ICC_NE : ICC_VAL< 9>; // Not Equal
def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal
def FCC_O : FCC_VAL<29>; // Ordered
+//===----------------------------------------------------------------------===//
+// Instruction Class Templates
+//===----------------------------------------------------------------------===//
+
+/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
+multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> {
+ def rr : F3_1<2, Op3Val,
+ (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
+ !strconcat(OpcStr, " $b, $c, $dst"),
+ [(set i32:$dst, (OpNode i32:$b, i32:$c))]>;
+ def ri : F3_2<2, Op3Val,
+ (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
+ !strconcat(OpcStr, " $b, $c, $dst"),
+ [(set i32:$dst, (OpNode i32:$b, (i32 simm13:$c)))]>;
+}
+
+/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no
+/// pattern.
+multiclass F3_12np<string OpcStr, bits<6> Op3Val> {
+ def rr : F3_1<2, Op3Val,
+ (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
+ !strconcat(OpcStr, " $b, $c, $dst"), []>;
+ def ri : F3_2<2, Op3Val,
+ (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
+ !strconcat(OpcStr, " $b, $c, $dst"), []>;
+}
//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//
// Pseudo instructions.
-class Pseudo<dag ops, string asmstr, list<dag> pattern>
- : InstV8<ops, asmstr, pattern>;
+class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstSP<outs, ins, asmstr, pattern>;
+
+// GETPCX for PIC
+let Defs = [O7] in {
+ def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >;
+}
-def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt),
+let Defs = [O6], Uses = [O6] in {
+def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
"!ADJCALLSTACKDOWN $amt",
- [(callseq_start imm:$amt)]>;
-def ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt),
- "!ADJCALLSTACKUP $amt",
- [(callseq_end imm:$amt)]>;
-def IMPLICIT_DEF_Int : Pseudo<(ops IntRegs:$dst),
- "!IMPLICIT_DEF $dst",
- [(set IntRegs:$dst, (undef))]>;
-def IMPLICIT_DEF_FP : Pseudo<(ops FPRegs:$dst), "!IMPLICIT_DEF $dst",
- [(set FPRegs:$dst, (undef))]>;
-def IMPLICIT_DEF_DFP : Pseudo<(ops DFPRegs:$dst), "!IMPLICIT_DEF $dst",
- [(set DFPRegs:$dst, (undef))]>;
-
-// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the
+ [(callseq_start timm:$amt)]>;
+def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
+ "!ADJCALLSTACKUP $amt1",
+ [(callseq_end timm:$amt1, timm:$amt2)]>;
+}
+
+let hasSideEffects = 1, mayStore = 1 in {
+ let rd = 0, rs1 = 0, rs2 = 0 in
+ def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins),
+ "flushw",
+ [(flushw)]>, Requires<[HasV9]>;
+ let rd = 0, rs1 = 1, simm13 = 3 in
+ def TA3 : F3_2<0b10, 0b111010, (outs), (ins),
+ "ta 3",
+ [(flushw)]>;
+}
+
+def UNIMP : F2_1<0b000, (outs), (ins i32imm:$val),
+ "unimp $val", []>;
+
+// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the
// fpmover pass.
let Predicates = [HasNoV9] in { // Only emit these in V8 mode.
- def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
+ def FpMOVD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
"!FpMOVD $src, $dst", []>;
- def FpNEGD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
+ def FpNEGD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
"!FpNEGD $src, $dst",
- [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
- def FpABSD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
+ [(set f64:$dst, (fneg f64:$src))]>;
+ def FpABSD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
"!FpABSD $src, $dst",
- [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>;
+ [(set f64:$dst, (fabs f64:$src))]>;
}
-// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
-// scheduler into a branch sequence. This has to handle all permutations of
-// selection between i32/f32/f64 on ICC and FCC.
-let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
- Predicates = [HasNoV9] in { // V9 has conditional moves
+// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
+// instruction selection into a branch sequence. This has to handle all
+// permutations of selection between i32/f32/f64 on ICC and FCC.
+// Expanded after instruction selection.
+let Uses = [ICC], usesCustomInserter = 1 in {
def SELECT_CC_Int_ICC
- : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
+ : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
"; SELECT_CC_Int_ICC PSEUDO!",
- [(set IntRegs:$dst, (V8selecticc IntRegs:$T, IntRegs:$F,
- imm:$Cond, ICC))]>;
- def SELECT_CC_Int_FCC
- : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
- "; SELECT_CC_Int_FCC PSEUDO!",
- [(set IntRegs:$dst, (V8selectfcc IntRegs:$T, IntRegs:$F,
- imm:$Cond, FCC))]>;
+ [(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>;
def SELECT_CC_FP_ICC
- : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
+ : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
"; SELECT_CC_FP_ICC PSEUDO!",
- [(set FPRegs:$dst, (V8selecticc FPRegs:$T, FPRegs:$F,
- imm:$Cond, ICC))]>;
- def SELECT_CC_FP_FCC
- : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
- "; SELECT_CC_FP_FCC PSEUDO!",
- [(set FPRegs:$dst, (V8selectfcc FPRegs:$T, FPRegs:$F,
- imm:$Cond, FCC))]>;
+ [(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>;
+
def SELECT_CC_DFP_ICC
- : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
+ : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
"; SELECT_CC_DFP_ICC PSEUDO!",
- [(set DFPRegs:$dst, (V8selecticc DFPRegs:$T, DFPRegs:$F,
- imm:$Cond, ICC))]>;
+ [(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>;
+}
+
+let usesCustomInserter = 1, Uses = [FCC] in {
+
+ def SELECT_CC_Int_FCC
+ : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
+ "; SELECT_CC_Int_FCC PSEUDO!",
+ [(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>;
+
+ def SELECT_CC_FP_FCC
+ : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
+ "; SELECT_CC_FP_FCC PSEUDO!",
+ [(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>;
def SELECT_CC_DFP_FCC
- : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
+ : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
"; SELECT_CC_DFP_FCC PSEUDO!",
- [(set DFPRegs:$dst, (V8selectfcc DFPRegs:$T, DFPRegs:$F,
- imm:$Cond, FCC))]>;
+ [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>;
}
// Section A.3 - Synthetic Instructions, p. 85
// special cases of JMPL:
-let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in {
- let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
- def RETL: F3_2<2, 0b111000, (ops), "retl", [(retflag)]>;
+let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in {
+ let rd = O7.Num, rs1 = G0.Num in
+ def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
+ "jmp %o7+$val", [(retflag simm13:$val)]>;
+
+ let rd = I7.Num, rs1 = G0.Num in
+ def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
+ "jmp %i7+$val", []>;
}
// Section B.1 - Load Integer Instructions, p. 90
def LDSBrr : F3_1<3, 0b001001,
- (ops IntRegs:$dst, MEMrr:$addr),
+ (outs IntRegs:$dst), (ins MEMrr:$addr),
"ldsb [$addr], $dst",
- [(set IntRegs:$dst, (sextload ADDRrr:$addr, i8))]>;
+ [(set i32:$dst, (sextloadi8 ADDRrr:$addr))]>;
def LDSBri : F3_2<3, 0b001001,
- (ops IntRegs:$dst, MEMri:$addr),
+ (outs IntRegs:$dst), (ins MEMri:$addr),
"ldsb [$addr], $dst",
- [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>;
+ [(set i32:$dst, (sextloadi8 ADDRri:$addr))]>;
def LDSHrr : F3_1<3, 0b001010,
- (ops IntRegs:$dst, MEMrr:$addr),
+ (outs IntRegs:$dst), (ins MEMrr:$addr),
"ldsh [$addr], $dst",
- [(set IntRegs:$dst, (sextload ADDRrr:$addr, i16))]>;
+ [(set i32:$dst, (sextloadi16 ADDRrr:$addr))]>;
def LDSHri : F3_2<3, 0b001010,
- (ops IntRegs:$dst, MEMri:$addr),
+ (outs IntRegs:$dst), (ins MEMri:$addr),
"ldsh [$addr], $dst",
- [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>;
+ [(set i32:$dst, (sextloadi16 ADDRri:$addr))]>;
def LDUBrr : F3_1<3, 0b000001,
- (ops IntRegs:$dst, MEMrr:$addr),
+ (outs IntRegs:$dst), (ins MEMrr:$addr),
"ldub [$addr], $dst",
- [(set IntRegs:$dst, (zextload ADDRrr:$addr, i8))]>;
+ [(set i32:$dst, (zextloadi8 ADDRrr:$addr))]>;
def LDUBri : F3_2<3, 0b000001,
- (ops IntRegs:$dst, MEMri:$addr),
+ (outs IntRegs:$dst), (ins MEMri:$addr),
"ldub [$addr], $dst",
- [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>;
+ [(set i32:$dst, (zextloadi8 ADDRri:$addr))]>;
def LDUHrr : F3_1<3, 0b000010,
- (ops IntRegs:$dst, MEMrr:$addr),
+ (outs IntRegs:$dst), (ins MEMrr:$addr),
"lduh [$addr], $dst",
- [(set IntRegs:$dst, (zextload ADDRrr:$addr, i16))]>;
+ [(set i32:$dst, (zextloadi16 ADDRrr:$addr))]>;
def LDUHri : F3_2<3, 0b000010,
- (ops IntRegs:$dst, MEMri:$addr),
+ (outs IntRegs:$dst), (ins MEMri:$addr),
"lduh [$addr], $dst",
- [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>;
+ [(set i32:$dst, (zextloadi16 ADDRri:$addr))]>;
def LDrr : F3_1<3, 0b000000,
- (ops IntRegs:$dst, MEMrr:$addr),
+ (outs IntRegs:$dst), (ins MEMrr:$addr),
"ld [$addr], $dst",
- [(set IntRegs:$dst, (load ADDRrr:$addr))]>;
+ [(set i32:$dst, (load ADDRrr:$addr))]>;
def LDri : F3_2<3, 0b000000,
- (ops IntRegs:$dst, MEMri:$addr),
+ (outs IntRegs:$dst), (ins MEMri:$addr),
"ld [$addr], $dst",
- [(set IntRegs:$dst, (load ADDRri:$addr))]>;
+ [(set i32:$dst, (load ADDRri:$addr))]>;
// Section B.2 - Load Floating-point Instructions, p. 92
def LDFrr : F3_1<3, 0b100000,
- (ops FPRegs:$dst, MEMrr:$addr),
+ (outs FPRegs:$dst), (ins MEMrr:$addr),
"ld [$addr], $dst",
- [(set FPRegs:$dst, (load ADDRrr:$addr))]>;
+ [(set f32:$dst, (load ADDRrr:$addr))]>;
def LDFri : F3_2<3, 0b100000,
- (ops FPRegs:$dst, MEMri:$addr),
+ (outs FPRegs:$dst), (ins MEMri:$addr),
"ld [$addr], $dst",
- [(set FPRegs:$dst, (load ADDRri:$addr))]>;
+ [(set f32:$dst, (load ADDRri:$addr))]>;
def LDDFrr : F3_1<3, 0b100011,
- (ops DFPRegs:$dst, MEMrr:$addr),
+ (outs DFPRegs:$dst), (ins MEMrr:$addr),
"ldd [$addr], $dst",
- [(set DFPRegs:$dst, (load ADDRrr:$addr))]>;
+ [(set f64:$dst, (load ADDRrr:$addr))]>;
def LDDFri : F3_2<3, 0b100011,
- (ops DFPRegs:$dst, MEMri:$addr),
+ (outs DFPRegs:$dst), (ins MEMri:$addr),
"ldd [$addr], $dst",
- [(set DFPRegs:$dst, (load ADDRri:$addr))]>;
+ [(set f64:$dst, (load ADDRri:$addr))]>;
// Section B.4 - Store Integer Instructions, p. 95
def STBrr : F3_1<3, 0b000101,
- (ops MEMrr:$addr, IntRegs:$src),
+ (outs), (ins MEMrr:$addr, IntRegs:$src),
"stb $src, [$addr]",
- [(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>;
+ [(truncstorei8 i32:$src, ADDRrr:$addr)]>;
def STBri : F3_2<3, 0b000101,
- (ops MEMri:$addr, IntRegs:$src),
+ (outs), (ins MEMri:$addr, IntRegs:$src),
"stb $src, [$addr]",
- [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>;
+ [(truncstorei8 i32:$src, ADDRri:$addr)]>;
def STHrr : F3_1<3, 0b000110,
- (ops MEMrr:$addr, IntRegs:$src),
+ (outs), (ins MEMrr:$addr, IntRegs:$src),
"sth $src, [$addr]",
- [(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>;
+ [(truncstorei16 i32:$src, ADDRrr:$addr)]>;
def STHri : F3_2<3, 0b000110,
- (ops MEMri:$addr, IntRegs:$src),
+ (outs), (ins MEMri:$addr, IntRegs:$src),
"sth $src, [$addr]",
- [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>;
+ [(truncstorei16 i32:$src, ADDRri:$addr)]>;
def STrr : F3_1<3, 0b000100,
- (ops MEMrr:$addr, IntRegs:$src),
+ (outs), (ins MEMrr:$addr, IntRegs:$src),
"st $src, [$addr]",
- [(store IntRegs:$src, ADDRrr:$addr)]>;
+ [(store i32:$src, ADDRrr:$addr)]>;
def STri : F3_2<3, 0b000100,
- (ops MEMri:$addr, IntRegs:$src),
+ (outs), (ins MEMri:$addr, IntRegs:$src),
"st $src, [$addr]",
- [(store IntRegs:$src, ADDRri:$addr)]>;
+ [(store i32:$src, ADDRri:$addr)]>;
// Section B.5 - Store Floating-point Instructions, p. 97
def STFrr : F3_1<3, 0b100100,
- (ops MEMrr:$addr, FPRegs:$src),
+ (outs), (ins MEMrr:$addr, FPRegs:$src),
"st $src, [$addr]",
- [(store FPRegs:$src, ADDRrr:$addr)]>;
+ [(store f32:$src, ADDRrr:$addr)]>;
def STFri : F3_2<3, 0b100100,
- (ops MEMri:$addr, FPRegs:$src),
+ (outs), (ins MEMri:$addr, FPRegs:$src),
"st $src, [$addr]",
- [(store FPRegs:$src, ADDRri:$addr)]>;
+ [(store f32:$src, ADDRri:$addr)]>;
def STDFrr : F3_1<3, 0b100111,
- (ops MEMrr:$addr, DFPRegs:$src),
+ (outs), (ins MEMrr:$addr, DFPRegs:$src),
"std $src, [$addr]",
- [(store DFPRegs:$src, ADDRrr:$addr)]>;
+ [(store f64:$src, ADDRrr:$addr)]>;
def STDFri : F3_2<3, 0b100111,
- (ops MEMri:$addr, DFPRegs:$src),
+ (outs), (ins MEMri:$addr, DFPRegs:$src),
"std $src, [$addr]",
- [(store DFPRegs:$src, ADDRri:$addr)]>;
+ [(store f64:$src, ADDRri:$addr)]>;
// Section B.9 - SETHI Instruction, p. 104
def SETHIi: F2_1<0b100,
- (ops IntRegs:$dst, i32imm:$src),
+ (outs IntRegs:$dst), (ins i32imm:$src),
"sethi $src, $dst",
- [(set IntRegs:$dst, SETHIimm:$src)]>;
+ [(set i32:$dst, SETHIimm:$src)]>;
// Section B.10 - NOP Instruction, p. 105
// (It's a special case of SETHI)
let rd = 0, imm22 = 0 in
- def NOP : F2_1<0b100, (ops), "nop", []>;
+ def NOP : F2_1<0b100, (outs), (ins), "nop", []>;
// Section B.11 - Logical Instructions, p. 106
-def ANDrr : F3_1<2, 0b000001,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "and $b, $c, $dst",
- [(set IntRegs:$dst, (and IntRegs:$b, IntRegs:$c))]>;
-def ANDri : F3_2<2, 0b000001,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "and $b, $c, $dst",
- [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>;
+defm AND : F3_12<"and", 0b000001, and>;
+
def ANDNrr : F3_1<2, 0b000101,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
+ (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
"andn $b, $c, $dst",
- [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>;
+ [(set i32:$dst, (and i32:$b, (not i32:$c)))]>;
def ANDNri : F3_2<2, 0b000101,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+ (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
"andn $b, $c, $dst", []>;
-def ORrr : F3_1<2, 0b000010,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "or $b, $c, $dst",
- [(set IntRegs:$dst, (or IntRegs:$b, IntRegs:$c))]>;
-def ORri : F3_2<2, 0b000010,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "or $b, $c, $dst",
- [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>;
+
+defm OR : F3_12<"or", 0b000010, or>;
+
def ORNrr : F3_1<2, 0b000110,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
+ (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
"orn $b, $c, $dst",
- [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>;
+ [(set i32:$dst, (or i32:$b, (not i32:$c)))]>;
def ORNri : F3_2<2, 0b000110,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+ (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
"orn $b, $c, $dst", []>;
-def XORrr : F3_1<2, 0b000011,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "xor $b, $c, $dst",
- [(set IntRegs:$dst, (xor IntRegs:$b, IntRegs:$c))]>;
-def XORri : F3_2<2, 0b000011,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "xor $b, $c, $dst",
- [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>;
+defm XOR : F3_12<"xor", 0b000011, xor>;
+
def XNORrr : F3_1<2, 0b000111,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
+ (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
"xnor $b, $c, $dst",
- [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>;
+ [(set i32:$dst, (not (xor i32:$b, i32:$c)))]>;
def XNORri : F3_2<2, 0b000111,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+ (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
"xnor $b, $c, $dst", []>;
// Section B.12 - Shift Instructions, p. 107
-def SLLrr : F3_1<2, 0b100101,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "sll $b, $c, $dst",
- [(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>;
-def SLLri : F3_2<2, 0b100101,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "sll $b, $c, $dst",
- [(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>;
-def SRLrr : F3_1<2, 0b100110,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "srl $b, $c, $dst",
- [(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>;
-def SRLri : F3_2<2, 0b100110,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "srl $b, $c, $dst",
- [(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>;
-def SRArr : F3_1<2, 0b100111,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "sra $b, $c, $dst",
- [(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>;
-def SRAri : F3_2<2, 0b100111,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "sra $b, $c, $dst",
- [(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>;
+defm SLL : F3_12<"sll", 0b100101, shl>;
+defm SRL : F3_12<"srl", 0b100110, srl>;
+defm SRA : F3_12<"sra", 0b100111, sra>;
// Section B.13 - Add Instructions, p. 108
-def ADDrr : F3_1<2, 0b000000,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "add $b, $c, $dst",
- [(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))]>;
-def ADDri : F3_2<2, 0b000000,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "add $b, $c, $dst",
- [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>;
-def ADDCCrr : F3_1<2, 0b010000,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "addcc $b, $c, $dst", []>;
-def ADDCCri : F3_2<2, 0b010000,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "addcc $b, $c, $dst", []>;
-def ADDXrr : F3_1<2, 0b001000,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "addx $b, $c, $dst", []>;
-def ADDXri : F3_2<2, 0b001000,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "addx $b, $c, $dst", []>;
+defm ADD : F3_12<"add", 0b000000, add>;
+
+// "LEA" forms of add (patterns to make tblgen happy)
+def LEA_ADDri : F3_2<2, 0b000000,
+ (outs IntRegs:$dst), (ins MEMri:$addr),
+ "add ${addr:arith}, $dst",
+ [(set iPTR:$dst, ADDRri:$addr)]>;
+
+let Defs = [ICC] in
+ defm ADDCC : F3_12<"addcc", 0b010000, addc>;
+
+let Uses = [ICC] in
+ defm ADDX : F3_12<"addx", 0b001000, adde>;
// Section B.15 - Subtract Instructions, p. 110
-def SUBrr : F3_1<2, 0b000100,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "sub $b, $c, $dst",
- [(set IntRegs:$dst, (sub IntRegs:$b, IntRegs:$c))]>;
-def SUBri : F3_2<2, 0b000100,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "sub $b, $c, $dst",
- [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>;
-def SUBXrr : F3_1<2, 0b001100,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "subx $b, $c, $dst", []>;
-def SUBXri : F3_2<2, 0b001100,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "subx $b, $c, $dst", []>;
-def SUBCCrr : F3_1<2, 0b010100,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "subcc $b, $c, $dst",
- [(set IntRegs:$dst, (V8cmpicc IntRegs:$b, IntRegs:$c))]>;
-def SUBCCri : F3_2<2, 0b010100,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "subcc $b, $c, $dst",
- [(set IntRegs:$dst, (V8cmpicc IntRegs:$b, simm13:$c))]>;
-def SUBXCCrr: F3_1<2, 0b011100,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "subxcc $b, $c, $dst", []>;
+defm SUB : F3_12 <"sub" , 0b000100, sub>;
+let Uses = [ICC] in
+ defm SUBX : F3_12 <"subx" , 0b001100, sube>;
+
+let Defs = [ICC] in
+ defm SUBCC : F3_12 <"subcc", 0b010100, SPcmpicc>;
+
+let Uses = [ICC], Defs = [ICC] in
+ def SUBXCCrr: F3_1<2, 0b011100,
+ (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
+ "subxcc $b, $c, $dst", []>;
+
// Section B.18 - Multiply Instructions, p. 113
-def UMULrr : F3_1<2, 0b001010,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "umul $b, $c, $dst", []>;
-def UMULri : F3_2<2, 0b001010,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "umul $b, $c, $dst", []>;
-def SMULrr : F3_1<2, 0b001011,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "smul $b, $c, $dst",
- [(set IntRegs:$dst, (mul IntRegs:$b, IntRegs:$c))]>;
-def SMULri : F3_2<2, 0b001011,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "smul $b, $c, $dst",
- [(set IntRegs:$dst, (mul IntRegs:$b, simm13:$c))]>;
+let Defs = [Y] in {
+ defm UMUL : F3_12np<"umul", 0b001010>;
+ defm SMUL : F3_12 <"smul", 0b001011, mul>;
+}
// Section B.19 - Divide Instructions, p. 115
-def UDIVrr : F3_1<2, 0b001110,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "udiv $b, $c, $dst", []>;
-def UDIVri : F3_2<2, 0b001110,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "udiv $b, $c, $dst", []>;
-def SDIVrr : F3_1<2, 0b001111,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "sdiv $b, $c, $dst", []>;
-def SDIVri : F3_2<2, 0b001111,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "sdiv $b, $c, $dst", []>;
+let Defs = [Y] in {
+ defm UDIV : F3_12np<"udiv", 0b001110>;
+ defm SDIV : F3_12np<"sdiv", 0b001111>;
+}
// Section B.20 - SAVE and RESTORE, p. 117
-def SAVErr : F3_1<2, 0b111100,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "save $b, $c, $dst", []>;
-def SAVEri : F3_2<2, 0b111100,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "save $b, $c, $dst", []>;
-def RESTORErr : F3_1<2, 0b111101,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "restore $b, $c, $dst", []>;
-def RESTOREri : F3_2<2, 0b111101,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "restore $b, $c, $dst", []>;
+defm SAVE : F3_12np<"save" , 0b111100>;
+defm RESTORE : F3_12np<"restore", 0b111101>;
// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
// conditional branch class:
-class BranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
- : F2_2<cc, 0b010, ops, asmstr, pattern> {
+class BranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern>
+ : F2_2<cc, 0b010, (outs), ins, asmstr, pattern> {
let isBranch = 1;
let isTerminator = 1;
let hasDelaySlot = 1;
- let noResults = 1;
}
let isBarrier = 1 in
- def BA : BranchV8<0b1000, (ops brtarget:$dst),
+ def BA : BranchSP<0b1000, (ins brtarget:$dst),
"ba $dst",
[(br bb:$dst)]>;
-
+
+// Indirect branch instructions.
+let isTerminator = 1, isBarrier = 1,
+ hasDelaySlot = 1, isBranch =1,
+ isIndirectBranch = 1 in {
+ def BINDrr : F3_1<2, 0b111000,
+ (outs), (ins MEMrr:$ptr),
+ "jmp $ptr",
+ [(brind ADDRrr:$ptr)]>;
+ def BINDri : F3_2<2, 0b111000,
+ (outs), (ins MEMri:$ptr),
+ "jmp $ptr",
+ [(brind ADDRri:$ptr)]>;
+}
+
// FIXME: the encoding for the JIT should look at the condition field.
-def BCOND : BranchV8<0, (ops brtarget:$dst, V8CC:$cc),
- "b$cc $dst",
- [(V8bricc bb:$dst, imm:$cc, ICC)]>;
+let Uses = [ICC] in
+ def BCOND : BranchSP<0, (ins brtarget:$dst, CCOp:$cc),
+ "b$cc $dst",
+ [(SPbricc bb:$dst, imm:$cc)]>;
// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
// floating-point conditional branch class:
-class FPBranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
- : F2_2<cc, 0b110, ops, asmstr, pattern> {
+class FPBranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern>
+ : F2_2<cc, 0b110, (outs), ins, asmstr, pattern> {
let isBranch = 1;
let isTerminator = 1;
let hasDelaySlot = 1;
- let noResults = 1;
}
// FIXME: the encoding for the JIT should look at the condition field.
-def FBCOND : FPBranchV8<0, (ops brtarget:$dst, V8CC:$cc),
- "fb$cc $dst",
- [(V8brfcc bb:$dst, imm:$cc, FCC)]>;
+let Uses = [FCC] in
+ def FBCOND : FPBranchSP<0, (ins brtarget:$dst, CCOp:$cc),
+ "fb$cc $dst",
+ [(SPbrfcc bb:$dst, imm:$cc)]>;
// Section B.24 - Call and Link Instruction, p. 125
// This is the only Format 1 instruction
-let Uses = [O0, O1, O2, O3, O4, O5],
- hasDelaySlot = 1, isCall = 1, noResults = 1,
+let Uses = [O6],
+ hasDelaySlot = 1, isCall = 1,
Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
- D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in {
- def CALL : InstV8<(ops calltarget:$dst),
+ D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
+ ICC, FCC, Y] in {
+ def CALL : InstSP<(outs), (ins calltarget:$dst, variable_ops),
"call $dst", []> {
bits<30> disp;
let op = 1;
let Inst{29-0} = disp;
}
-
+
// indirect calls
def JMPLrr : F3_1<2, 0b111000,
- (ops MEMrr:$ptr),
+ (outs), (ins MEMrr:$ptr, variable_ops),
"call $ptr",
- [(call ADDRrr:$ptr)]>;
+ [(call ADDRrr:$ptr)]>;
def JMPLri : F3_2<2, 0b111000,
- (ops MEMri:$ptr),
+ (outs), (ins MEMri:$ptr, variable_ops),
"call $ptr",
- [(call ADDRri:$ptr)]>;
+ [(call ADDRri:$ptr)]>;
}
// Section B.28 - Read State Register Instructions
-def RDY : F3_1<2, 0b101000,
- (ops IntRegs:$dst),
- "rd %y, $dst", []>;
+let Uses = [Y] in
+ def RDY : F3_1<2, 0b101000,
+ (outs IntRegs:$dst), (ins),
+ "rd %y, $dst", []>;
// Section B.29 - Write State Register Instructions
-def WRYrr : F3_1<2, 0b110000,
- (ops IntRegs:$b, IntRegs:$c),
- "wr $b, $c, %y", []>;
-def WRYri : F3_2<2, 0b110000,
- (ops IntRegs:$b, i32imm:$c),
- "wr $b, $c, %y", []>;
-
+let Defs = [Y] in {
+ def WRYrr : F3_1<2, 0b110000,
+ (outs), (ins IntRegs:$b, IntRegs:$c),
+ "wr $b, $c, %y", []>;
+ def WRYri : F3_2<2, 0b110000,
+ (outs), (ins IntRegs:$b, i32imm:$c),
+ "wr $b, $c, %y", []>;
+}
// Convert Integer to Floating-point Instructions, p. 141
def FITOS : F3_3<2, 0b110100, 0b011000100,
- (ops FPRegs:$dst, FPRegs:$src),
+ (outs FPRegs:$dst), (ins FPRegs:$src),
"fitos $src, $dst",
- [(set FPRegs:$dst, (V8itof FPRegs:$src))]>;
-def FITOD : F3_3<2, 0b110100, 0b011001000,
- (ops DFPRegs:$dst, FPRegs:$src),
+ [(set FPRegs:$dst, (SPitof FPRegs:$src))]>;
+def FITOD : F3_3<2, 0b110100, 0b011001000,
+ (outs DFPRegs:$dst), (ins FPRegs:$src),
"fitod $src, $dst",
- [(set DFPRegs:$dst, (V8itof FPRegs:$src))]>;
+ [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>;
// Convert Floating-point to Integer Instructions, p. 142
def FSTOI : F3_3<2, 0b110100, 0b011010001,
- (ops FPRegs:$dst, FPRegs:$src),
+ (outs FPRegs:$dst), (ins FPRegs:$src),
"fstoi $src, $dst",
- [(set FPRegs:$dst, (V8ftoi FPRegs:$src))]>;
+ [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>;
def FDTOI : F3_3<2, 0b110100, 0b011010010,
- (ops FPRegs:$dst, DFPRegs:$src),
+ (outs FPRegs:$dst), (ins DFPRegs:$src),
"fdtoi $src, $dst",
- [(set FPRegs:$dst, (V8ftoi DFPRegs:$src))]>;
+ [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>;
// Convert between Floating-point Formats Instructions, p. 143
-def FSTOD : F3_3<2, 0b110100, 0b011001001,
- (ops DFPRegs:$dst, FPRegs:$src),
+def FSTOD : F3_3<2, 0b110100, 0b011001001,
+ (outs DFPRegs:$dst), (ins FPRegs:$src),
"fstod $src, $dst",
- [(set DFPRegs:$dst, (fextend FPRegs:$src))]>;
+ [(set f64:$dst, (fextend f32:$src))]>;
def FDTOS : F3_3<2, 0b110100, 0b011000110,
- (ops FPRegs:$dst, DFPRegs:$src),
+ (outs FPRegs:$dst), (ins DFPRegs:$src),
"fdtos $src, $dst",
- [(set FPRegs:$dst, (fround DFPRegs:$src))]>;
+ [(set f32:$dst, (fround f64:$src))]>;
// Floating-point Move Instructions, p. 144
def FMOVS : F3_3<2, 0b110100, 0b000000001,
- (ops FPRegs:$dst, FPRegs:$src),
+ (outs FPRegs:$dst), (ins FPRegs:$src),
"fmovs $src, $dst", []>;
-def FNEGS : F3_3<2, 0b110100, 0b000000101,
- (ops FPRegs:$dst, FPRegs:$src),
+def FNEGS : F3_3<2, 0b110100, 0b000000101,
+ (outs FPRegs:$dst), (ins FPRegs:$src),
"fnegs $src, $dst",
- [(set FPRegs:$dst, (fneg FPRegs:$src))]>;
-def FABSS : F3_3<2, 0b110100, 0b000001001,
- (ops FPRegs:$dst, FPRegs:$src),
+ [(set f32:$dst, (fneg f32:$src))]>;
+def FABSS : F3_3<2, 0b110100, 0b000001001,
+ (outs FPRegs:$dst), (ins FPRegs:$src),
"fabss $src, $dst",
- [(set FPRegs:$dst, (fabs FPRegs:$src))]>;
+ [(set f32:$dst, (fabs f32:$src))]>;
// Floating-point Square Root Instructions, p.145
-def FSQRTS : F3_3<2, 0b110100, 0b000101001,
- (ops FPRegs:$dst, FPRegs:$src),
+def FSQRTS : F3_3<2, 0b110100, 0b000101001,
+ (outs FPRegs:$dst), (ins FPRegs:$src),
"fsqrts $src, $dst",
- [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>;
-def FSQRTD : F3_3<2, 0b110100, 0b000101010,
- (ops DFPRegs:$dst, DFPRegs:$src),
+ [(set f32:$dst, (fsqrt f32:$src))]>;
+def FSQRTD : F3_3<2, 0b110100, 0b000101010,
+ (outs DFPRegs:$dst), (ins DFPRegs:$src),
"fsqrtd $src, $dst",
- [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>;
+ [(set f64:$dst, (fsqrt f64:$src))]>;
// Floating-point Add and Subtract Instructions, p. 146
def FADDS : F3_3<2, 0b110100, 0b001000001,
- (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
+ (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
"fadds $src1, $src2, $dst",
- [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>;
+ [(set f32:$dst, (fadd f32:$src1, f32:$src2))]>;
def FADDD : F3_3<2, 0b110100, 0b001000010,
- (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
+ (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
"faddd $src1, $src2, $dst",
- [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>;
+ [(set f64:$dst, (fadd f64:$src1, f64:$src2))]>;
def FSUBS : F3_3<2, 0b110100, 0b001000101,
- (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
+ (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
"fsubs $src1, $src2, $dst",
- [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>;
+ [(set f32:$dst, (fsub f32:$src1, f32:$src2))]>;
def FSUBD : F3_3<2, 0b110100, 0b001000110,
- (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
+ (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
"fsubd $src1, $src2, $dst",
- [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>;
+ [(set f64:$dst, (fsub f64:$src1, f64:$src2))]>;
// Floating-point Multiply and Divide Instructions, p. 147
def FMULS : F3_3<2, 0b110100, 0b001001001,
- (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
+ (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
"fmuls $src1, $src2, $dst",
- [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>;
+ [(set f32:$dst, (fmul f32:$src1, f32:$src2))]>;
def FMULD : F3_3<2, 0b110100, 0b001001010,
- (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
+ (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
"fmuld $src1, $src2, $dst",
- [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>;
+ [(set f64:$dst, (fmul f64:$src1, f64:$src2))]>;
def FSMULD : F3_3<2, 0b110100, 0b001101001,
- (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
+ (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
"fsmuld $src1, $src2, $dst",
- [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1),
- (fextend FPRegs:$src2)))]>;
+ [(set f64:$dst, (fmul (fextend f32:$src1),
+ (fextend f32:$src2)))]>;
def FDIVS : F3_3<2, 0b110100, 0b001001101,
- (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
+ (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
"fdivs $src1, $src2, $dst",
- [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>;
+ [(set f32:$dst, (fdiv f32:$src1, f32:$src2))]>;
def FDIVD : F3_3<2, 0b110100, 0b001001110,
- (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
+ (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
"fdivd $src1, $src2, $dst",
- [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>;
+ [(set f64:$dst, (fdiv f64:$src1, f64:$src2))]>;
// Floating-point Compare Instructions, p. 148
// Note: the 2nd template arg is different for these guys.
// Note 2: the result of a FCMP is not available until the 2nd cycle
// after the instr is retired, but there is no interlock. This behavior
// is modelled with a forced noop after the instruction.
-def FCMPS : F3_3<2, 0b110101, 0b001010001,
- (ops FPRegs:$src1, FPRegs:$src2),
- "fcmps $src1, $src2\n\tnop",
- [(set FCC, (V8cmpfcc FPRegs:$src1, FPRegs:$src2))]>;
-def FCMPD : F3_3<2, 0b110101, 0b001010010,
- (ops DFPRegs:$src1, DFPRegs:$src2),
- "fcmpd $src1, $src2\n\tnop",
- [(set FCC, (V8cmpfcc DFPRegs:$src1, DFPRegs:$src2))]>;
-
+let Defs = [FCC] in {
+ def FCMPS : F3_3<2, 0b110101, 0b001010001,
+ (outs), (ins FPRegs:$src1, FPRegs:$src2),
+ "fcmps $src1, $src2\n\tnop",
+ [(SPcmpfcc f32:$src1, f32:$src2)]>;
+ def FCMPD : F3_3<2, 0b110101, 0b001010010,
+ (outs), (ins DFPRegs:$src1, DFPRegs:$src2),
+ "fcmpd $src1, $src2\n\tnop",
+ [(SPcmpfcc f64:$src1, f64:$src2)]>;
+}
//===----------------------------------------------------------------------===//
// V9 Instructions
//===----------------------------------------------------------------------===//
// V9 Conditional Moves.
-let Predicates = [HasV9], isTwoAddress = 1 in {
+let Predicates = [HasV9], Constraints = "$f = $rd" in {
// Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
// FIXME: Add instruction encodings for the JIT some day.
- def MOVICCrr
- : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, V8CC:$cc),
- "mov$cc %icc, $F, $dst",
- [(set IntRegs:$dst,
- (V8selecticc IntRegs:$F, IntRegs:$T, imm:$cc, ICC))]>;
- def MOVICCri
- : Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, V8CC:$cc),
- "mov$cc %icc, $F, $dst",
- [(set IntRegs:$dst,
- (V8selecticc simm11:$F, IntRegs:$T, imm:$cc, ICC))]>;
-
- def MOVFCCrr
- : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, V8CC:$cc),
- "movf$cc %fcc, $F, $dst",
- [(set IntRegs:$dst,
- (V8selectfcc IntRegs:$F, IntRegs:$T, imm:$cc, FCC))]>;
- def MOVFCCri
- : Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, V8CC:$cc),
- "movf$cc %fcc, $F, $dst",
- [(set IntRegs:$dst,
- (V8selectfcc simm11:$F, IntRegs:$T, imm:$cc, FCC))]>;
-
- def FMOVS_ICC
- : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, V8CC:$cc),
- "fmovs$cc %icc, $F, $dst",
- [(set FPRegs:$dst,
- (V8selecticc FPRegs:$F, FPRegs:$T, imm:$cc, ICC))]>;
- def FMOVD_ICC
- : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, V8CC:$cc),
- "fmovd$cc %icc, $F, $dst",
- [(set DFPRegs:$dst,
- (V8selecticc DFPRegs:$F, DFPRegs:$T, imm:$cc, ICC))]>;
- def FMOVS_FCC
- : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, V8CC:$cc),
- "fmovs$cc %fcc, $F, $dst",
- [(set FPRegs:$dst,
- (V8selectfcc FPRegs:$F, FPRegs:$T, imm:$cc, FCC))]>;
- def FMOVD_FCC
- : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, V8CC:$cc),
- "fmovd$cc %fcc, $F, $dst",
- [(set DFPRegs:$dst,
- (V8selectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc, FCC))]>;
+ let Uses = [ICC] in {
+ def MOVICCrr
+ : Pseudo<(outs IntRegs:$rd), (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cc),
+ "mov$cc %icc, $rs2, $rd",
+ [(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cc))]>;
+ def MOVICCri
+ : Pseudo<(outs IntRegs:$rd), (ins i32imm:$i, IntRegs:$f, CCOp:$cc),
+ "mov$cc %icc, $i, $rd",
+ [(set i32:$rd, (SPselecticc simm11:$i, i32:$f, imm:$cc))]>;
+ }
+
+ let Uses = [FCC] in {
+ def MOVFCCrr
+ : Pseudo<(outs IntRegs:$rd), (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cc),
+ "mov$cc %fcc0, $rs2, $rd",
+ [(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cc))]>;
+ def MOVFCCri
+ : Pseudo<(outs IntRegs:$rd), (ins i32imm:$i, IntRegs:$f, CCOp:$cc),
+ "mov$cc %fcc0, $i, $rd",
+ [(set i32:$rd, (SPselectfcc simm11:$i, i32:$f, imm:$cc))]>;
+ }
+
+ let Uses = [ICC] in {
+ def FMOVS_ICC
+ : Pseudo<(outs FPRegs:$rd), (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cc),
+ "fmovs$cc %icc, $rs2, $rd",
+ [(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cc))]>;
+ def FMOVD_ICC
+ : Pseudo<(outs DFPRegs:$rd), (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cc),
+ "fmovd$cc %icc, $rs2, $rd",
+ [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cc))]>;
+ }
+
+ let Uses = [FCC] in {
+ def FMOVS_FCC
+ : Pseudo<(outs FPRegs:$rd), (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cc),
+ "fmovs$cc %fcc0, $rs2, $rd",
+ [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cc))]>;
+ def FMOVD_FCC
+ : Pseudo<(outs DFPRegs:$rd), (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cc),
+ "fmovd$cc %fcc0, $rs2, $rd",
+ [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cc))]>;
+ }
}
// Floating-Point Move Instructions, p. 164 of the V9 manual.
let Predicates = [HasV9] in {
def FMOVD : F3_3<2, 0b110100, 0b000000010,
- (ops DFPRegs:$dst, DFPRegs:$src),
+ (outs DFPRegs:$dst), (ins DFPRegs:$src),
"fmovd $src, $dst", []>;
- def FNEGD : F3_3<2, 0b110100, 0b000000110,
- (ops DFPRegs:$dst, DFPRegs:$src),
+ def FNEGD : F3_3<2, 0b110100, 0b000000110,
+ (outs DFPRegs:$dst), (ins DFPRegs:$src),
"fnegd $src, $dst",
- [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
- def FABSD : F3_3<2, 0b110100, 0b000001010,
- (ops DFPRegs:$dst, DFPRegs:$src),
+ [(set f64:$dst, (fneg f64:$src))]>;
+ def FABSD : F3_3<2, 0b110100, 0b000001010,
+ (outs DFPRegs:$dst), (ins DFPRegs:$src),
"fabsd $src, $dst",
- [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>;
+ [(set f64:$dst, (fabs f64:$src))]>;
}
// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
// the top 32-bits before using it. To do this clearing, we use a SLLri X,0.
-def POPCrr : F3_1<2, 0b101110,
- (ops IntRegs:$dst, IntRegs:$src),
+def POPCrr : F3_1<2, 0b101110,
+ (outs IntRegs:$dst), (ins IntRegs:$src),
"popc $src, $dst", []>, Requires<[HasV9]>;
-def : Pat<(ctpop IntRegs:$src),
- (POPCrr (SLLri IntRegs:$src, 0))>;
+def : Pat<(ctpop i32:$src),
+ (POPCrr (SLLri $src, 0))>;
//===----------------------------------------------------------------------===//
// Non-Instruction Patterns
// Small immediates.
def : Pat<(i32 simm13:$val),
- (ORri G0, imm:$val)>;
+ (ORri (i32 G0), imm:$val)>;
// Arbitrary immediates.
def : Pat<(i32 imm:$val),
(ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
+// subc
+def : Pat<(subc i32:$b, i32:$c),
+ (SUBCCrr $b, $c)>;
+def : Pat<(subc i32:$b, simm13:$val),
+ (SUBCCri $b, imm:$val)>;
+
// Global addresses, constant pool entries
-def : Pat<(V8hi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
-def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;
-def : Pat<(V8hi tconstpool:$in), (SETHIi tconstpool:$in)>;
-def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>;
+def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
+def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>;
+def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
+def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>;
-// Add reg, lo. This is used when taking the addr of a global/constpool entry.
-def : Pat<(add IntRegs:$r, (V8lo tglobaladdr:$in)),
- (ADDri IntRegs:$r, tglobaladdr:$in)>;
-def : Pat<(add IntRegs:$r, (V8lo tconstpool:$in)),
- (ADDri IntRegs:$r, tconstpool:$in)>;
+// Blockaddress
+def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>;
+def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>;
+// Add reg, lo. This is used when taking the addr of a global/constpool entry.
+def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>;
+def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>;
+def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)),
+ (ADDri $r, tblockaddress:$in)>;
-// Calls:
+// Calls:
def : Pat<(call tglobaladdr:$dst),
(CALL tglobaladdr:$dst)>;
-def : Pat<(call externalsym:$dst),
- (CALL externalsym:$dst)>;
-
-def : Pat<(ret), (RETL)>;
+def : Pat<(call texternalsym:$dst),
+ (CALL texternalsym:$dst)>;
// Map integer extload's to zextloads.
-def : Pat<(i32 (extload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>;
-def : Pat<(i32 (extload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>;
-def : Pat<(i32 (extload ADDRrr:$src, i8)), (LDUBrr ADDRrr:$src)>;
-def : Pat<(i32 (extload ADDRri:$src, i8)), (LDUBri ADDRri:$src)>;
-def : Pat<(i32 (extload ADDRrr:$src, i16)), (LDUHrr ADDRrr:$src)>;
-def : Pat<(i32 (extload ADDRri:$src, i16)), (LDUHri ADDRri:$src)>;
+def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
+def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
+def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
+def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
+def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;
+def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>;
// zextload bool -> zextload byte
-def : Pat<(i32 (zextload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>;
-def : Pat<(i32 (zextload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>;
-
-// truncstore bool -> truncstore byte.
-def : Pat<(truncstore IntRegs:$src, ADDRrr:$addr, i1),
- (STBrr ADDRrr:$addr, IntRegs:$src)>;
-def : Pat<(truncstore IntRegs:$src, ADDRri:$addr, i1),
- (STBri ADDRri:$addr, IntRegs:$src)>;
+def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
+def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
+
+// store 0, addr -> store %g0, addr
+def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>;
+def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>;
+
+include "SparcInstr64Bit.td"
projects / oota-llvm.git / blobdiff