Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from

[oota-llvm.git] / lib / Target / Sparc / SparcISelDAGToDAG.cpp

diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index f361b4670a54f55502f5d25010b551a787ca3ccf..7a093f08e7f0d136073bb44053ba16e0a720bfb2 100644 (file)
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -112,6 +112,7 @@ namespace {
                                                 uint64_t Mask,
                                                 uint64_t &KnownZero, 
                                                 uint64_t &KnownOne,
+                                                const SelectionDAG &DAG,
                                                 unsigned Depth = 0) const;
     
     virtual std::vector<SDOperand>
@@ -261,6 +262,7 @@ void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
                                                          uint64_t Mask,
                                                          uint64_t &KnownZero, 
                                                          uint64_t &KnownOne,
+                                                         const SelectionDAG &DAG,
                                                          unsigned Depth) const {
   uint64_t KnownZero2, KnownOne2;
   KnownZero = KnownOne = 0;   // Don't know anything.
@@ -269,8 +271,10 @@ void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
   default: break;
   case SPISD::SELECT_ICC:
   case SPISD::SELECT_FCC:
-    ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
-    ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
+    DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne,
+                          Depth+1);
+    DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2,
+                          Depth+1);
     assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 
     assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 
     
@@ -516,9 +520,11 @@ SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
     case MVT::i16: {
       // Promote the integer to 32-bits.  If the input type is signed, use a
       // sign extend, otherwise use a zero extend.
-      ISD::NodeType ExtendKind = ISD::ZERO_EXTEND;
-      if (Args[i].isSigned)
+      ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
+      if (Args[i].isSExt)
         ExtendKind = ISD::SIGN_EXTEND;
+      else if (Args[i].isZExt)
+        ExtendKind = ISD::ZERO_EXTEND;
       Val = DAG.getNode(ExtendKind, MVT::i32, Val);
       // FALL THROUGH
     }
@@ -868,7 +874,11 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
     }
     return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
   }
+  // Frame & Return address.  Currently unimplemented
+  case ISD::RETURNADDR:         break;
+  case ISD::FRAMEADDR:          break;
   }
+  return SDOperand();
 }
 
 MachineBasicBlock *