: AMDGPUInst <outs, ins, asm, pattern> {
field bits<64> Inst;
- bit TransOnly = 0;
bit Trig = 0;
bit Op3 = 0;
bit isVector = 0;
bits<2> FlagOperandIdx = 0;
bit Op1 = 0;
bit Op2 = 0;
+ bit LDS_1A = 0;
+ bit LDS_1A1D = 0;
bit HasNativeOperands = 0;
bit VTXInst = 0;
bit TEXInst = 0;
+ bit ALUInst = 0;
+ bit IsExport = 0;
+ bit LDS_1A2D = 0;
let Namespace = "AMDGPU";
let OutOperandList = outs;
let Pattern = pattern;
let Itinerary = itin;
- let TSFlags{0} = TransOnly;
+ // No AsmMatcher support.
+ let isCodeGenOnly = 1;
+
let TSFlags{4} = Trig;
let TSFlags{5} = Op3;
let TSFlags{11} = Op2;
let TSFlags{12} = VTXInst;
let TSFlags{13} = TEXInst;
+ let TSFlags{14} = ALUInst;
+ let TSFlags{15} = LDS_1A;
+ let TSFlags{16} = LDS_1A1D;
+ let TSFlags{17} = IsExport;
+ let TSFlags{18} = LDS_1A2D;
}
//===----------------------------------------------------------------------===//
// ALU instructions
//===----------------------------------------------------------------------===//
-class R600ALU_Word0 {
+class R600_ALU_LDS_Word0 {
field bits<32> Word0;
bits<11> src0;
- bits<1> src0_neg;
bits<1> src0_rel;
bits<11> src1;
bits<1> src1_rel;
- bits<1> src1_neg;
bits<3> index_mode = 0;
bits<2> pred_sel;
bits<1> last;
let Word0{8-0} = src0_sel;
let Word0{9} = src0_rel;
let Word0{11-10} = src0_chan;
- let Word0{12} = src0_neg;
let Word0{21-13} = src1_sel;
let Word0{22} = src1_rel;
let Word0{24-23} = src1_chan;
- let Word0{25} = src1_neg;
let Word0{28-26} = index_mode;
let Word0{30-29} = pred_sel;
let Word0{31} = last;
}
+class R600ALU_Word0 : R600_ALU_LDS_Word0 {
+
+ bits<1> src0_neg;
+ bits<1> src1_neg;
+
+ let Word0{12} = src0_neg;
+ let Word0{25} = src1_neg;
+}
+
class R600ALU_Word1 {
field bits<32> Word1;
let Word1{17-13} = alu_inst;
}
+class R600LDS_Word1 {
+ field bits<32> Word1;
+
+ bits<11> src2;
+ bits<9> src2_sel = src2{8-0};
+ bits<2> src2_chan = src2{10-9};
+ bits<1> src2_rel;
+ // offset specifies the stride offset to the second set of data to be read
+ // from. This is a dword offset.
+ bits<5> alu_inst = 17; // OP3_INST_LDS_IDX_OP
+ bits<3> bank_swizzle;
+ bits<6> lds_op;
+ bits<2> dst_chan = 0;
+
+ let Word1{8-0} = src2_sel;
+ let Word1{9} = src2_rel;
+ let Word1{11-10} = src2_chan;
+ let Word1{17-13} = alu_inst;
+ let Word1{20-18} = bank_swizzle;
+ let Word1{26-21} = lds_op;
+ let Word1{30-29} = dst_chan;
+}
+
+
/*
XXX: R600 subtarget uses a slightly different encoding than the other
subtargets. We currently handle this in R600MCCodeEmitter, but we may
class VTX_WORD0 {
field bits<32> Word0;
- bits<7> SRC_GPR;
+ bits<7> src_gpr;
bits<5> VC_INST;
bits<2> FETCH_TYPE;
bits<1> FETCH_WHOLE_QUAD;
bits<8> BUFFER_ID;
bits<1> SRC_REL;
bits<2> SRC_SEL_X;
- bits<6> MEGA_FETCH_COUNT;
let Word0{4-0} = VC_INST;
let Word0{6-5} = FETCH_TYPE;
let Word0{7} = FETCH_WHOLE_QUAD;
let Word0{15-8} = BUFFER_ID;
- let Word0{22-16} = SRC_GPR;
+ let Word0{22-16} = src_gpr;
let Word0{23} = SRC_REL;
let Word0{25-24} = SRC_SEL_X;
+}
+
+class VTX_WORD0_eg : VTX_WORD0 {
+
+ bits<6> MEGA_FETCH_COUNT;
+
let Word0{31-26} = MEGA_FETCH_COUNT;
}
+class VTX_WORD0_cm : VTX_WORD0 {
+
+ bits<2> SRC_SEL_Y;
+ bits<2> STRUCTURED_READ;
+ bits<1> LDS_REQ;
+ bits<1> COALESCED_READ;
+
+ let Word0{27-26} = SRC_SEL_Y;
+ let Word0{29-28} = STRUCTURED_READ;
+ let Word0{30} = LDS_REQ;
+ let Word0{31} = COALESCED_READ;
+}
+
class VTX_WORD1_GPR {
field bits<32> Word1;
- bits<7> DST_GPR;
+ bits<7> dst_gpr;
bits<1> DST_REL;
bits<3> DST_SEL_X;
bits<3> DST_SEL_Y;
bits<1> FORMAT_COMP_ALL;
bits<1> SRF_MODE_ALL;
- let Word1{6-0} = DST_GPR;
+ let Word1{6-0} = dst_gpr;
let Word1{7} = DST_REL;
let Word1{8} = 0; // Reserved
let Word1{11-9} = DST_SEL_X;