Canonicalize header guards into a common format.

[oota-llvm.git] / lib / Target / PowerPC / PPCTargetMachine.h

diff --git a/lib/Target/PowerPC/PPCTargetMachine.h b/lib/Target/PowerPC/PPCTargetMachine.h
index 21dc0a0c62db52f6642b74b5060b3d2a0414d578..51bacb7fd8ba6bd48dee1d1f8f5a6ee968c938ff 100644 (file)
--- a/lib/Target/PowerPC/PPCTargetMachine.h
+++ b/lib/Target/PowerPC/PPCTargetMachine.h
@@ -1,48 +1,68 @@
-//===-- PPC32TargetMachine.h - Define TargetMachine for PowerPC -*- C++ -*-=//
-// 
+//===-- PPCTargetMachine.h - Define TargetMachine for PowerPC ---*- C++ -*-===//
+//
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
 //===----------------------------------------------------------------------===//
-// 
+//
 // This file declares the PowerPC specific subclass of TargetMachine.
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef POWERPC32_TARGETMACHINE_H
-#define POWERPC32_TARGETMACHINE_H
+#ifndef LLVM_LIB_TARGET_POWERPC_PPCTARGETMACHINE_H
+#define LLVM_LIB_TARGET_POWERPC_PPCTARGETMACHINE_H
 
-#include "PowerPCTargetMachine.h"
-#include "PPC32InstrInfo.h"
-#include "llvm/PassManager.h"
-#include <set>
+#include "PPCInstrInfo.h"
+#include "PPCSubtarget.h"
+#include "llvm/IR/DataLayout.h"
+#include "llvm/Target/TargetMachine.h"
 
 namespace llvm {
 
-class GlobalValue;
-class IntrinsicLowering;
-
-class PPC32TargetMachine : public PowerPCTargetMachine {
-  PPC32InstrInfo InstrInfo;
+/// PPCTargetMachine - Common code between 32-bit and 64-bit PowerPC targets.
+///
+class PPCTargetMachine : public LLVMTargetMachine {
+  PPCSubtarget        Subtarget;
 
 public:
-  PPC32TargetMachine(const Module &M, IntrinsicLowering *IL);
-  virtual const PPC32InstrInfo   *getInstrInfo() const { return &InstrInfo; }
-  virtual const MRegisterInfo *getRegisterInfo() const {
-    return &InstrInfo.getRegisterInfo();
-  }
+  PPCTargetMachine(const Target &T, StringRef TT,
+                   StringRef CPU, StringRef FS, const TargetOptions &Options,
+                   Reloc::Model RM, CodeModel::Model CM,
+                   CodeGenOpt::Level OL);
+
+  const PPCSubtarget *getSubtargetImpl() const override { return &Subtarget; }
 
-  static unsigned getModuleMatchQuality(const Module &M);
+  // Pass Pipeline Configuration
+  TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
+  bool addCodeEmitter(PassManagerBase &PM,
+                      JITCodeEmitter &JCE) override;
 
-  bool addPassesToEmitMachineCode(FunctionPassManager &PM,
-                                  MachineCodeEmitter &MCE);
+  /// \brief Register PPC analysis passes with a pass manager.
+  void addAnalysisPasses(PassManagerBase &PM) override;
+};
 
-  // Two shared sets between the instruction selector and the printer allow for
-  // correct linkage on Darwin
-  std::set<GlobalValue*> CalledFunctions;
-  std::set<GlobalValue*> AddressTaken;
+/// PPC32TargetMachine - PowerPC 32-bit target machine.
+///
+class PPC32TargetMachine : public PPCTargetMachine {
+  virtual void anchor();
+public:
+  PPC32TargetMachine(const Target &T, StringRef TT,
+                     StringRef CPU, StringRef FS, const TargetOptions &Options,
+                     Reloc::Model RM, CodeModel::Model CM,
+                     CodeGenOpt::Level OL);
+};
+
+/// PPC64TargetMachine - PowerPC 64-bit target machine.
+///
+class PPC64TargetMachine : public PPCTargetMachine {
+  virtual void anchor();
+public:
+  PPC64TargetMachine(const Target &T, StringRef TT,
+                     StringRef CPU, StringRef FS, const TargetOptions &Options,
+                     Reloc::Model RM, CodeModel::Model CM,
+                     CodeGenOpt::Level OL);
 };
 
 } // end namespace llvm