-//===- PowerPCSubtarget.cpp - PPC Subtarget Information -------------------===//
+//===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
//
// The LLVM Compiler Infrastructure
//
-// This file was developed by Nate Begeman and is distributed under the
-// University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
-// This file implements the PPC specific subclass of TargetSubtarget.
+// This file implements the PPC specific subclass of TargetSubtargetInfo.
//
//===----------------------------------------------------------------------===//
#include "PPCSubtarget.h"
#include "PPC.h"
-#include "llvm/Module.h"
+#include "PPCRegisterInfo.h"
+#include "llvm/IR/GlobalValue.h"
+#include "llvm/Support/Host.h"
+#include "llvm/Support/TargetRegistry.h"
#include "llvm/Target/TargetMachine.h"
-#include "PPCGenSubtarget.inc"
-using namespace llvm;
+#include <cstdlib>
-#if defined(__APPLE__)
-#include <mach/mach.h>
-#include <mach/mach_host.h>
-#include <mach/host_info.h>
-#include <mach/machine.h>
-
-/// GetCurrentPowerPCFeatures - Returns the current CPUs features.
-static const char *GetCurrentPowerPCCPU() {
- host_basic_info_data_t hostInfo;
- mach_msg_type_number_t infoCount;
-
- infoCount = HOST_BASIC_INFO_COUNT;
- host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo,
- &infoCount);
-
- if (hostInfo.cpu_type != CPU_TYPE_POWERPC) return "generic";
-
- switch(hostInfo.cpu_subtype) {
- case CPU_SUBTYPE_POWERPC_601: return "601";
- case CPU_SUBTYPE_POWERPC_602: return "602";
- case CPU_SUBTYPE_POWERPC_603: return "603";
- case CPU_SUBTYPE_POWERPC_603e: return "603e";
- case CPU_SUBTYPE_POWERPC_603ev: return "603ev";
- case CPU_SUBTYPE_POWERPC_604: return "604";
- case CPU_SUBTYPE_POWERPC_604e: return "604e";
- case CPU_SUBTYPE_POWERPC_620: return "620";
- case CPU_SUBTYPE_POWERPC_750: return "750";
- case CPU_SUBTYPE_POWERPC_7400: return "7400";
- case CPU_SUBTYPE_POWERPC_7450: return "7450";
- case CPU_SUBTYPE_POWERPC_970: return "970";
- default: ;
- }
-
- return "generic";
-}
-#endif
+#define GET_SUBTARGETINFO_TARGET_DESC
+#define GET_SUBTARGETINFO_CTOR
+#include "PPCGenSubtargetInfo.inc"
+using namespace llvm;
-PPCSubtarget::PPCSubtarget(const TargetMachine &tm, const Module &M,
+PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, bool is64Bit)
- : TM(tm)
+ : PPCGenSubtargetInfo(TT, CPU, FS)
, StackAlignment(16)
- , IsGigaProcessor(false)
+ , DarwinDirective(PPC::DIR_NONE)
+ , HasMFOCRF(false)
, Has64BitSupport(false)
, Use64BitRegs(false)
, IsPPC64(is64Bit)
, HasAltivec(false)
, HasFSQRT(false)
, HasSTFIWX(false)
- , IsDarwin(false)
- , HasLazyResolverStubs(false) {
+ , HasISEL(false)
+ , IsBookE(false)
+ , HasLazyResolverStubs(false)
+ , IsJITCodeModel(false)
+ , TargetTriple(TT) {
// Determine default and user specified characteristics
- std::string CPU = "generic";
-#if defined(__APPLE__)
- CPU = GetCurrentPowerPCCPU();
+ std::string CPUName = CPU;
+ if (CPUName.empty())
+ CPUName = "generic";
+#if (defined(__APPLE__) || defined(__linux__)) && \
+ (defined(__ppc__) || defined(__powerpc__))
+ if (CPUName == "generic")
+ CPUName = sys::getHostCPUName();
#endif
- // Parse features string.
- ParseSubtargetFeatures(FS, CPU);
+ // Initialize scheduling itinerary for the specified CPU.
+ InstrItins = getInstrItineraryForCPU(CPUName);
+
+ // Make sure 64-bit features are available when CPUname is generic
+ std::string FullFS = FS;
// If we are generating code for ppc64, verify that options make sense.
if (is64Bit) {
- if (!has64BitSupport()) {
- cerr << "PPC: Generation of 64-bit code for a 32-bit processor "
- << "requested. Ignoring 32-bit processor feature.\n";
- Has64BitSupport = true;
- }
+ Has64BitSupport = true;
// Silently force 64-bit register use on ppc64.
Use64BitRegs = true;
+ if (!FullFS.empty())
+ FullFS = "+64bit," + FullFS;
+ else
+ FullFS = "+64bit";
}
-
+
+ // Parse features string.
+ ParseSubtargetFeatures(CPUName, FullFS);
+
// If the user requested use of 64-bit regs, but the cpu selected doesn't
- // support it, warn and ignore.
- if (use64BitRegs() && !has64BitSupport()) {
- cerr << "PPC: 64-bit registers requested on CPU without support. "
- << "Disabling 64-bit register use.\n";
+ // support it, ignore.
+ if (use64BitRegs() && !has64BitSupport())
Use64BitRegs = false;
- }
-
- // Set the boolean corresponding to the current target triple, or the default
- // if one cannot be determined, to true.
- const std::string& TT = M.getTargetTriple();
- if (TT.length() > 5) {
- IsDarwin = TT.find("-darwin") != std::string::npos;
- } else if (TT.empty()) {
-#if defined(__APPLE__)
- IsDarwin = true;
-#endif
- }
// Set up darwin-specific properties.
- if (IsDarwin) {
+ if (isDarwin())
HasLazyResolverStubs = true;
- AsmFlavor = NewMnemonic;
- } else {
- AsmFlavor = OldMnemonic;
- }
}
/// SetJITMode - This is called to inform the subtarget info that we are
// everything is. This matters for PPC64, which codegens in PIC mode without
// stubs.
HasLazyResolverStubs = false;
+
+ // Calls to external functions need to use indirect calls
+ IsJITCodeModel = true;
}
/// hasLazyResolverStub - Return true if accesses to the specified global have
/// to go through a dyld lazy resolution stub. This means that an extra load
/// is required to get the address of the global.
-bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV) const {
- // We never hae stubs if HasLazyResolverStubs=false or if in static mode.
+bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV,
+ const TargetMachine &TM) const {
+ // We never have stubs if HasLazyResolverStubs=false or if in static mode.
if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static)
return false;
-
+ // If symbol visibility is hidden, the extra load is not needed if
+ // the symbol is definitely defined in the current translation unit.
+ bool isDecl = GV->isDeclaration() && !GV->isMaterializable();
+ if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage())
+ return false;
return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
- (GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode());
+ GV->hasCommonLinkage() || isDecl;
}
+
+bool PPCSubtarget::enablePostRAScheduler(
+ CodeGenOpt::Level OptLevel,
+ TargetSubtargetInfo::AntiDepBreakMode& Mode,
+ RegClassVector& CriticalPathRCs) const {
+ // FIXME: It would be best to use TargetSubtargetInfo::ANTIDEP_ALL here,
+ // but we can't because we can't reassign the cr registers. There is a
+ // dependence between the cr register and the RLWINM instruction used
+ // to extract its value which the anti-dependency breaker can't currently
+ // see. Maybe we should make a late-expanded pseudo to encode this dependency.
+ // (the relevant code is in PPCDAGToDAGISel::SelectSETCC)
+
+ Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
+
+ CriticalPathRCs.clear();
+
+ if (isPPC64())
+ CriticalPathRCs.push_back(&PPC::G8RCRegClass);
+ else
+ CriticalPathRCs.push_back(&PPC::GPRCRegClass);
+
+ CriticalPathRCs.push_back(&PPC::F8RCRegClass);
+ CriticalPathRCs.push_back(&PPC::VRRCRegClass);
+
+ return OptLevel >= CodeGenOpt::Default;
+}
+
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