//
// The LLVM Compiler Infrastructure
//
-// This file was developed by Chris Lattner and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
//
//===----------------------------------------------------------------------===//
+#define DEBUG_TYPE "ppc-codegen"
#include "PPC.h"
+#include "PPCPredicates.h"
#include "PPCTargetMachine.h"
#include "PPCISelLowering.h"
#include "PPCHazardRecognizers.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/SSARegMap.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/ADT/Statistic.h"
#include "llvm/Constants.h"
#include "llvm/GlobalValue.h"
#include "llvm/Intrinsics.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
-#include <iostream>
+#include "llvm/Support/Compiler.h"
+#include <queue>
#include <set>
using namespace llvm;
namespace {
- Statistic<> FrameOff("ppc-codegen", "Number of frame idx offsets collapsed");
-
//===--------------------------------------------------------------------===//
/// PPCDAGToDAGISel - PPC specific code to select PPC machine
/// instructions for SelectionDAG operations.
///
- class PPCDAGToDAGISel : public SelectionDAGISel {
+ class VISIBILITY_HIDDEN PPCDAGToDAGISel : public SelectionDAGISel {
PPCTargetMachine &TM;
PPCTargetLowering PPCLowering;
+ const PPCSubtarget &PPCSubTarget;
unsigned GlobalBaseReg;
public:
PPCDAGToDAGISel(PPCTargetMachine &tm)
: SelectionDAGISel(PPCLowering), TM(tm),
- PPCLowering(*TM.getTargetLowering()) {}
+ PPCLowering(*TM.getTargetLowering()),
+ PPCSubTarget(*TM.getSubtargetImpl()) {}
virtual bool runOnFunction(Function &Fn) {
// Make sure we re-emit a set of the global base reg if necessary
return CurDAG->getTargetConstant(Imm, MVT::i32);
}
+ /// getI64Imm - Return a target constant with the specified value, of type
+ /// i64.
+ inline SDOperand getI64Imm(uint64_t Imm) {
+ return CurDAG->getTargetConstant(Imm, MVT::i64);
+ }
+
+ /// getSmallIPtrImm - Return a target constant of pointer type.
+ inline SDOperand getSmallIPtrImm(unsigned Imm) {
+ return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy());
+ }
+
+ /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s
+ /// with any number of 0s on either side. The 1s are allowed to wrap from
+ /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs.
+ /// 0x0F0F0000 is not, since all 1s are not contiguous.
+ static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME);
+
+
+ /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
+ /// rotate and mask opcode and mask operation.
+ static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
+ unsigned &SH, unsigned &MB, unsigned &ME);
+
/// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
/// base register. Return the virtual register that holds this value.
- SDOperand getGlobalBaseReg();
+ SDNode *getGlobalBaseReg();
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
- void Select(SDOperand &Result, SDOperand Op);
+ SDNode *Select(SDOperand Op);
SDNode *SelectBitfieldInsert(SDNode *N);
/// SelectAddrImm - Returns true if the address N can be represented by
/// a base register plus a signed 16-bit displacement [r+imm].
- bool SelectAddrImm(SDOperand N, SDOperand &Disp, SDOperand &Base);
+ bool SelectAddrImm(SDOperand Op, SDOperand N, SDOperand &Disp,
+ SDOperand &Base) {
+ return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG);
+ }
+
+ /// SelectAddrImmOffs - Return true if the operand is valid for a preinc
+ /// immediate field. Because preinc imms have already been validated, just
+ /// accept it.
+ bool SelectAddrImmOffs(SDOperand Op, SDOperand N, SDOperand &Out) const {
+ Out = N;
+ return true;
+ }
/// SelectAddrIdx - Given the specified addressed, check to see if it can be
/// represented as an indexed [r+r] operation. Returns false if it can
/// be represented by [r+imm], which are preferred.
- bool SelectAddrIdx(SDOperand N, SDOperand &Base, SDOperand &Index);
+ bool SelectAddrIdx(SDOperand Op, SDOperand N, SDOperand &Base,
+ SDOperand &Index) {
+ return PPCLowering.SelectAddressRegReg(N, Base, Index, *CurDAG);
+ }
/// SelectAddrIdxOnly - Given the specified addressed, force it to be
/// represented as an indexed [r+r] operation.
- bool SelectAddrIdxOnly(SDOperand N, SDOperand &Base, SDOperand &Index);
+ bool SelectAddrIdxOnly(SDOperand Op, SDOperand N, SDOperand &Base,
+ SDOperand &Index) {
+ return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
+ }
/// SelectAddrImmShift - Returns true if the address N can be represented by
/// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
/// for use by STD and friends.
- bool SelectAddrImmShift(SDOperand N, SDOperand &Disp, SDOperand &Base);
-
+ bool SelectAddrImmShift(SDOperand Op, SDOperand N, SDOperand &Disp,
+ SDOperand &Base) {
+ return PPCLowering.SelectAddressRegImmShift(N, Disp, Base, *CurDAG);
+ }
+
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
switch (ConstraintCode) {
default: return true;
case 'm': // memory
- if (!SelectAddrIdx(Op, Op0, Op1))
- SelectAddrImm(Op, Op0, Op1);
+ if (!SelectAddrIdx(Op, Op, Op0, Op1))
+ SelectAddrImm(Op, Op, Op0, Op1);
break;
case 'o': // offsetable
- if (!SelectAddrImm(Op, Op0, Op1)) {
- Select(Op0, Op); // r+0.
- Op1 = getI32Imm(0);
+ if (!SelectAddrImm(Op, Op, Op0, Op1)) {
+ Op0 = Op;
+ AddToISelQueue(Op0); // r+0.
+ Op1 = getSmallIPtrImm(0);
}
break;
case 'v': // not offsetable
- SelectAddrIdxOnly(Op, Op0, Op1);
+ SelectAddrIdxOnly(Op, Op, Op0, Op1);
break;
}
return "PowerPC DAG->DAG Pattern Instruction Selection";
}
- /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for this
- /// target when scheduling the DAG.
+ /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
+ /// this target when scheduling the DAG.
virtual HazardRecognizer *CreateTargetHazardRecognizer() {
// Should use subtarget info to pick the right hazard recognizer. For
// now, always return a PPC970 recognizer.
#include "PPCGenDAGISel.inc"
private:
- SDOperand SelectSETCC(SDOperand Op);
- SDOperand SelectCALL(SDOperand Op);
+ SDNode *SelectSETCC(SDOperand Op);
};
}
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
void PPCDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
DEBUG(BB->dump());
-
- // The selection process is inherently a bottom-up recursive process (users
- // select their uses before themselves). Given infinite stack space, we
- // could just start selecting on the root and traverse the whole graph. In
- // practice however, this causes us to run out of stack space on large basic
- // blocks. To avoid this problem, select the entry node, then all its uses,
- // iteratively instead of recursively.
- std::vector<SDOperand> Worklist;
- Worklist.push_back(DAG.getEntryNode());
-
- // Note that we can do this in the PPC target (scanning forward across token
- // chain edges) because no nodes ever get folded across these edges. On a
- // target like X86 which supports load/modify/store operations, this would
- // have to be more careful.
- while (!Worklist.empty()) {
- SDOperand Node = Worklist.back();
- Worklist.pop_back();
-
- // Chose from the least deep of the top two nodes.
- if (!Worklist.empty() &&
- Worklist.back().Val->getNodeDepth() < Node.Val->getNodeDepth())
- std::swap(Worklist.back(), Node);
-
- if ((Node.Val->getOpcode() >= ISD::BUILTIN_OP_END &&
- Node.Val->getOpcode() < PPCISD::FIRST_NUMBER) ||
- CodeGenMap.count(Node)) continue;
-
- for (SDNode::use_iterator UI = Node.Val->use_begin(),
- E = Node.Val->use_end(); UI != E; ++UI) {
- // Scan the values. If this use has a value that is a token chain, add it
- // to the worklist.
- SDNode *User = *UI;
- for (unsigned i = 0, e = User->getNumValues(); i != e; ++i)
- if (User->getValueType(i) == MVT::Other) {
- Worklist.push_back(SDOperand(User, i));
- break;
- }
- }
- // Finally, legalize this node.
- SDOperand Dummy;
- Select(Dummy, Node);
- }
-
// Select target instructions for the DAG.
DAG.setRoot(SelectRoot(DAG.getRoot()));
- CodeGenMap.clear();
DAG.RemoveDeadNodes();
// Emit machine code to BB.
// In this case, there will be virtual registers of vector type type created
// by the scheduler. Detect them now.
MachineFunction &Fn = MachineFunction::get(&F);
- SSARegMap *RegMap = Fn.getSSARegMap();
bool HasVectorVReg = false;
for (unsigned i = MRegisterInfo::FirstVirtualRegister,
- e = RegMap->getLastVirtReg()+1; i != e; ++i)
- if (RegMap->getRegClass(i) == &PPC::VRRCRegClass) {
+ e = RegInfo->getLastVirtReg()+1; i != e; ++i)
+ if (RegInfo->getRegClass(i) == &PPC::VRRCRegClass) {
HasVectorVReg = true;
break;
}
// Create two vregs - one to hold the VRSAVE register that is live-in to the
// function and one for the value after having bits or'd into it.
- unsigned InVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
- unsigned UpdatedVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
+ unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
+ unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
+ const TargetInstrInfo &TII = *TM.getInstrInfo();
MachineBasicBlock &EntryBB = *Fn.begin();
// Emit the following code into the entry block:
// InVRSAVE = MFVRSAVE
// UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
// MTVRSAVE UpdatedVRSAVE
MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
- BuildMI(EntryBB, IP, PPC::MFVRSAVE, 0, InVRSAVE);
- BuildMI(EntryBB, IP, PPC::UPDATE_VRSAVE, 1, UpdatedVRSAVE).addReg(InVRSAVE);
- BuildMI(EntryBB, IP, PPC::MTVRSAVE, 1).addReg(UpdatedVRSAVE);
+ BuildMI(EntryBB, IP, TII.get(PPC::MFVRSAVE), InVRSAVE);
+ BuildMI(EntryBB, IP, TII.get(PPC::UPDATE_VRSAVE),
+ UpdatedVRSAVE).addReg(InVRSAVE);
+ BuildMI(EntryBB, IP, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
// Find all return blocks, outputting a restore in each epilog.
- const TargetInstrInfo &TII = *TM.getInstrInfo();
for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
if (!BB->empty() && TII.isReturn(BB->back().getOpcode())) {
IP = BB->end(); --IP;
// Skip over all terminator instructions, which are part of the return
// sequence.
MachineBasicBlock::iterator I2 = IP;
- while (I2 != BB->begin() && TII.isTerminatorInstr((--I2)->getOpcode()))
+ while (I2 != BB->begin() && (--I2)->getDesc()->isTerminator())
IP = I2;
// Emit: MTVRSAVE InVRSave
- BuildMI(*BB, IP, PPC::MTVRSAVE, 1).addReg(InVRSAVE);
+ BuildMI(*BB, IP, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
}
}
}
/// getGlobalBaseReg - Output the instructions required to put the
/// base address to use for accessing globals into a register.
///
-SDOperand PPCDAGToDAGISel::getGlobalBaseReg() {
+SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
if (!GlobalBaseReg) {
+ const TargetInstrInfo &TII = *TM.getInstrInfo();
// Insert the set of GlobalBaseReg into the first MBB of the function
MachineBasicBlock &FirstMBB = BB->getParent()->front();
MachineBasicBlock::iterator MBBI = FirstMBB.begin();
- SSARegMap *RegMap = BB->getParent()->getSSARegMap();
- // FIXME: when we get to LP64, we will need to create the appropriate
- // type of register here.
- GlobalBaseReg = RegMap->createVirtualRegister(PPC::GPRCRegisterClass);
- BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
- BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg);
+
+ if (PPCLowering.getPointerTy() == MVT::i32) {
+ GlobalBaseReg = RegInfo->createVirtualRegister(PPC::GPRCRegisterClass);
+ BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR), PPC::LR);
+ BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR), GlobalBaseReg);
+ } else {
+ GlobalBaseReg = RegInfo->createVirtualRegister(PPC::G8RCRegisterClass);
+ BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR8), PPC::LR8);
+ BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR8), GlobalBaseReg);
+ }
}
- return CurDAG->getRegister(GlobalBaseReg, MVT::i32);
+ return CurDAG->getRegister(GlobalBaseReg, PPCLowering.getPointerTy()).Val;
}
+/// isIntS16Immediate - This method tests to see if the node is either a 32-bit
+/// or 64-bit immediate, and if the value can be accurately represented as a
+/// sign extension from a 16-bit value. If so, this returns true and the
+/// immediate.
+static bool isIntS16Immediate(SDNode *N, short &Imm) {
+ if (N->getOpcode() != ISD::Constant)
+ return false;
-// isIntImmediate - This method tests to see if a constant operand.
-// If so Imm will receive the 32 bit value.
-static bool isIntImmediate(SDNode *N, unsigned& Imm) {
- if (N->getOpcode() == ISD::Constant) {
+ Imm = (short)cast<ConstantSDNode>(N)->getValue();
+ if (N->getValueType(0) == MVT::i32)
+ return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue();
+ else
+ return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
+}
+
+static bool isIntS16Immediate(SDOperand Op, short &Imm) {
+ return isIntS16Immediate(Op.Val, Imm);
+}
+
+
+/// isInt32Immediate - This method tests to see if the node is a 32-bit constant
+/// operand. If so Imm will receive the 32-bit value.
+static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
+ if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
Imm = cast<ConstantSDNode>(N)->getValue();
return true;
}
return false;
}
-// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s with
-// any number of 0s on either side. The 1s are allowed to wrap from LSB to
-// MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is
-// not, since all 1s are not contiguous.
-static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
+/// isInt64Immediate - This method tests to see if the node is a 64-bit constant
+/// operand. If so Imm will receive the 64-bit value.
+static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
+ if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
+ Imm = cast<ConstantSDNode>(N)->getValue();
+ return true;
+ }
+ return false;
+}
+
+// isInt32Immediate - This method tests to see if a constant operand.
+// If so Imm will receive the 32 bit value.
+static bool isInt32Immediate(SDOperand N, unsigned &Imm) {
+ return isInt32Immediate(N.Val, Imm);
+}
+
+
+// isOpcWithIntImmediate - This method tests to see if the node is a specific
+// opcode and that it has a immediate integer right operand.
+// If so Imm will receive the 32 bit value.
+static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
+ return N->getOpcode() == Opc && isInt32Immediate(N->getOperand(1).Val, Imm);
+}
+
+bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
if (isShiftedMask_32(Val)) {
// look for the first non-zero bit
MB = CountLeadingZeros_32(Val);
return false;
}
-// isRotateAndMask - Returns true if Mask and Shift can be folded into a rotate
-// and mask opcode and mask operation.
-static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
- unsigned &SH, unsigned &MB, unsigned &ME) {
+bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
+ bool IsShiftMask, unsigned &SH,
+ unsigned &MB, unsigned &ME) {
// Don't even go down this path for i64, since different logic will be
// necessary for rldicl/rldicr/rldimi.
if (N->getValueType(0) != MVT::i32)
unsigned Indeterminant = ~0; // bit mask marking indeterminant results
unsigned Opcode = N->getOpcode();
if (N->getNumOperands() != 2 ||
- !isIntImmediate(N->getOperand(1).Val, Shift) || (Shift > 31))
+ !isInt32Immediate(N->getOperand(1).Val, Shift) || (Shift > 31))
return false;
if (Opcode == ISD::SHL) {
Indeterminant = ~(0xFFFFFFFFu >> Shift);
// adjust for the left rotate
Shift = 32 - Shift;
+ } else if (Opcode == ISD::ROTL) {
+ Indeterminant = 0;
} else {
return false;
}
// if the mask doesn't intersect any Indeterminant bits
if (Mask && !(Mask & Indeterminant)) {
- SH = Shift;
+ SH = Shift & 31;
// make sure the mask is still a mask (wrap arounds may not be)
return isRunOfOnes(Mask, MB, ME);
}
return false;
}
-// isOpcWithIntImmediate - This method tests to see if the node is a specific
-// opcode and that it has a immediate integer right operand.
-// If so Imm will receive the 32 bit value.
-static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
- return N->getOpcode() == Opc && isIntImmediate(N->getOperand(1).Val, Imm);
-}
-
-// isIntImmediate - This method tests to see if a constant operand.
-// If so Imm will receive the 32 bit value.
-static bool isIntImmediate(SDOperand N, unsigned& Imm) {
- if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
- Imm = (unsigned)CN->getSignExtended();
- return true;
- }
- return false;
-}
-
/// SelectBitfieldInsert - turn an or of two masked values into
/// the rotate left word immediate then mask insert (rlwimi) instruction.
-/// Returns true on success, false if the caller still needs to select OR.
-///
-/// Patterns matched:
-/// 1. or shl, and 5. or and, and
-/// 2. or and, shl 6. or shl, shr
-/// 3. or shr, and 7. or shr, shl
-/// 4. or and, shr
SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
- bool IsRotate = false;
- unsigned TgtMask = 0xFFFFFFFF, InsMask = 0xFFFFFFFF, SH = 0;
- unsigned Value;
-
SDOperand Op0 = N->getOperand(0);
SDOperand Op1 = N->getOperand(1);
- unsigned Op0Opc = Op0.getOpcode();
- unsigned Op1Opc = Op1.getOpcode();
+ uint64_t LKZ, LKO, RKZ, RKO;
+ CurDAG->ComputeMaskedBits(Op0, 0xFFFFFFFFULL, LKZ, LKO);
+ CurDAG->ComputeMaskedBits(Op1, 0xFFFFFFFFULL, RKZ, RKO);
- // Verify that we have the correct opcodes
- if (ISD::SHL != Op0Opc && ISD::SRL != Op0Opc && ISD::AND != Op0Opc)
- return false;
- if (ISD::SHL != Op1Opc && ISD::SRL != Op1Opc && ISD::AND != Op1Opc)
- return false;
-
- // Generate Mask value for Target
- if (isIntImmediate(Op0.getOperand(1), Value)) {
- switch(Op0Opc) {
- case ISD::SHL: TgtMask <<= Value; break;
- case ISD::SRL: TgtMask >>= Value; break;
- case ISD::AND: TgtMask &= Value; break;
- }
- } else {
- return 0;
- }
-
- // Generate Mask value for Insert
- if (!isIntImmediate(Op1.getOperand(1), Value))
- return 0;
-
- switch(Op1Opc) {
- case ISD::SHL:
- SH = Value;
- InsMask <<= SH;
- if (Op0Opc == ISD::SRL) IsRotate = true;
- break;
- case ISD::SRL:
- SH = Value;
- InsMask >>= SH;
- SH = 32-SH;
- if (Op0Opc == ISD::SHL) IsRotate = true;
- break;
- case ISD::AND:
- InsMask &= Value;
- break;
- }
-
- // If both of the inputs are ANDs and one of them has a logical shift by
- // constant as its input, make that AND the inserted value so that we can
- // combine the shift into the rotate part of the rlwimi instruction
- bool IsAndWithShiftOp = false;
- if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
- if (Op1.getOperand(0).getOpcode() == ISD::SHL ||
- Op1.getOperand(0).getOpcode() == ISD::SRL) {
- if (isIntImmediate(Op1.getOperand(0).getOperand(1), Value)) {
- SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value;
- IsAndWithShiftOp = true;
- }
- } else if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
- Op0.getOperand(0).getOpcode() == ISD::SRL) {
- if (isIntImmediate(Op0.getOperand(0).getOperand(1), Value)) {
- std::swap(Op0, Op1);
- std::swap(TgtMask, InsMask);
- SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value;
- IsAndWithShiftOp = true;
- }
- }
- }
+ unsigned TargetMask = LKZ;
+ unsigned InsertMask = RKZ;
- // Verify that the Target mask and Insert mask together form a full word mask
- // and that the Insert mask is a run of set bits (which implies both are runs
- // of set bits). Given that, Select the arguments and generate the rlwimi
- // instruction.
- unsigned MB, ME;
- if (((TgtMask & InsMask) == 0) && isRunOfOnes(InsMask, MB, ME)) {
- bool fullMask = (TgtMask ^ InsMask) == 0xFFFFFFFF;
- bool Op0IsAND = Op0Opc == ISD::AND;
- // Check for rotlwi / rotrwi here, a special case of bitfield insert
- // where both bitfield halves are sourced from the same value.
- if (IsRotate && fullMask &&
- N->getOperand(0).getOperand(0) == N->getOperand(1).getOperand(0)) {
- SDOperand Tmp;
- Select(Tmp, N->getOperand(0).getOperand(0));
- return CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Tmp,
- getI32Imm(SH), getI32Imm(0), getI32Imm(31));
- }
- SDOperand Tmp1, Tmp2;
- Select(Tmp1, ((Op0IsAND && fullMask) ? Op0.getOperand(0) : Op0));
- Select(Tmp2, (IsAndWithShiftOp ? Op1.getOperand(0).getOperand(0)
- : Op1.getOperand(0)));
- return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp1, Tmp2,
- getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
- }
- return 0;
-}
+ if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
+ unsigned Op0Opc = Op0.getOpcode();
+ unsigned Op1Opc = Op1.getOpcode();
+ unsigned Value, SH = 0;
+ TargetMask = ~TargetMask;
+ InsertMask = ~InsertMask;
-/// SelectAddrImm - Returns true if the address N can be represented by
-/// a base register plus a signed 16-bit displacement [r+imm].
-bool PPCDAGToDAGISel::SelectAddrImm(SDOperand N, SDOperand &Disp,
- SDOperand &Base) {
- // If this can be more profitably realized as r+r, fail.
- if (SelectAddrIdx(N, Disp, Base))
- return false;
-
- if (N.getOpcode() == ISD::ADD) {
- unsigned imm = 0;
- if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm)) {
- Disp = getI32Imm(imm & 0xFFFF);
- if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
- Base = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
- } else {
- Base = N.getOperand(0);
+ // If the LHS has a foldable shift and the RHS does not, then swap it to the
+ // RHS so that we can fold the shift into the insert.
+ if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
+ if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
+ Op0.getOperand(0).getOpcode() == ISD::SRL) {
+ if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
+ Op1.getOperand(0).getOpcode() != ISD::SRL) {
+ std::swap(Op0, Op1);
+ std::swap(Op0Opc, Op1Opc);
+ std::swap(TargetMask, InsertMask);
+ }
}
- return true; // [r+i]
- } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
- // Match LOAD (ADD (X, Lo(G))).
- assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
- && "Cannot handle constant offsets yet!");
- Disp = N.getOperand(1).getOperand(0); // The global address.
- assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
- Disp.getOpcode() == ISD::TargetConstantPool);
- Base = N.getOperand(0);
- return true; // [&g+r]
- }
- } else if (N.getOpcode() == ISD::OR) {
- unsigned imm = 0;
- if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm)) {
- // If this is an or of disjoint bitfields, we can codegen this as an add
- // (for better address arithmetic) if the LHS and RHS of the OR are
- // provably disjoint.
- uint64_t LHSKnownZero, LHSKnownOne;
- PPCLowering.ComputeMaskedBits(N.getOperand(0), ~0U,
- LHSKnownZero, LHSKnownOne);
- if ((LHSKnownZero|~imm) == ~0U) {
- // If all of the bits are known zero on the LHS or RHS, the add won't
- // carry.
- Base = N.getOperand(0);
- Disp = getI32Imm(imm & 0xFFFF);
- return true;
+ } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
+ if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
+ Op1.getOperand(0).getOpcode() != ISD::SRL) {
+ std::swap(Op0, Op1);
+ std::swap(Op0Opc, Op1Opc);
+ std::swap(TargetMask, InsertMask);
}
}
- } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
- // Loading from a constant address.
- int Addr = (int)CN->getValue();
- // If this address fits entirely in a 16-bit sext immediate field, codegen
- // this as "d, 0"
- if (Addr == (short)Addr) {
- Disp = getI32Imm(Addr);
- Base = CurDAG->getRegister(PPC::R0, MVT::i32);
- return true;
- }
-
- // Otherwise, break this down into an LIS + disp.
- Disp = getI32Imm((short)Addr);
- Base = CurDAG->getConstant(Addr - (signed short)Addr, MVT::i32);
- return true;
- }
-
- Disp = getI32Imm(0);
- if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
- Base = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
- else
- Base = N;
- return true; // [r+0]
-}
-
-/// SelectAddrIdx - Given the specified addressed, check to see if it can be
-/// represented as an indexed [r+r] operation. Returns false if it can
-/// be represented by [r+imm], which are preferred.
-bool PPCDAGToDAGISel::SelectAddrIdx(SDOperand N, SDOperand &Base,
- SDOperand &Index) {
- unsigned imm = 0;
- if (N.getOpcode() == ISD::ADD) {
- if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm))
- return false; // r+i
- if (N.getOperand(1).getOpcode() == PPCISD::Lo)
- return false; // r+i
-
- Base = N.getOperand(0);
- Index = N.getOperand(1);
- return true;
- } else if (N.getOpcode() == ISD::OR) {
- if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm))
- return false; // r+i can fold it if we can.
-
- // If this is an or of disjoint bitfields, we can codegen this as an add
- // (for better address arithmetic) if the LHS and RHS of the OR are provably
- // disjoint.
- uint64_t LHSKnownZero, LHSKnownOne;
- uint64_t RHSKnownZero, RHSKnownOne;
- PPCLowering.ComputeMaskedBits(N.getOperand(0), ~0U,
- LHSKnownZero, LHSKnownOne);
-
- if (LHSKnownZero) {
- PPCLowering.ComputeMaskedBits(N.getOperand(1), ~0U,
- RHSKnownZero, RHSKnownOne);
- // If all of the bits are known zero on the LHS or RHS, the add won't
- // carry.
- if ((LHSKnownZero | RHSKnownZero) == ~0U) {
- Base = N.getOperand(0);
- Index = N.getOperand(1);
- return true;
- }
- }
- }
-
- return false;
-}
+ unsigned MB, ME;
+ if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) {
+ SDOperand Tmp1, Tmp2, Tmp3;
+ bool DisjointMask = (TargetMask ^ InsertMask) == 0xFFFFFFFF;
-/// SelectAddrIdxOnly - Given the specified addressed, force it to be
-/// represented as an indexed [r+r] operation.
-bool PPCDAGToDAGISel::SelectAddrIdxOnly(SDOperand N, SDOperand &Base,
- SDOperand &Index) {
- // Check to see if we can easily represent this as an [r+r] address. This
- // will fail if it thinks that the address is more profitably represented as
- // reg+imm, e.g. where imm = 0.
- if (SelectAddrIdx(N, Base, Index))
- return true;
-
- // If the operand is an addition, always emit this as [r+r], since this is
- // better (for code size, and execution, as the memop does the add for free)
- // than emitting an explicit add.
- if (N.getOpcode() == ISD::ADD) {
- Base = N.getOperand(0);
- Index = N.getOperand(1);
- return true;
- }
-
- // Otherwise, do it the hard way, using R0 as the base register.
- Base = CurDAG->getRegister(PPC::R0, MVT::i32);
- Index = N;
- return true;
-}
-
-/// SelectAddrImmShift - Returns true if the address N can be represented by
-/// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
-/// for use by STD and friends.
-bool PPCDAGToDAGISel::SelectAddrImmShift(SDOperand N, SDOperand &Disp,
- SDOperand &Base) {
- // If this can be more profitably realized as r+r, fail.
- if (SelectAddrIdx(N, Disp, Base))
- return false;
-
- if (N.getOpcode() == ISD::ADD) {
- unsigned imm = 0;
- if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm) &&
- (imm & 3) == 0) {
- Disp = getI32Imm((imm & 0xFFFF) >> 2);
- if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
- Base = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
- } else {
- Base = N.getOperand(0);
- }
- return true; // [r+i]
- } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
- // Match LOAD (ADD (X, Lo(G))).
- assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
- && "Cannot handle constant offsets yet!");
- Disp = N.getOperand(1).getOperand(0); // The global address.
- assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
- Disp.getOpcode() == ISD::TargetConstantPool);
- Base = N.getOperand(0);
- return true; // [&g+r]
- }
- } else if (N.getOpcode() == ISD::OR) {
- unsigned imm = 0;
- if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm) &&
- (imm & 3) == 0) {
- // If this is an or of disjoint bitfields, we can codegen this as an add
- // (for better address arithmetic) if the LHS and RHS of the OR are
- // provably disjoint.
- uint64_t LHSKnownZero, LHSKnownOne;
- PPCLowering.ComputeMaskedBits(N.getOperand(0), ~0U,
- LHSKnownZero, LHSKnownOne);
- if ((LHSKnownZero|~imm) == ~0U) {
- // If all of the bits are known zero on the LHS or RHS, the add won't
- // carry.
- Base = N.getOperand(0);
- Disp = getI32Imm((imm & 0xFFFF) >> 2);
- return true;
+ if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
+ isInt32Immediate(Op1.getOperand(1), Value)) {
+ Op1 = Op1.getOperand(0);
+ SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
}
- }
- } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
- // Loading from a constant address.
- int Addr = (int)CN->getValue();
- if ((Addr & 3) == 0) {
- // If this address fits entirely in a 16-bit sext immediate field, codegen
- // this as "d, 0"
- if (Addr == (short)Addr) {
- Disp = getI32Imm(Addr >> 2);
- Base = CurDAG->getRegister(PPC::R0, MVT::i32);
- return true;
+ if (Op1Opc == ISD::AND) {
+ unsigned SHOpc = Op1.getOperand(0).getOpcode();
+ if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) &&
+ isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
+ Op1 = Op1.getOperand(0).getOperand(0);
+ SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
+ } else {
+ Op1 = Op1.getOperand(0);
+ }
}
- // Otherwise, break this down into an LIS + disp.
- Disp = getI32Imm((short)Addr >> 2);
- Base = CurDAG->getConstant(Addr - (signed short)Addr, MVT::i32);
- return true;
+ Tmp3 = (Op0Opc == ISD::AND && DisjointMask) ? Op0.getOperand(0) : Op0;
+ AddToISelQueue(Tmp3);
+ AddToISelQueue(Op1);
+ SH &= 31;
+ SDOperand Ops[] = { Tmp3, Op1, getI32Imm(SH), getI32Imm(MB),
+ getI32Imm(ME) };
+ return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5);
}
}
-
- Disp = getI32Imm(0);
- if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
- Base = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
- else
- Base = N;
- return true; // [r+0]
+ return 0;
}
-
/// SelectCC - Select a comparison of the specified values with the specified
/// condition code, returning the CR# of the expression.
SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
ISD::CondCode CC) {
// Always select the LHS.
- Select(LHS, LHS);
-
- // Use U to determine whether the SETCC immediate range is signed or not.
- if (MVT::isInteger(LHS.getValueType())) {
- bool U = ISD::isUnsignedIntSetCC(CC);
+ AddToISelQueue(LHS);
+ unsigned Opc;
+
+ if (LHS.getValueType() == MVT::i32) {
unsigned Imm;
- if (isIntImmediate(RHS, Imm) &&
- ((U && isUInt16(Imm)) || (!U && isInt16(Imm))))
- return SDOperand(CurDAG->getTargetNode(U ? PPC::CMPLWI : PPC::CMPWI,
- MVT::i32, LHS, getI32Imm(Imm & 0xFFFF)), 0);
- Select(RHS, RHS);
- return SDOperand(CurDAG->getTargetNode(U ? PPC::CMPLW : PPC::CMPW, MVT::i32,
- LHS, RHS), 0);
+ if (CC == ISD::SETEQ || CC == ISD::SETNE) {
+ if (isInt32Immediate(RHS, Imm)) {
+ // SETEQ/SETNE comparison with 16-bit immediate, fold it.
+ if (isUInt16(Imm))
+ return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS,
+ getI32Imm(Imm & 0xFFFF)), 0);
+ // If this is a 16-bit signed immediate, fold it.
+ if (isInt16((int)Imm))
+ return SDOperand(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS,
+ getI32Imm(Imm & 0xFFFF)), 0);
+
+ // For non-equality comparisons, the default code would materialize the
+ // constant, then compare against it, like this:
+ // lis r2, 4660
+ // ori r2, r2, 22136
+ // cmpw cr0, r3, r2
+ // Since we are just comparing for equality, we can emit this instead:
+ // xoris r0,r3,0x1234
+ // cmplwi cr0,r0,0x5678
+ // beq cr0,L6
+ SDOperand Xor(CurDAG->getTargetNode(PPC::XORIS, MVT::i32, LHS,
+ getI32Imm(Imm >> 16)), 0);
+ return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, Xor,
+ getI32Imm(Imm & 0xFFFF)), 0);
+ }
+ Opc = PPC::CMPLW;
+ } else if (ISD::isUnsignedIntSetCC(CC)) {
+ if (isInt32Immediate(RHS, Imm) && isUInt16(Imm))
+ return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS,
+ getI32Imm(Imm & 0xFFFF)), 0);
+ Opc = PPC::CMPLW;
+ } else {
+ short SImm;
+ if (isIntS16Immediate(RHS, SImm))
+ return SDOperand(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS,
+ getI32Imm((int)SImm & 0xFFFF)),
+ 0);
+ Opc = PPC::CMPW;
+ }
+ } else if (LHS.getValueType() == MVT::i64) {
+ uint64_t Imm;
+ if (CC == ISD::SETEQ || CC == ISD::SETNE) {
+ if (isInt64Immediate(RHS.Val, Imm)) {
+ // SETEQ/SETNE comparison with 16-bit immediate, fold it.
+ if (isUInt16(Imm))
+ return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS,
+ getI32Imm(Imm & 0xFFFF)), 0);
+ // If this is a 16-bit signed immediate, fold it.
+ if (isInt16(Imm))
+ return SDOperand(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS,
+ getI32Imm(Imm & 0xFFFF)), 0);
+
+ // For non-equality comparisons, the default code would materialize the
+ // constant, then compare against it, like this:
+ // lis r2, 4660
+ // ori r2, r2, 22136
+ // cmpd cr0, r3, r2
+ // Since we are just comparing for equality, we can emit this instead:
+ // xoris r0,r3,0x1234
+ // cmpldi cr0,r0,0x5678
+ // beq cr0,L6
+ if (isUInt32(Imm)) {
+ SDOperand Xor(CurDAG->getTargetNode(PPC::XORIS8, MVT::i64, LHS,
+ getI64Imm(Imm >> 16)), 0);
+ return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, Xor,
+ getI64Imm(Imm & 0xFFFF)), 0);
+ }
+ }
+ Opc = PPC::CMPLD;
+ } else if (ISD::isUnsignedIntSetCC(CC)) {
+ if (isInt64Immediate(RHS.Val, Imm) && isUInt16(Imm))
+ return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS,
+ getI64Imm(Imm & 0xFFFF)), 0);
+ Opc = PPC::CMPLD;
+ } else {
+ short SImm;
+ if (isIntS16Immediate(RHS, SImm))
+ return SDOperand(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS,
+ getI64Imm(SImm & 0xFFFF)),
+ 0);
+ Opc = PPC::CMPD;
+ }
} else if (LHS.getValueType() == MVT::f32) {
- Select(RHS, RHS);
- return SDOperand(CurDAG->getTargetNode(PPC::FCMPUS, MVT::i32, LHS, RHS), 0);
+ Opc = PPC::FCMPUS;
} else {
- Select(RHS, RHS);
- return SDOperand(CurDAG->getTargetNode(PPC::FCMPUD, MVT::i32, LHS, RHS), 0);
+ assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
+ Opc = PPC::FCMPUD;
}
+ AddToISelQueue(RHS);
+ return SDOperand(CurDAG->getTargetNode(Opc, MVT::i32, LHS, RHS), 0);
}
-/// getBCCForSetCC - Returns the PowerPC condition branch mnemonic corresponding
-/// to Condition.
-static unsigned getBCCForSetCC(ISD::CondCode CC) {
+static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
switch (CC) {
default: assert(0 && "Unknown condition!"); abort();
case ISD::SETOEQ: // FIXME: This is incorrect see PR642.
- case ISD::SETEQ: return PPC::BEQ;
+ case ISD::SETUEQ:
+ case ISD::SETEQ: return PPC::PRED_EQ;
case ISD::SETONE: // FIXME: This is incorrect see PR642.
- case ISD::SETNE: return PPC::BNE;
+ case ISD::SETUNE:
+ case ISD::SETNE: return PPC::PRED_NE;
case ISD::SETOLT: // FIXME: This is incorrect see PR642.
case ISD::SETULT:
- case ISD::SETLT: return PPC::BLT;
+ case ISD::SETLT: return PPC::PRED_LT;
case ISD::SETOLE: // FIXME: This is incorrect see PR642.
case ISD::SETULE:
- case ISD::SETLE: return PPC::BLE;
+ case ISD::SETLE: return PPC::PRED_LE;
case ISD::SETOGT: // FIXME: This is incorrect see PR642.
case ISD::SETUGT:
- case ISD::SETGT: return PPC::BGT;
+ case ISD::SETGT: return PPC::PRED_GT;
case ISD::SETOGE: // FIXME: This is incorrect see PR642.
case ISD::SETUGE:
- case ISD::SETGE: return PPC::BGE;
+ case ISD::SETGE: return PPC::PRED_GE;
- case ISD::SETO: return PPC::BUN;
- case ISD::SETUO: return PPC::BNU;
+ case ISD::SETO: return PPC::PRED_NU;
+ case ISD::SETUO: return PPC::PRED_UN;
}
- return 0;
}
/// getCRIdxForSetCC - Return the index of the condition register field
case ISD::SETULE:
case ISD::SETLE: Inv = true; return 1;
case ISD::SETOEQ: // FIXME: This is incorrect see PR642.
+ case ISD::SETUEQ:
case ISD::SETEQ: Inv = false; return 2;
case ISD::SETONE: // FIXME: This is incorrect see PR642.
+ case ISD::SETUNE:
case ISD::SETNE: Inv = true; return 2;
case ISD::SETO: Inv = true; return 3;
case ISD::SETUO: Inv = false; return 3;
return 0;
}
-SDOperand PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
+SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
SDNode *N = Op.Val;
unsigned Imm;
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
- if (isIntImmediate(N->getOperand(1), Imm)) {
+ if (isInt32Immediate(N->getOperand(1), Imm)) {
// We can codegen setcc op, imm very efficiently compared to a brcond.
// Check for those cases here.
// setcc op, 0
if (Imm == 0) {
- SDOperand Op;
- Select(Op, N->getOperand(0));
+ SDOperand Op = N->getOperand(0);
+ AddToISelQueue(Op);
switch (CC) {
default: break;
- case ISD::SETEQ:
+ case ISD::SETEQ: {
Op = SDOperand(CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op), 0);
- return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(27),
- getI32Imm(5), getI32Imm(31));
+ SDOperand Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
+ return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
+ }
case ISD::SETNE: {
SDOperand AD =
SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
AD.getValue(1));
}
- case ISD::SETLT:
- return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
- getI32Imm(31), getI32Imm(31));
+ case ISD::SETLT: {
+ SDOperand Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
+ return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
+ }
case ISD::SETGT: {
SDOperand T =
SDOperand(CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op), 0);
T = SDOperand(CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op), 0);
- return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, T, getI32Imm(1),
- getI32Imm(31), getI32Imm(31));
+ SDOperand Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
+ return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
}
} else if (Imm == ~0U) { // setcc op, -1
- SDOperand Op;
- Select(Op, N->getOperand(0));
+ SDOperand Op = N->getOperand(0);
+ AddToISelQueue(Op);
switch (CC) {
default: break;
case ISD::SETEQ:
Op = SDOperand(CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op), 0);
SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
Op, getI32Imm(~0U));
- return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDOperand(AD, 0), Op,
- SDOperand(AD, 1));
+ return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDOperand(AD, 0),
+ Op, SDOperand(AD, 1));
}
case ISD::SETLT: {
SDOperand AD = SDOperand(CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op,
getI32Imm(1)), 0);
SDOperand AN = SDOperand(CurDAG->getTargetNode(PPC::AND, MVT::i32, AD,
Op), 0);
- return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, AN, getI32Imm(1),
- getI32Imm(31), getI32Imm(31));
+ SDOperand Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
+ return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
+ }
+ case ISD::SETGT: {
+ SDOperand Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
+ Op = SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
+ return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
+ getI32Imm(1));
}
- case ISD::SETGT:
- Op = SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Op,
- getI32Imm(1), getI32Imm(31),
- getI32Imm(31)), 0);
- return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1));
}
}
}
CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), CR7Reg, CCReg,
InFlag).getValue(1);
- if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
+ if (PPCSubTarget.isGigaProcessor())
IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg,
CCReg), 0);
else
IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg), 0);
+ SDOperand Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
+ getI32Imm(31), getI32Imm(31) };
if (!Inv) {
- return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, IntCR,
- getI32Imm((32-(3-Idx)) & 31),
- getI32Imm(31), getI32Imm(31));
+ return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
} else {
SDOperand Tmp =
- SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, IntCR,
- getI32Imm((32-(3-Idx)) & 31),
- getI32Imm(31),getI32Imm(31)), 0);
+ SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
}
}
-/// isCallCompatibleAddress - Return true if the specified 32-bit value is
-/// representable in the immediate field of a Bx instruction.
-static bool isCallCompatibleAddress(ConstantSDNode *C) {
- int Addr = C->getValue();
- if (Addr & 3) return false; // Low 2 bits are implicitly zero.
- return (Addr << 6 >> 6) == Addr; // Top 6 bits have to be sext of immediate.
-}
-SDOperand PPCDAGToDAGISel::SelectCALL(SDOperand Op) {
+// Select - Convert the specified operand from a target-independent to a
+// target-specific node if it hasn't already been changed.
+SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
SDNode *N = Op.Val;
- SDOperand Chain;
- Select(Chain, N->getOperand(0));
-
- unsigned CallOpcode;
- std::vector<SDOperand> CallOperands;
-
- if (GlobalAddressSDNode *GASD =
- dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
- CallOpcode = PPC::BL;
- CallOperands.push_back(N->getOperand(1));
- } else if (ExternalSymbolSDNode *ESSDN =
- dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) {
- CallOpcode = PPC::BL;
- CallOperands.push_back(N->getOperand(1));
- } else if (isa<ConstantSDNode>(N->getOperand(1)) &&
- isCallCompatibleAddress(cast<ConstantSDNode>(N->getOperand(1)))) {
- ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(1));
- CallOpcode = PPC::BLA;
- CallOperands.push_back(getI32Imm((int)C->getValue() >> 2));
- } else {
- // Copy the callee address into the CTR register.
- SDOperand Callee;
- Select(Callee, N->getOperand(1));
- Chain = SDOperand(CurDAG->getTargetNode(PPC::MTCTR, MVT::Other, Callee,
- Chain), 0);
-
- // Copy the callee address into R12 on darwin.
- SDOperand R12 = CurDAG->getRegister(PPC::R12, MVT::i32);
- Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, R12, Callee);
+ if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
+ N->getOpcode() < PPCISD::FIRST_NUMBER)
+ return NULL; // Already selected.
- CallOperands.push_back(R12);
- CallOpcode = PPC::BCTRL;
- }
-
- unsigned GPR_idx = 0, FPR_idx = 0;
- static const unsigned GPR[] = {
- PPC::R3, PPC::R4, PPC::R5, PPC::R6,
- PPC::R7, PPC::R8, PPC::R9, PPC::R10,
- };
- static const unsigned FPR[] = {
- PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
- PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
- };
-
- SDOperand InFlag; // Null incoming flag value.
-
- for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i) {
- unsigned DestReg = 0;
- MVT::ValueType RegTy = N->getOperand(i).getValueType();
- if (RegTy == MVT::i32) {
- assert(GPR_idx < 8 && "Too many int args");
- DestReg = GPR[GPR_idx++];
- } else {
- assert(MVT::isFloatingPoint(N->getOperand(i).getValueType()) &&
- "Unpromoted integer arg?");
- assert(FPR_idx < 13 && "Too many fp args");
- DestReg = FPR[FPR_idx++];
- }
-
- if (N->getOperand(i).getOpcode() != ISD::UNDEF) {
- SDOperand Val;
- Select(Val, N->getOperand(i));
- Chain = CurDAG->getCopyToReg(Chain, DestReg, Val, InFlag);
- InFlag = Chain.getValue(1);
- CallOperands.push_back(CurDAG->getRegister(DestReg, RegTy));
- }
- }
-
- // Finally, once everything is in registers to pass to the call, emit the
- // call itself.
- if (InFlag.Val)
- CallOperands.push_back(InFlag); // Strong dep on register copies.
- else
- CallOperands.push_back(Chain); // Weak dep on whatever occurs before
- Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
- CallOperands), 0);
-
- std::vector<SDOperand> CallResults;
+ switch (N->getOpcode()) {
+ default: break;
- // If the call has results, copy the values out of the ret val registers.
- switch (N->getValueType(0)) {
- default: assert(0 && "Unexpected ret value!");
- case MVT::Other: break;
- case MVT::i32:
- if (N->getValueType(1) == MVT::i32) {
- Chain = CurDAG->getCopyFromReg(Chain, PPC::R4, MVT::i32,
- Chain.getValue(1)).getValue(1);
- CallResults.push_back(Chain.getValue(0));
- Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32,
- Chain.getValue(2)).getValue(1);
- CallResults.push_back(Chain.getValue(0));
+ case ISD::Constant: {
+ if (N->getValueType(0) == MVT::i64) {
+ // Get 64 bit value.
+ int64_t Imm = cast<ConstantSDNode>(N)->getValue();
+ // Assume no remaining bits.
+ unsigned Remainder = 0;
+ // Assume no shift required.
+ unsigned Shift = 0;
+
+ // If it can't be represented as a 32 bit value.
+ if (!isInt32(Imm)) {
+ Shift = CountTrailingZeros_64(Imm);
+ int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
+
+ // If the shifted value fits 32 bits.
+ if (isInt32(ImmSh)) {
+ // Go with the shifted value.
+ Imm = ImmSh;
+ } else {
+ // Still stuck with a 64 bit value.
+ Remainder = Imm;
+ Shift = 32;
+ Imm >>= 32;
+ }
+ }
+
+ // Intermediate operand.
+ SDNode *Result;
+
+ // Handle first 32 bits.
+ unsigned Lo = Imm & 0xFFFF;
+ unsigned Hi = (Imm >> 16) & 0xFFFF;
+
+ // Simple value.
+ if (isInt16(Imm)) {
+ // Just the Lo bits.
+ Result = CurDAG->getTargetNode(PPC::LI8, MVT::i64, getI32Imm(Lo));
+ } else if (Lo) {
+ // Handle the Hi bits.
+ unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
+ Result = CurDAG->getTargetNode(OpC, MVT::i64, getI32Imm(Hi));
+ // And Lo bits.
+ Result = CurDAG->getTargetNode(PPC::ORI8, MVT::i64,
+ SDOperand(Result, 0), getI32Imm(Lo));
} else {
- Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32,
- Chain.getValue(1)).getValue(1);
- CallResults.push_back(Chain.getValue(0));
+ // Just the Hi bits.
+ Result = CurDAG->getTargetNode(PPC::LIS8, MVT::i64, getI32Imm(Hi));
}
- break;
- case MVT::f32:
- case MVT::f64:
- Chain = CurDAG->getCopyFromReg(Chain, PPC::F1, N->getValueType(0),
- Chain.getValue(1)).getValue(1);
- CallResults.push_back(Chain.getValue(0));
- break;
- }
-
- CallResults.push_back(Chain);
- for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
- CodeGenMap[Op.getValue(i)] = CallResults[i];
- return CallResults[Op.ResNo];
-}
+
+ // If no shift, we're done.
+ if (!Shift) return Result;
-// Select - Convert the specified operand from a target-independent to a
-// target-specific node if it hasn't already been changed.
-void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
- SDNode *N = Op.Val;
- if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
- N->getOpcode() < PPCISD::FIRST_NUMBER) {
- Result = Op;
- return; // Already selected.
- }
+ // Shift for next step if the upper 32-bits were not zero.
+ if (Imm) {
+ Result = CurDAG->getTargetNode(PPC::RLDICR, MVT::i64,
+ SDOperand(Result, 0),
+ getI32Imm(Shift), getI32Imm(63 - Shift));
+ }
- // If this has already been converted, use it.
- std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
- if (CGMI != CodeGenMap.end()) {
- Result = CGMI->second;
- return;
+ // Add in the last bits as required.
+ if ((Hi = (Remainder >> 16) & 0xFFFF)) {
+ Result = CurDAG->getTargetNode(PPC::ORIS8, MVT::i64,
+ SDOperand(Result, 0), getI32Imm(Hi));
+ }
+ if ((Lo = Remainder & 0xFFFF)) {
+ Result = CurDAG->getTargetNode(PPC::ORI8, MVT::i64,
+ SDOperand(Result, 0), getI32Imm(Lo));
+ }
+
+ return Result;
+ }
+ break;
}
- switch (N->getOpcode()) {
- default: break;
case ISD::SETCC:
- Result = SelectSETCC(Op);
- return;
- case PPCISD::CALL:
- Result = SelectCALL(Op);
- return;
+ return SelectSETCC(Op);
case PPCISD::GlobalBaseReg:
- Result = getGlobalBaseReg();
- return;
+ return getGlobalBaseReg();
case ISD::FrameIndex: {
int FI = cast<FrameIndexSDNode>(N)->getIndex();
- if (N->hasOneUse()) {
- Result = CurDAG->SelectNodeTo(N, PPC::ADDI, MVT::i32,
- CurDAG->getTargetFrameIndex(FI, MVT::i32),
- getI32Imm(0));
- return;
- }
- Result = CodeGenMap[Op] =
- SDOperand(CurDAG->getTargetNode(PPC::ADDI, MVT::i32,
- CurDAG->getTargetFrameIndex(FI, MVT::i32),
- getI32Imm(0)), 0);
- return;
+ SDOperand TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType());
+ unsigned Opc = Op.getValueType() == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
+ if (N->hasOneUse())
+ return CurDAG->SelectNodeTo(N, Opc, Op.getValueType(), TFI,
+ getSmallIPtrImm(0));
+ return CurDAG->getTargetNode(Opc, Op.getValueType(), TFI,
+ getSmallIPtrImm(0));
+ }
+
+ case PPCISD::MFCR: {
+ SDOperand InFlag = N->getOperand(1);
+ AddToISelQueue(InFlag);
+ // Use MFOCRF if supported.
+ if (PPCSubTarget.isGigaProcessor())
+ return CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32,
+ N->getOperand(0), InFlag);
+ else
+ return CurDAG->getTargetNode(PPC::MFCR, MVT::i32, InFlag);
}
+
case ISD::SDIV: {
// FIXME: since this depends on the setting of the carry flag from the srawi
// we should really be making notes about that for the scheduler.
// srl/add/sra pattern the dag combiner will generate for this as
// sra/addze rather than having to handle sdiv ourselves. oh well.
unsigned Imm;
- if (isIntImmediate(N->getOperand(1), Imm)) {
- SDOperand N0;
- Select(N0, N->getOperand(0));
+ if (isInt32Immediate(N->getOperand(1), Imm)) {
+ SDOperand N0 = N->getOperand(0);
+ AddToISelQueue(N0);
if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
SDNode *Op =
CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
N0, getI32Imm(Log2_32(Imm)));
- Result = CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
- SDOperand(Op, 0), SDOperand(Op, 1));
+ return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
+ SDOperand(Op, 0), SDOperand(Op, 1));
} else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
SDNode *Op =
CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
SDOperand(CurDAG->getTargetNode(PPC::ADDZE, MVT::i32,
SDOperand(Op, 0), SDOperand(Op, 1)),
0);
- Result = CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
+ return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
}
- return;
}
// Other cases are autogenerated.
break;
}
+
+ case ISD::LOAD: {
+ // Handle preincrement loads.
+ LoadSDNode *LD = cast<LoadSDNode>(Op);
+ MVT::ValueType LoadedVT = LD->getLoadedVT();
+
+ // Normal loads are handled by code generated from the .td file.
+ if (LD->getAddressingMode() != ISD::PRE_INC)
+ break;
+
+ SDOperand Offset = LD->getOffset();
+ if (isa<ConstantSDNode>(Offset) ||
+ Offset.getOpcode() == ISD::TargetGlobalAddress) {
+
+ unsigned Opcode;
+ bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
+ if (LD->getValueType(0) != MVT::i64) {
+ // Handle PPC32 integer and normal FP loads.
+ assert(!isSExt || LoadedVT == MVT::i16 && "Invalid sext update load");
+ switch (LoadedVT) {
+ default: assert(0 && "Invalid PPC load type!");
+ case MVT::f64: Opcode = PPC::LFDU; break;
+ case MVT::f32: Opcode = PPC::LFSU; break;
+ case MVT::i32: Opcode = PPC::LWZU; break;
+ case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
+ case MVT::i1:
+ case MVT::i8: Opcode = PPC::LBZU; break;
+ }
+ } else {
+ assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
+ assert(!isSExt || LoadedVT == MVT::i16 && "Invalid sext update load");
+ switch (LoadedVT) {
+ default: assert(0 && "Invalid PPC load type!");
+ case MVT::i64: Opcode = PPC::LDU; break;
+ case MVT::i32: Opcode = PPC::LWZU8; break;
+ case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
+ case MVT::i1:
+ case MVT::i8: Opcode = PPC::LBZU8; break;
+ }
+ }
+
+ SDOperand Chain = LD->getChain();
+ SDOperand Base = LD->getBasePtr();
+ AddToISelQueue(Chain);
+ AddToISelQueue(Base);
+ AddToISelQueue(Offset);
+ SDOperand Ops[] = { Offset, Base, Chain };
+ // FIXME: PPC64
+ return CurDAG->getTargetNode(Opcode, MVT::i32, MVT::i32,
+ MVT::Other, Ops, 3);
+ } else {
+ assert(0 && "R+R preindex loads not supported yet!");
+ }
+ }
+
case ISD::AND: {
- unsigned Imm, Imm2;
+ unsigned Imm, Imm2, SH, MB, ME;
+
// If this is an and of a value rotated between 0 and 31 bits and then and'd
// with a mask, emit rlwinm
- if (isIntImmediate(N->getOperand(1), Imm) && (isShiftedMask_32(Imm) ||
- isShiftedMask_32(~Imm))) {
- SDOperand Val;
- unsigned SH, MB, ME;
- if (isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
- Select(Val, N->getOperand(0).getOperand(0));
- } else if (Imm == 0) {
- // AND X, 0 -> 0, not "rlwinm 32".
- Select(Result, N->getOperand(1));
- return ;
- } else {
- Select(Val, N->getOperand(0));
- isRunOfOnes(Imm, MB, ME);
- SH = 0;
- }
- Result = CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Val,
- getI32Imm(SH), getI32Imm(MB),
- getI32Imm(ME));
- return;
+ if (isInt32Immediate(N->getOperand(1), Imm) &&
+ isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
+ SDOperand Val = N->getOperand(0).getOperand(0);
+ AddToISelQueue(Val);
+ SDOperand Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
+ return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
+ }
+ // If this is just a masked value where the input is not handled above, and
+ // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
+ if (isInt32Immediate(N->getOperand(1), Imm) &&
+ isRunOfOnes(Imm, MB, ME) &&
+ N->getOperand(0).getOpcode() != ISD::ROTL) {
+ SDOperand Val = N->getOperand(0);
+ AddToISelQueue(Val);
+ SDOperand Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
+ return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
+ }
+ // AND X, 0 -> 0, not "rlwinm 32".
+ if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
+ AddToISelQueue(N->getOperand(1));
+ ReplaceUses(SDOperand(N, 0), N->getOperand(1));
+ return NULL;
}
// ISD::OR doesn't get all the bitfield insertion fun.
// (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
- if (isIntImmediate(N->getOperand(1), Imm) &&
+ if (isInt32Immediate(N->getOperand(1), Imm) &&
N->getOperand(0).getOpcode() == ISD::OR &&
- isIntImmediate(N->getOperand(0).getOperand(1), Imm2)) {
+ isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
unsigned MB, ME;
Imm = ~(Imm^Imm2);
if (isRunOfOnes(Imm, MB, ME)) {
- SDOperand Tmp1, Tmp2;
- Select(Tmp1, N->getOperand(0).getOperand(0));
- Select(Tmp2, N->getOperand(0).getOperand(1));
- Result = SDOperand(CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32,
- Tmp1, Tmp2,
- getI32Imm(0), getI32Imm(MB),
- getI32Imm(ME)), 0);
- return;
+ AddToISelQueue(N->getOperand(0).getOperand(0));
+ AddToISelQueue(N->getOperand(0).getOperand(1));
+ SDOperand Ops[] = { N->getOperand(0).getOperand(0),
+ N->getOperand(0).getOperand(1),
+ getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
+ return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5);
}
}
break;
}
case ISD::OR:
- if (SDNode *I = SelectBitfieldInsert(N)) {
- Result = CodeGenMap[Op] = SDOperand(I, 0);
- return;
- }
+ if (N->getValueType(0) == MVT::i32)
+ if (SDNode *I = SelectBitfieldInsert(N))
+ return I;
// Other cases are autogenerated.
break;
unsigned Imm, SH, MB, ME;
if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
isRotateAndMask(N, Imm, true, SH, MB, ME)) {
- SDOperand Val;
- Select(Val, N->getOperand(0).getOperand(0));
- Result = CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
- Val, getI32Imm(SH), getI32Imm(MB),
- getI32Imm(ME));
- return;
+ AddToISelQueue(N->getOperand(0).getOperand(0));
+ SDOperand Ops[] = { N->getOperand(0).getOperand(0),
+ getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
+ return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
// Other cases are autogenerated.
unsigned Imm, SH, MB, ME;
if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
isRotateAndMask(N, Imm, true, SH, MB, ME)) {
- SDOperand Val;
- Select(Val, N->getOperand(0).getOperand(0));
- Result = CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
- Val, getI32Imm(SH & 0x1F), getI32Imm(MB),
- getI32Imm(ME));
- return;
+ AddToISelQueue(N->getOperand(0).getOperand(0));
+ SDOperand Ops[] = { N->getOperand(0).getOperand(0),
+ getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
+ return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
// Other cases are autogenerated.
case ISD::SELECT_CC: {
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
- // handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
+ // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
if (N1C->isNullValue() && N3C->isNullValue() &&
- N2C->getValue() == 1ULL && CC == ISD::SETNE) {
- SDOperand LHS;
- Select(LHS, N->getOperand(0));
+ N2C->getValue() == 1ULL && CC == ISD::SETNE &&
+ // FIXME: Implement this optzn for PPC64.
+ N->getValueType(0) == MVT::i32) {
+ AddToISelQueue(N->getOperand(0));
SDNode *Tmp =
CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
- LHS, getI32Imm(~0U));
- Result = CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
- SDOperand(Tmp, 0), LHS,
- SDOperand(Tmp, 1));
- return;
+ N->getOperand(0), getI32Imm(~0U));
+ return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
+ SDOperand(Tmp, 0), N->getOperand(0),
+ SDOperand(Tmp, 1));
}
SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
- unsigned BROpc = getBCCForSetCC(CC);
+ unsigned BROpc = getPredicateForSetCC(CC);
- bool isFP = MVT::isFloatingPoint(N->getValueType(0));
unsigned SelectCCOp;
- if (MVT::isInteger(N->getValueType(0)))
- SelectCCOp = PPC::SELECT_CC_Int;
+ if (N->getValueType(0) == MVT::i32)
+ SelectCCOp = PPC::SELECT_CC_I4;
+ else if (N->getValueType(0) == MVT::i64)
+ SelectCCOp = PPC::SELECT_CC_I8;
else if (N->getValueType(0) == MVT::f32)
SelectCCOp = PPC::SELECT_CC_F4;
- else
+ else if (N->getValueType(0) == MVT::f64)
SelectCCOp = PPC::SELECT_CC_F8;
- SDOperand N2, N3;
- Select(N2, N->getOperand(2));
- Select(N3, N->getOperand(3));
- Result = CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), CCReg,
- N2, N3, getI32Imm(BROpc));
- return;
+ else
+ SelectCCOp = PPC::SELECT_CC_VRRC;
+
+ AddToISelQueue(N->getOperand(2));
+ AddToISelQueue(N->getOperand(3));
+ SDOperand Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
+ getI32Imm(BROpc) };
+ return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4);
+ }
+ case PPCISD::COND_BRANCH: {
+ AddToISelQueue(N->getOperand(0)); // Op #0 is the Chain.
+ // Op #1 is the PPC::PRED_* number.
+ // Op #2 is the CR#
+ // Op #3 is the Dest MBB
+ AddToISelQueue(N->getOperand(4)); // Op #4 is the Flag.
+ // Prevent PPC::PRED_* from being selected into LI.
+ SDOperand Pred =
+ getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getValue());
+ SDOperand Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
+ N->getOperand(0), N->getOperand(4) };
+ return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5);
}
case ISD::BR_CC: {
- SDOperand Chain;
- Select(Chain, N->getOperand(0));
+ AddToISelQueue(N->getOperand(0));
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
- Result = CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other,
- CondCode, getI32Imm(getBCCForSetCC(CC)),
- N->getOperand(4), Chain);
- return;
+ SDOperand Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode,
+ N->getOperand(4), N->getOperand(0) };
+ return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4);
+ }
+ case ISD::BRIND: {
+ // FIXME: Should custom lower this.
+ SDOperand Chain = N->getOperand(0);
+ SDOperand Target = N->getOperand(1);
+ AddToISelQueue(Chain);
+ AddToISelQueue(Target);
+ unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
+ Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, Target,
+ Chain), 0);
+ return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain);
}
}
- SelectCode(Result, Op);
+ return SelectCode(Op);
}
+
/// createPPCISelDag - This pass converts a legalized DAG into a
/// PowerPC-specific DAG, ready for instruction scheduling.
///
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