Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects

[oota-llvm.git] / lib / Target / PowerPC / PPCISelDAGToDAG.cpp

diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 372d2387ff747884e3660ed2bbb28c49e84caf40..87c698b4b13186c84111685055fc3d9c08f0a3e6 100644 (file)
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -2,8 +2,8 @@
 //
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by Chris Lattner and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
@@ -20,7 +20,7 @@
 #include "PPCHazardRecognizers.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/SSARegMap.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/SelectionDAGISel.h"
 #include "llvm/Target/TargetOptions.h"
@@ -224,11 +224,10 @@ void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) {
   // In this case, there will be virtual registers of vector type type created
   // by the scheduler.  Detect them now.
   MachineFunction &Fn = MachineFunction::get(&F);
-  SSARegMap *RegMap = Fn.getSSARegMap();
   bool HasVectorVReg = false;
   for (unsigned i = MRegisterInfo::FirstVirtualRegister, 
-       e = RegMap->getLastVirtReg()+1; i != e; ++i)
-    if (RegMap->getRegClass(i) == &PPC::VRRCRegClass) {
+       e = RegInfo->getLastVirtReg()+1; i != e; ++i)
+    if (RegInfo->getRegClass(i) == &PPC::VRRCRegClass) {
       HasVectorVReg = true;
       break;
     }
@@ -246,8 +245,8 @@ void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) {
 
   // Create two vregs - one to hold the VRSAVE register that is live-in to the
   // function and one for the value after having bits or'd into it.
-  unsigned InVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
-  unsigned UpdatedVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
+  unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
+  unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
   
   const TargetInstrInfo &TII = *TM.getInstrInfo();
   MachineBasicBlock &EntryBB = *Fn.begin();
@@ -257,7 +256,8 @@ void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) {
   // MTVRSAVE UpdatedVRSAVE
   MachineBasicBlock::iterator IP = EntryBB.begin();  // Insert Point
   BuildMI(EntryBB, IP, TII.get(PPC::MFVRSAVE), InVRSAVE);
-  BuildMI(EntryBB, IP, TII.get(PPC::UPDATE_VRSAVE), UpdatedVRSAVE).addReg(InVRSAVE);
+  BuildMI(EntryBB, IP, TII.get(PPC::UPDATE_VRSAVE),
+          UpdatedVRSAVE).addReg(InVRSAVE);
   BuildMI(EntryBB, IP, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
   
   // Find all return blocks, outputting a restore in each epilog.
@@ -268,7 +268,7 @@ void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) {
       // Skip over all terminator instructions, which are part of the return
       // sequence.
       MachineBasicBlock::iterator I2 = IP;
-      while (I2 != BB->begin() && TII.isTerminatorInstr((--I2)->getOpcode()))
+      while (I2 != BB->begin() && (--I2)->getDesc()->isTerminator())
         IP = I2;
       
       // Emit: MTVRSAVE InVRSave
@@ -287,14 +287,13 @@ SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
     // Insert the set of GlobalBaseReg into the first MBB of the function
     MachineBasicBlock &FirstMBB = BB->getParent()->front();
     MachineBasicBlock::iterator MBBI = FirstMBB.begin();
-    SSARegMap *RegMap = BB->getParent()->getSSARegMap();
 
     if (PPCLowering.getPointerTy() == MVT::i32) {
-      GlobalBaseReg = RegMap->createVirtualRegister(PPC::GPRCRegisterClass);
+      GlobalBaseReg = RegInfo->createVirtualRegister(PPC::GPRCRegisterClass);
       BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR), PPC::LR);
       BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR), GlobalBaseReg);
     } else {
-      GlobalBaseReg = RegMap->createVirtualRegister(PPC::G8RCRegisterClass);
+      GlobalBaseReg = RegInfo->createVirtualRegister(PPC::G8RCRegisterClass);
       BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR8), PPC::LR8);
       BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR8), GlobalBaseReg);
     }