-//===-- PPCCodeEmitter.cpp - JIT Code Emitter for PowerPC32 -------*- C++ -*-=//
+//===-- PPCCodeEmitter.cpp - JIT Code Emitter for PowerPC -----------------===//
//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines the PowerPC 32-bit CodeEmitter and associated machinery to
-// JIT-compile bytecode to native PowerPC.
+// JIT-compile bitcode to native PowerPC.
//
//===----------------------------------------------------------------------===//
#include "PPC.h"
#include "llvm/Module.h"
#include "llvm/PassManager.h"
-#include "llvm/CodeGen/MachineCodeEmitter.h"
+#include "llvm/CodeGen/JITCodeEmitter.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/Passes.h"
-#include "llvm/Support/Debug.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetOptions.h"
-#include <iostream>
using namespace llvm;
namespace {
class PPCCodeEmitter : public MachineFunctionPass {
TargetMachine &TM;
- MachineCodeEmitter &MCE;
+ JITCodeEmitter &MCE;
+ MachineModuleInfo *MMI;
+
+ void getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.addRequired<MachineModuleInfo>();
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
+
+ static char ID;
+
+ /// MovePCtoLROffset - When/if we see a MovePCtoLR instruction, we record
+ /// its address in the function into this pointer.
+ void *MovePCtoLROffset;
+ public:
+
+ PPCCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
+ : MachineFunctionPass(ID), TM(tm), MCE(mce) {}
- // Tracks which instruction references which BasicBlock
- std::vector<std::pair<MachineBasicBlock*, unsigned*> > BBRefs;
- // Tracks where each BasicBlock starts
- std::map<MachineBasicBlock*, long> BBLocations;
+ /// getBinaryCodeForInstr - This function, generated by the
+ /// CodeEmitterGenerator using TableGen, produces the binary encoding for
+ /// machine instructions.
+ uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
+
+ MachineRelocation GetRelocation(const MachineOperand &MO,
+ unsigned RelocID) const;
+
/// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr
- ///
- int getMachineOpValue(MachineInstr &MI, MachineOperand &MO);
+ unsigned getMachineOpValue(const MachineInstr &MI,
+ const MachineOperand &MO) const;
- public:
- PPCCodeEmitter(TargetMachine &T, MachineCodeEmitter &M)
- : TM(T), MCE(M) {}
+ unsigned get_crbitm_encoding(const MachineInstr &MI, unsigned OpNo) const;
+ unsigned getDirectBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
+ unsigned getCondBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
+
+ unsigned getHA16Encoding(const MachineInstr &MI, unsigned OpNo) const;
+ unsigned getLO16Encoding(const MachineInstr &MI, unsigned OpNo) const;
+ unsigned getMemRIEncoding(const MachineInstr &MI, unsigned OpNo) const;
+ unsigned getMemRIXEncoding(const MachineInstr &MI, unsigned OpNo) const;
const char *getPassName() const { return "PowerPC Machine Code Emitter"; }
/// emitBasicBlock - emits the given MachineBasicBlock to memory
///
void emitBasicBlock(MachineBasicBlock &MBB);
-
- /// emitWord - write a 32-bit word to memory at the current PC
- ///
- void emitWord(unsigned w) { MCE.emitWord(w); }
-
- /// getValueBit - return the particular bit of Val
- ///
- unsigned getValueBit(int64_t Val, unsigned bit) { return (Val >> bit) & 1; }
-
- /// getBinaryCodeForInstr - This function, generated by the
- /// CodeEmitterGenerator using TableGen, produces the binary encoding for
- /// machine instructions.
- ///
- unsigned getBinaryCodeForInstr(MachineInstr &MI);
};
}
-/// addPassesToEmitMachineCode - Add passes to the specified pass manager to get
-/// machine code emitted. This uses a MachineCodeEmitter object to handle
-/// actually outputting the machine code and resolving things like the address
-/// of functions. This method should returns true if machine code emission is
-/// not supported.
-///
-bool PPCTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
- MachineCodeEmitter &MCE) {
- // Machine code emitter pass for PowerPC
- PM.add(new PPCCodeEmitter(*this, MCE));
- // Delete machine code for this function after emitting it
- PM.add(createMachineCodeDeleter());
- return false;
+char PPCCodeEmitter::ID = 0;
+
+/// createPPCCodeEmitterPass - Return a pass that emits the collected PPC code
+/// to the specified MCE object.
+FunctionPass *llvm::createPPCJITCodeEmitterPass(PPCTargetMachine &TM,
+ JITCodeEmitter &JCE) {
+ return new PPCCodeEmitter(TM, JCE);
}
bool PPCCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
MF.getTarget().getRelocationModel() != Reloc::Static) &&
"JIT relocation model must be set to static or default!");
- MCE.startFunction(MF);
- MCE.emitConstantPool(MF.getConstantPool());
- for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
- emitBasicBlock(*BB);
- MCE.finishFunction(MF);
-
- // Resolve branches to BasicBlocks for the entire function
- for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) {
- intptr_t Location = BBLocations[BBRefs[i].first];
- unsigned *Ref = BBRefs[i].second;
- DEBUG(std::cerr << "Fixup @ " << (void*)Ref << " to " << (void*)Location
- << "\n");
- unsigned Instr = *Ref;
- intptr_t BranchTargetDisp = (Location - (intptr_t)Ref) >> 2;
- switch (Instr >> 26) {
- default: assert(0 && "Unknown branch user!");
- case 18: // This is B or BL
- *Ref |= (BranchTargetDisp & ((1 << 24)-1)) << 2;
- break;
- case 16: // This is BLT,BLE,BEQ,BGE,BGT,BNE, or other bcx instruction
- *Ref |= (BranchTargetDisp & ((1 << 14)-1)) << 2;
- break;
- }
- }
- BBRefs.clear();
- BBLocations.clear();
+ MMI = &getAnalysis<MachineModuleInfo>();
+ MCE.setModuleInfo(MMI);
+ do {
+ MovePCtoLROffset = 0;
+ MCE.startFunction(MF);
+ for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
+ emitBasicBlock(*BB);
+ } while (MCE.finishFunction(MF));
return false;
}
void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
- BBLocations[&MBB] = MCE.getCurrentPCValue();
+ MCE.StartMachineBasicBlock(&MBB);
+
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
- MachineInstr &MI = *I;
- unsigned Opcode = MI.getOpcode();
+ const MachineInstr &MI = *I;
+ MCE.processDebugLoc(MI.getDebugLoc(), true);
switch (MI.getOpcode()) {
default:
- emitWord(getBinaryCodeForInstr(*I));
+ MCE.emitWordBE(getBinaryCodeForInstr(MI));
+ break;
+ case TargetOpcode::PROLOG_LABEL:
+ case TargetOpcode::EH_LABEL:
+ MCE.emitLabel(MI.getOperand(0).getMCSymbol());
break;
- case PPC::IMPLICIT_DEF_GPR:
- case PPC::IMPLICIT_DEF_F8:
- case PPC::IMPLICIT_DEF_F4:
- case PPC::IMPLICIT_DEF_VRRC:
+ case TargetOpcode::IMPLICIT_DEF:
+ case TargetOpcode::KILL:
break; // pseudo opcode, no side effects
case PPC::MovePCtoLR:
- assert(0 && "CodeEmitter does not support MovePCtoLR instruction");
+ case PPC::MovePCtoLR8:
+ assert(TM.getRelocationModel() == Reloc::PIC_);
+ MovePCtoLROffset = (void*)MCE.getCurrentPCValue();
+ MCE.emitWordBE(0x48000005); // bl 1
break;
}
+ MCE.processDebugLoc(MI.getDebugLoc(), false);
}
}
-static unsigned enumRegToMachineReg(unsigned enumReg) {
- switch (enumReg) {
- case PPC::R0 : case PPC::F0 : case PPC::V0 : case PPC::CR0: return 0;
- case PPC::R1 : case PPC::F1 : case PPC::V1 : case PPC::CR1: return 1;
- case PPC::R2 : case PPC::F2 : case PPC::V2 : case PPC::CR2: return 2;
- case PPC::R3 : case PPC::F3 : case PPC::V3 : case PPC::CR3: return 3;
- case PPC::R4 : case PPC::F4 : case PPC::V4 : case PPC::CR4: return 4;
- case PPC::R5 : case PPC::F5 : case PPC::V5 : case PPC::CR5: return 5;
- case PPC::R6 : case PPC::F6 : case PPC::V6 : case PPC::CR6: return 6;
- case PPC::R7 : case PPC::F7 : case PPC::V7 : case PPC::CR7: return 7;
- case PPC::R8 : case PPC::F8 : case PPC::V8 : return 8;
- case PPC::R9 : case PPC::F9 : case PPC::V9 : return 9;
- case PPC::R10: case PPC::F10: case PPC::V10: return 10;
- case PPC::R11: case PPC::F11: case PPC::V11: return 11;
- case PPC::R12: case PPC::F12: case PPC::V12: return 12;
- case PPC::R13: case PPC::F13: case PPC::V13: return 13;
- case PPC::R14: case PPC::F14: case PPC::V14: return 14;
- case PPC::R15: case PPC::F15: case PPC::V15: return 15;
- case PPC::R16: case PPC::F16: case PPC::V16: return 16;
- case PPC::R17: case PPC::F17: case PPC::V17: return 17;
- case PPC::R18: case PPC::F18: case PPC::V18: return 18;
- case PPC::R19: case PPC::F19: case PPC::V19: return 19;
- case PPC::R20: case PPC::F20: case PPC::V20: return 20;
- case PPC::R21: case PPC::F21: case PPC::V21: return 21;
- case PPC::R22: case PPC::F22: case PPC::V22: return 22;
- case PPC::R23: case PPC::F23: case PPC::V23: return 23;
- case PPC::R24: case PPC::F24: case PPC::V24: return 24;
- case PPC::R25: case PPC::F25: case PPC::V25: return 25;
- case PPC::R26: case PPC::F26: case PPC::V26: return 26;
- case PPC::R27: case PPC::F27: case PPC::V27: return 27;
- case PPC::R28: case PPC::F28: case PPC::V28: return 28;
- case PPC::R29: case PPC::F29: case PPC::V29: return 29;
- case PPC::R30: case PPC::F30: case PPC::V30: return 30;
- case PPC::R31: case PPC::F31: case PPC::V31: return 31;
- default:
- std::cerr << "Unhandled reg in enumRegToRealReg!\n";
- abort();
+unsigned PPCCodeEmitter::get_crbitm_encoding(const MachineInstr &MI,
+ unsigned OpNo) const {
+ const MachineOperand &MO = MI.getOperand(OpNo);
+ assert((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MTCRF8 ||
+ MI.getOpcode() == PPC::MFOCRF) &&
+ (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
+ return 0x80 >> getPPCRegisterNumbering(MO.getReg());
+}
+
+MachineRelocation PPCCodeEmitter::GetRelocation(const MachineOperand &MO,
+ unsigned RelocID) const {
+ // If in PIC mode, we need to encode the negated address of the
+ // 'movepctolr' into the unrelocated field. After relocation, we'll have
+ // &gv-&movepctolr-4 in the imm field. Once &movepctolr is added to the imm
+ // field, we get &gv. This doesn't happen for branch relocations, which are
+ // always implicitly pc relative.
+ intptr_t Cst = 0;
+ if (TM.getRelocationModel() == Reloc::PIC_) {
+ assert(MovePCtoLROffset && "MovePCtoLR not seen yet?");
+ Cst = -(intptr_t)MovePCtoLROffset - 4;
}
+
+ if (MO.isGlobal())
+ return MachineRelocation::getGV(MCE.getCurrentPCOffset(), RelocID,
+ const_cast<GlobalValue *>(MO.getGlobal()),
+ Cst, isa<Function>(MO.getGlobal()));
+ if (MO.isSymbol())
+ return MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
+ RelocID, MO.getSymbolName(), Cst);
+ if (MO.isCPI())
+ return MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
+ RelocID, MO.getIndex(), Cst);
+
+ if (MO.isMBB())
+ return MachineRelocation::getBB(MCE.getCurrentPCOffset(),
+ RelocID, MO.getMBB());
+
+ assert(MO.isJTI());
+ return MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
+ RelocID, MO.getIndex(), Cst);
}
-int PPCCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
+unsigned PPCCodeEmitter::getDirectBrEncoding(const MachineInstr &MI,
+ unsigned OpNo) const {
+ const MachineOperand &MO = MI.getOperand(OpNo);
+ if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
+
+ MCE.addRelocation(GetRelocation(MO, PPC::reloc_pcrel_bx));
+ return 0;
+}
- int rv = 0; // Return value; defaults to 0 for unhandled cases
- // or things that get fixed up later by the JIT.
- if (MO.isRegister()) {
- rv = enumRegToMachineReg(MO.getReg());
+unsigned PPCCodeEmitter::getCondBrEncoding(const MachineInstr &MI,
+ unsigned OpNo) const {
+ const MachineOperand &MO = MI.getOperand(OpNo);
+ MCE.addRelocation(GetRelocation(MO, PPC::reloc_pcrel_bcx));
+ return 0;
+}
- // Special encoding for MTCRF and MFOCRF, which uses a bit mask for the
- // register, not the register number directly.
- if ((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFOCRF) &&
- (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)) {
- rv = 0x80 >> rv;
- }
- } else if (MO.isImmediate()) {
- rv = MO.getImmedValue();
- } else if (MO.isGlobalAddress() || MO.isExternalSymbol()) {
- bool isExternal = MO.isExternalSymbol() ||
- MO.getGlobal()->hasWeakLinkage() ||
- MO.getGlobal()->hasLinkOnceLinkage() ||
- (MO.getGlobal()->isExternal() &&
- !MO.getGlobal()->hasNotBeenReadFromBytecode());
- unsigned Reloc = 0;
- if (MI.getOpcode() == PPC::BL)
- Reloc = PPC::reloc_pcrel_bx;
- else {
- switch (MI.getOpcode()) {
- default: MI.dump(); assert(0 && "Unknown instruction for relocation!");
- case PPC::LIS:
- if (isExternal)
- Reloc = PPC::reloc_absolute_ptr_high; // Pointer to stub
- else
- Reloc = PPC::reloc_absolute_high; // Pointer to symbol
- break;
- case PPC::LA:
- assert(!isExternal && "Something in the ISEL changed\n");
- Reloc = PPC::reloc_absolute_low;
- break;
- case PPC::LBZ:
- case PPC::LHA:
- case PPC::LHZ:
- case PPC::LWZ:
- case PPC::LFS:
- case PPC::LFD:
- case PPC::STB:
- case PPC::STH:
- case PPC::STW:
- case PPC::STFS:
- case PPC::STFD:
- if (isExternal)
- Reloc = PPC::reloc_absolute_ptr_low;
- else
- Reloc = PPC::reloc_absolute_low;
- break;
- }
- }
- if (MO.isGlobalAddress())
- MCE.addRelocation(MachineRelocation(MCE.getCurrentPCOffset(),
- Reloc, MO.getGlobal(), 0));
- else
- MCE.addRelocation(MachineRelocation(MCE.getCurrentPCOffset(),
- Reloc, MO.getSymbolName(), 0));
- } else if (MO.isMachineBasicBlock()) {
- unsigned* CurrPC = (unsigned*)(intptr_t)MCE.getCurrentPCValue();
- BBRefs.push_back(std::make_pair(MO.getMachineBasicBlock(), CurrPC));
- } else if (MO.isConstantPoolIndex()) {
- unsigned index = MO.getConstantPoolIndex();
- unsigned Opcode = MI.getOpcode();
- rv = MCE.getConstantPoolEntryAddress(index);
- if (Opcode == PPC::LIS || Opcode == PPC::ADDIS) {
- // lis wants hi16(addr)
- if ((short)rv < 0) rv += 1 << 16;
- rv >>= 16;
- } else if (Opcode == PPC::LWZ || Opcode == PPC::LA ||
- Opcode == PPC::LI ||
- Opcode == PPC::LFS || Opcode == PPC::LFD) {
- // These load opcodes want lo16(addr)
- rv &= 0xffff;
- } else {
- assert(0 && "Unknown constant pool using instruction!");
- }
- } else {
- std::cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
- abort();
- }
+unsigned PPCCodeEmitter::getHA16Encoding(const MachineInstr &MI,
+ unsigned OpNo) const {
+ const MachineOperand &MO = MI.getOperand(OpNo);
+ if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
- return rv;
+ MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_high));
+ return 0;
+}
+
+unsigned PPCCodeEmitter::getLO16Encoding(const MachineInstr &MI,
+ unsigned OpNo) const {
+ const MachineOperand &MO = MI.getOperand(OpNo);
+ if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
+
+ MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_low));
+ return 0;
+}
+
+unsigned PPCCodeEmitter::getMemRIEncoding(const MachineInstr &MI,
+ unsigned OpNo) const {
+ // Encode (imm, reg) as a memri, which has the low 16-bits as the
+ // displacement and the next 5 bits as the register #.
+ assert(MI.getOperand(OpNo+1).isReg());
+ unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 16;
+
+ const MachineOperand &MO = MI.getOperand(OpNo);
+ if (MO.isImm())
+ return (getMachineOpValue(MI, MO) & 0xFFFF) | RegBits;
+
+ // Add a fixup for the displacement field.
+ MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_low));
+ return RegBits;
+}
+
+unsigned PPCCodeEmitter::getMemRIXEncoding(const MachineInstr &MI,
+ unsigned OpNo) const {
+ // Encode (imm, reg) as a memrix, which has the low 14-bits as the
+ // displacement and the next 5 bits as the register #.
+ assert(MI.getOperand(OpNo+1).isReg());
+ unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 14;
+
+ const MachineOperand &MO = MI.getOperand(OpNo);
+ if (MO.isImm())
+ return (getMachineOpValue(MI, MO) & 0x3FFF) | RegBits;
+
+ MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_low_ix));
+ return RegBits;
}
-#include "PPCGenCodeEmitter.inc"
+unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI,
+ const MachineOperand &MO) const {
+
+ if (MO.isReg()) {
+ // MTCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
+ // The GPR operand should come through here though.
+ assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MTCRF8 &&
+ MI.getOpcode() != PPC::MFOCRF) ||
+ MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
+ return getPPCRegisterNumbering(MO.getReg());
+ }
+
+ assert(MO.isImm() &&
+ "Relocation required in an instruction that we cannot encode!");
+ return MO.getImm();
+}
+
+#include "PPCGenCodeEmitter.inc"
projects / oota-llvm.git / blobdiff