#include "PowerPC.h"
#include "PowerPCInstrBuilder.h"
#include "PowerPCInstrInfo.h"
+#include "PPC32TargetMachine.h"
#include "llvm/Constants.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Function.h"
#include "llvm/Support/GetElementPtrTypeIterator.h"
#include "llvm/Support/InstVisitor.h"
#include "Support/Debug.h"
+#include "Support/Statistic.h"
#include <vector>
using namespace llvm;
namespace {
+ Statistic<> GEPFolds("ppc-codegen", "Number of GEPs folded");
+
/// TypeClass - Used by the PowerPC backend to group LLVM types by their basic
/// PPC Representation.
///
enum TypeClass {
- cByte, cShort, cInt, cFP, cLong
+ cByte, cShort, cInt, cFP32, cFP64, cLong
};
}
case Type::UIntTyID:
case Type::PointerTyID: return cInt; // Ints and pointers are class #2
- case Type::FloatTyID:
- case Type::DoubleTyID: return cFP; // Floating Point is #3
+ case Type::FloatTyID: return cFP32; // Single float is #3
+ case Type::DoubleTyID: return cFP64; // Double Point is #4
case Type::LongTyID:
- case Type::ULongTyID: return cLong; // Longs are class #4
+ case Type::ULongTyID: return cLong; // Longs are class #5
default:
assert(0 && "Invalid type to getClass!");
return cByte; // not reached
// getClassB - Just like getClass, but treat boolean values as ints.
static inline TypeClass getClassB(const Type *Ty) {
- if (Ty == Type::BoolTy) return cInt;
+ if (Ty == Type::BoolTy) return cByte;
return getClass(Ty);
}
namespace {
struct ISel : public FunctionPass, InstVisitor<ISel> {
- TargetMachine &TM;
+ PPC32TargetMachine &TM;
MachineFunction *F; // The function we are compiling into
MachineBasicBlock *BB; // The current MBB we are compiling
int VarArgsFrameIndex; // FrameIndex for start of varargs area
- int ReturnAddressIndex; // FrameIndex for the return address
-
+
std::map<Value*, unsigned> RegMap; // Mapping between Values and SSA Regs
// External functions used in the Module
- Function *fmodFn, *__moddi3Fn, *__divdi3Fn, *__umoddi3Fn, *__udivdi3Fn,
- *__fixdfdiFn, *__floatdisfFn, *__floatdidfFn, *mallocFn, *freeFn;
+ Function *fmodfFn, *fmodFn, *__cmpdi2Fn, *__moddi3Fn, *__divdi3Fn,
+ *__umoddi3Fn, *__udivdi3Fn, *__fixsfdiFn, *__fixdfdiFn, *__fixunssfdiFn,
+ *__fixunsdfdiFn, *__floatdisfFn, *__floatdidfFn, *mallocFn, *freeFn;
// MBBMap - Mapping between LLVM BB -> Machine BB
std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
// FrameIndex for the alloca.
std::map<AllocaInst*, unsigned> AllocaMap;
- ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
+ // A Reg to hold the base address used for global loads and stores, and a
+ // flag to set whether or not we need to emit it for this function.
+ unsigned GlobalBaseReg;
+ bool GlobalBaseInitialized;
+
+ ISel(TargetMachine &tm) : TM(reinterpret_cast<PPC32TargetMachine&>(tm)),
+ F(0), BB(0) {}
bool doInitialization(Module &M) {
// Add external functions that we may call
+ Type *i = Type::IntTy;
Type *d = Type::DoubleTy;
Type *f = Type::FloatTy;
Type *l = Type::LongTy;
Type *ul = Type::ULongTy;
Type *voidPtr = PointerType::get(Type::SByteTy);
+ // float fmodf(float, float);
+ fmodfFn = M.getOrInsertFunction("fmodf", f, f, f, 0);
// double fmod(double, double);
fmodFn = M.getOrInsertFunction("fmod", d, d, d, 0);
+ // int __cmpdi2(long, long);
+ __cmpdi2Fn = M.getOrInsertFunction("__cmpdi2", i, l, l, 0);
// long __moddi3(long, long);
__moddi3Fn = M.getOrInsertFunction("__moddi3", l, l, l, 0);
// long __divdi3(long, long);
__umoddi3Fn = M.getOrInsertFunction("__umoddi3", ul, ul, ul, 0);
// unsigned long __udivdi3(unsigned long, unsigned long);
__udivdi3Fn = M.getOrInsertFunction("__udivdi3", ul, ul, ul, 0);
+ // long __fixsfdi(float)
+ __fixsfdiFn = M.getOrInsertFunction("__fixsfdi", l, f, 0);
// long __fixdfdi(double)
__fixdfdiFn = M.getOrInsertFunction("__fixdfdi", l, d, 0);
+ // unsigned long __fixunssfdi(float)
+ __fixunssfdiFn = M.getOrInsertFunction("__fixunssfdi", ul, f, 0);
+ // unsigned long __fixunsdfdi(double)
+ __fixunsdfdiFn = M.getOrInsertFunction("__fixunsdfdi", ul, d, 0);
// float __floatdisf(long)
__floatdisfFn = M.getOrInsertFunction("__floatdisf", f, l, 0);
// double __floatdidf(long)
BB = &F->front();
- // Set up a frame object for the return address. This is used by the
- // llvm.returnaddress & llvm.frameaddress intrinisics.
- ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
+ // Make sure we re-emit a set of the global base reg if necessary
+ GlobalBaseInitialized = false;
// Copy incoming arguments off of the stack...
LoadArgumentsToVirtualRegs(Fn);
ValueRecord(unsigned R, const Type *T) : Val(0), Reg(R), Ty(T) {}
ValueRecord(Value *V) : Val(V), Reg(0), Ty(V->getType()) {}
};
+
+ // This struct is for recording the necessary operations to emit the GEP
+ struct CollapsedGepOp {
+ bool isMul;
+ Value *index;
+ ConstantSInt *size;
+ CollapsedGepOp(bool mul, Value *i, ConstantSInt *s) :
+ isMul(mul), index(i), size(s) {}
+ };
+
void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
const std::vector<ValueRecord> &Args, bool isVarArg);
void visitCallInst(CallInst &I);
///
void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
Value *Src, User::op_iterator IdxBegin,
- User::op_iterator IdxEnd, unsigned TargetReg);
+ User::op_iterator IdxEnd, unsigned TargetReg,
+ bool CollapseRemainder, ConstantSInt **Remainder,
+ unsigned *PendingAddReg);
/// emitCastOperation - Common code shared between visitCastInst and
/// constant expression cast support.
void emitMultiply(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
Value *Op0, Value *Op1, unsigned TargetReg);
- void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
- unsigned DestReg, const Type *DestTy,
- unsigned Op0Reg, unsigned Op1Reg);
+ void doMultiply(MachineBasicBlock *MBB,
+ MachineBasicBlock::iterator IP,
+ unsigned DestReg, Value *Op0, Value *Op1);
+
+ /// doMultiplyConst - This method will multiply the value in Op0Reg by the
+ /// value of the ContantInt *CI
void doMultiplyConst(MachineBasicBlock *MBB,
- MachineBasicBlock::iterator MBBI,
- unsigned DestReg, const Type *DestTy,
- unsigned Op0Reg, unsigned Op1Val);
+ MachineBasicBlock::iterator IP,
+ unsigned DestReg, Value *Op0, ConstantInt *CI);
void emitDivRemOperation(MachineBasicBlock *BB,
MachineBasicBlock::iterator IP,
/// emitSelectOperation - Common code shared between visitSelectInst and the
/// constant expression support.
+ ///
void emitSelectOperation(MachineBasicBlock *MBB,
MachineBasicBlock::iterator IP,
Value *Cond, Value *TrueVal, Value *FalseVal,
unsigned DestReg);
+ /// copyGlobalBaseToRegister - Output the instructions required to put the
+ /// base address to use for accessing globals into a register.
+ ///
+ void ISel::copyGlobalBaseToRegister(MachineBasicBlock *MBB,
+ MachineBasicBlock::iterator IP,
+ unsigned R);
+
/// copyConstantToRegister - Output the instructions required to put the
/// specified constant into the specified register.
///
///
/// Long values are handled somewhat specially. They are always allocated
/// as pairs of 32 bit integer values. The register number returned is the
- /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
- /// of the long value.
+ /// high 32 bits of the long value, and the regNum+1 is the low 32 bits.
///
unsigned makeAnotherReg(const Type *Ty) {
assert(dynamic_cast<const PowerPCRegisterInfo*>(TM.getRegisterInfo()) &&
"Current target doesn't have PPC reg info??");
- const PowerPCRegisterInfo *MRI =
+ const PowerPCRegisterInfo *PPCRI =
static_cast<const PowerPCRegisterInfo*>(TM.getRegisterInfo());
if (Ty == Type::LongTy || Ty == Type::ULongTy) {
- const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
- // Create the lower part
+ const TargetRegisterClass *RC = PPCRI->getRegClassForType(Type::IntTy);
+ // Create the upper part
F->getSSARegMap()->createVirtualRegister(RC);
- // Create the upper part.
+ // Create the lower part.
return F->getSSARegMap()->createVirtualRegister(RC)-1;
}
// Add the mapping of regnumber => reg class to MachineFunction
- const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
+ const TargetRegisterClass *RC = PPCRI->getRegClassForType(Ty);
return F->getSSARegMap()->createVirtualRegister(RC);
}
}
unsigned getReg(Value *V, MachineBasicBlock *MBB,
MachineBasicBlock::iterator IPt);
+
+ /// canUseAsImmediateForOpcode - This method returns whether a ConstantInt
+ /// is okay to use as an immediate argument to a certain binary operation
+ bool canUseAsImmediateForOpcode(ConstantInt *CI, unsigned Opcode);
/// getFixedSizedAllocaFI - Return the frame index for a fixed sized alloca
/// that is to be statically allocated with the initial stack frame
///
unsigned ISel::getReg(Value *V, MachineBasicBlock *MBB,
MachineBasicBlock::iterator IPt) {
- // If this operand is a constant, emit the code to copy the constant into
- // the register here...
- //
if (Constant *C = dyn_cast<Constant>(V)) {
unsigned Reg = makeAnotherReg(V->getType());
copyConstantToRegister(MBB, IPt, C, Reg);
return Reg;
- } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
- // GV is located at PC + distance
- unsigned CurPC = makeAnotherReg(Type::IntTy);
- unsigned Reg1 = makeAnotherReg(V->getType());
- unsigned Reg2 = makeAnotherReg(V->getType());
- // Move PC to destination reg
- BuildMI(*MBB, IPt, PPC32::MovePCtoLR, 0, CurPC);
- // Move value at PC + distance into return reg
- BuildMI(*MBB, IPt, PPC32::LOADHiAddr, 2, Reg1).addReg(CurPC)
- .addGlobalAddress(GV);
- BuildMI(*MBB, IPt, PPC32::LOADLoAddr, 2, Reg2).addReg(Reg1)
- .addGlobalAddress(GV);
- return Reg2;
- } else if (CastInst *CI = dyn_cast<CastInst>(V)) {
- // Do not emit noop casts at all.
- if (getClassB(CI->getType()) == getClassB(CI->getOperand(0)->getType()))
- return getReg(CI->getOperand(0), MBB, IPt);
} else if (AllocaInst *AI = dyn_castFixedAlloca(V)) {
unsigned Reg = makeAnotherReg(V->getType());
unsigned FI = getFixedSizedAllocaFI(AI);
- addFrameReference(BuildMI(*MBB, IPt, PPC32::ADDI, 2, Reg), FI, 0, false);
+ addFrameReference(BuildMI(*MBB, IPt, PPC::ADDI, 2, Reg), FI, 0, false);
return Reg;
}
return Reg;
}
+/// canUseAsImmediateForOpcode - This method returns whether a ConstantInt
+/// is okay to use as an immediate argument to a certain binary operator.
+///
+/// Operator is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for Xor.
+bool ISel::canUseAsImmediateForOpcode(ConstantInt *CI, unsigned Operator) {
+ ConstantSInt *Op1Cs;
+ ConstantUInt *Op1Cu;
+
+ // ADDI, Compare, and non-indexed Load take SIMM
+ bool cond1 = (Operator == 0)
+ && (Op1Cs = dyn_cast<ConstantSInt>(CI))
+ && (Op1Cs->getValue() <= 32767)
+ && (Op1Cs->getValue() >= -32768);
+
+ // SUBI takes -SIMM since it is a mnemonic for ADDI
+ bool cond2 = (Operator == 1)
+ && (Op1Cs = dyn_cast<ConstantSInt>(CI))
+ && (Op1Cs->getValue() <= 32768)
+ && (Op1Cs->getValue() >= -32767);
+
+ // ANDIo, ORI, and XORI take unsigned values
+ bool cond3 = (Operator >= 2)
+ && (Op1Cs = dyn_cast<ConstantSInt>(CI))
+ && (Op1Cs->getValue() >= 0)
+ && (Op1Cs->getValue() <= 32767);
+
+ // ADDI and SUBI take SIMMs, so we have to make sure the UInt would fit
+ bool cond4 = (Operator < 2)
+ && (Op1Cu = dyn_cast<ConstantUInt>(CI))
+ && (Op1Cu->getValue() <= 32767);
+
+ // ANDIo, ORI, and XORI take UIMMs, so they can be larger
+ bool cond5 = (Operator >= 2)
+ && (Op1Cu = dyn_cast<ConstantUInt>(CI))
+ && (Op1Cu->getValue() <= 65535);
+
+ if (cond1 || cond2 || cond3 || cond4 || cond5)
+ return true;
+
+ return false;
+}
+
/// getFixedSizedAllocaFI - Return the frame index for a fixed sized alloca
/// that is to be statically allocated with the initial stack frame
/// adjustment.
}
+/// copyGlobalBaseToRegister - Output the instructions required to put the
+/// base address to use for accessing globals into a register.
+///
+void ISel::copyGlobalBaseToRegister(MachineBasicBlock *MBB,
+ MachineBasicBlock::iterator IP,
+ unsigned R) {
+ if (!GlobalBaseInitialized) {
+ // Insert the set of GlobalBaseReg into the first MBB of the function
+ MachineBasicBlock &FirstMBB = F->front();
+ MachineBasicBlock::iterator MBBI = FirstMBB.begin();
+ GlobalBaseReg = makeAnotherReg(Type::IntTy);
+ BuildMI(FirstMBB, MBBI, PPC::IMPLICIT_DEF, 0, PPC::LR);
+ BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, GlobalBaseReg);
+ GlobalBaseInitialized = true;
+ }
+ // Emit our copy of GlobalBaseReg to the destination register in the
+ // current MBB
+ BuildMI(*MBB, IP, PPC::OR, 2, R).addReg(GlobalBaseReg)
+ .addReg(GlobalBaseReg);
+}
+
/// copyConstantToRegister - Output the instructions required to put the
/// specified constant into the specified register.
///
unsigned Class = getClassB(C->getType());
if (Class == cLong) {
- // Copy the value into the register pair.
- uint64_t Val = cast<ConstantInt>(C)->getRawValue();
- unsigned hiTmp = makeAnotherReg(Type::IntTy);
- unsigned loTmp = makeAnotherReg(Type::IntTy);
- BuildMI(*MBB, IP, PPC32::ADDIS, 2, loTmp).addReg(PPC32::R0)
- .addImm(Val >> 48);
- BuildMI(*MBB, IP, PPC32::ORI, 2, R).addReg(loTmp)
- .addImm((Val >> 32) & 0xFFFF);
- BuildMI(*MBB, IP, PPC32::ADDIS, 2, hiTmp).addReg(PPC32::R0)
- .addImm((Val >> 16) & 0xFFFF);
- BuildMI(*MBB, IP, PPC32::ORI, 2, R+1).addReg(hiTmp).addImm(Val & 0xFFFF);
- return;
+ if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(C)) {
+ uint64_t uval = CUI->getValue();
+ unsigned hiUVal = uval >> 32;
+ unsigned loUVal = uval;
+ ConstantUInt *CUHi = ConstantUInt::get(Type::UIntTy, hiUVal);
+ ConstantUInt *CULo = ConstantUInt::get(Type::UIntTy, loUVal);
+ copyConstantToRegister(MBB, IP, CUHi, R);
+ copyConstantToRegister(MBB, IP, CULo, R+1);
+ return;
+ } else if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(C)) {
+ int64_t sval = CSI->getValue();
+ int hiSVal = sval >> 32;
+ int loSVal = sval;
+ ConstantSInt *CSHi = ConstantSInt::get(Type::IntTy, hiSVal);
+ ConstantSInt *CSLo = ConstantSInt::get(Type::IntTy, loSVal);
+ copyConstantToRegister(MBB, IP, CSHi, R);
+ copyConstantToRegister(MBB, IP, CSLo, R+1);
+ return;
+ } else {
+ std::cerr << "Unhandled long constant type!\n";
+ abort();
+ }
}
-
+
assert(Class <= cInt && "Type not handled yet!");
+ // Handle bool
if (C->getType() == Type::BoolTy) {
- BuildMI(*MBB, IP, PPC32::ADDI, 2, R).addReg(PPC32::R0)
- .addImm(C == ConstantBool::True);
- } else if (Class == cByte || Class == cShort) {
- ConstantInt *CI = cast<ConstantInt>(C);
- BuildMI(*MBB, IP, PPC32::ADDI, 2, R).addReg(PPC32::R0)
- .addImm(CI->getRawValue());
- } else {
- ConstantInt *CI = cast<ConstantInt>(C);
- int TheVal = CI->getRawValue() & 0xFFFFFFFF;
- if (TheVal < 32768 && TheVal >= -32768) {
- BuildMI(*MBB, IP, PPC32::ADDI, 2, R).addReg(PPC32::R0)
- .addImm(CI->getRawValue());
+ BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(C == ConstantBool::True);
+ return;
+ }
+
+ // Handle int
+ if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(C)) {
+ unsigned uval = CUI->getValue();
+ if (uval < 32768) {
+ BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(uval);
} else {
- unsigned TmpReg = makeAnotherReg(Type::IntTy);
- BuildMI(*MBB, IP, PPC32::ADDIS, 2, TmpReg).addReg(PPC32::R0)
- .addImm(CI->getRawValue() >> 16);
- BuildMI(*MBB, IP, PPC32::ORI, 2, R).addReg(TmpReg)
- .addImm(CI->getRawValue() & 0xFFFF);
+ unsigned Temp = makeAnotherReg(Type::IntTy);
+ BuildMI(*MBB, IP, PPC::LIS, 1, Temp).addSImm(uval >> 16);
+ BuildMI(*MBB, IP, PPC::ORI, 2, R).addReg(Temp).addImm(uval);
}
+ return;
+ } else if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(C)) {
+ int sval = CSI->getValue();
+ if (sval < 32768 && sval >= -32768) {
+ BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(sval);
+ } else {
+ unsigned Temp = makeAnotherReg(Type::IntTy);
+ BuildMI(*MBB, IP, PPC::LIS, 1, Temp).addSImm(sval >> 16);
+ BuildMI(*MBB, IP, PPC::ORI, 2, R).addReg(Temp).addImm(sval);
+ }
+ return;
}
+ std::cerr << "Unhandled integer constant!\n";
+ abort();
} else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
// We need to spill the constant to memory...
MachineConstantPool *CP = F->getConstantPool();
assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
- // Load addr of constant to reg; constant is located at PC + distance
- unsigned CurPC = makeAnotherReg(Type::IntTy);
+ // Load addr of constant to reg; constant is located at base + distance
+ unsigned GlobalBase = makeAnotherReg(Type::IntTy);
unsigned Reg1 = makeAnotherReg(Type::IntTy);
unsigned Reg2 = makeAnotherReg(Type::IntTy);
- // Move PC to destination reg
- BuildMI(*MBB, IP, PPC32::MovePCtoLR, 0, CurPC);
- // Move value at PC + distance into return reg
- BuildMI(*MBB, IP, PPC32::LOADHiAddr, 2, Reg1).addReg(CurPC)
+ // Move value at base + distance into return reg
+ copyGlobalBaseToRegister(MBB, IP, GlobalBase);
+ BuildMI(*MBB, IP, PPC::LOADHiAddr, 2, Reg1).addReg(GlobalBase)
.addConstantPoolIndex(CPI);
- BuildMI(*MBB, IP, PPC32::LOADLoAddr, 2, Reg2).addReg(Reg1)
+ BuildMI(*MBB, IP, PPC::LOADLoDirect, 2, Reg2).addReg(Reg1)
.addConstantPoolIndex(CPI);
-
- unsigned LoadOpcode = (Ty == Type::FloatTy) ? PPC32::LFS : PPC32::LFD;
- BuildMI(*MBB, IP, LoadOpcode, 2, R).addImm(0).addReg(Reg2);
+ BuildMI(*MBB, IP, PPC::LFD, 2, R).addSImm(0).addReg(Reg2);
} else if (isa<ConstantPointerNull>(C)) {
// Copy zero (null pointer) to the register.
- BuildMI(*MBB, IP, PPC32::ADDI, 2, R).addReg(PPC32::R0).addImm(0);
- } else if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(C)) {
- BuildMI(*MBB, IP, PPC32::ADDIS, 2, R).addReg(PPC32::R0)
- .addGlobalAddress(CPR->getValue());
- BuildMI(*MBB, IP, PPC32::ORI, 2, R).addReg(PPC32::R0)
- .addGlobalAddress(CPR->getValue());
+ BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(0);
+ } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
+ // GV is located at base + distance
+ unsigned GlobalBase = makeAnotherReg(Type::IntTy);
+ unsigned TmpReg = makeAnotherReg(GV->getType());
+ unsigned Opcode = (GV->hasWeakLinkage() || GV->isExternal()
+ || dyn_cast<Function>(GV)) ?
+ PPC::LOADLoIndirect : PPC::LOADLoDirect;
+
+ // Move value at base + distance into return reg
+ copyGlobalBaseToRegister(MBB, IP, GlobalBase);
+ BuildMI(*MBB, IP, PPC::LOADHiAddr, 2, TmpReg).addReg(GlobalBase)
+ .addGlobalAddress(GV);
+ BuildMI(*MBB, IP, Opcode, 2, R).addReg(TmpReg).addGlobalAddress(GV);
+
+ // Add the GV to the list of things whose addresses have been taken.
+ TM.AddressTaken.insert(GV);
} else {
- std::cerr << "Offending constant: " << C << "\n";
+ std::cerr << "Offending constant: " << *C << "\n";
assert(0 && "Type not handled yet!");
}
}
/// LoadArgumentsToVirtualRegs - Load all of the arguments to this function from
/// the stack into virtual registers.
-///
-/// FIXME: When we can calculate which args are coming in via registers
-/// source them from there instead.
void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
- unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
+ unsigned ArgOffset = 24;
unsigned GPR_remaining = 8;
unsigned FPR_remaining = 13;
unsigned GPR_idx = 0, FPR_idx = 0;
static const unsigned GPR[] = {
- PPC32::R3, PPC32::R4, PPC32::R5, PPC32::R6,
- PPC32::R7, PPC32::R8, PPC32::R9, PPC32::R10,
+ PPC::R3, PPC::R4, PPC::R5, PPC::R6,
+ PPC::R7, PPC::R8, PPC::R9, PPC::R10,
};
static const unsigned FPR[] = {
- PPC32::F1, PPC32::F2, PPC32::F3, PPC32::F4, PPC32::F5, PPC32::F6, PPC32::F7,
- PPC32::F8, PPC32::F9, PPC32::F10, PPC32::F11, PPC32::F12, PPC32::F13
+ PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
+ PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
};
MachineFrameInfo *MFI = F->getFrameInfo();
switch (getClassB(I->getType())) {
case cByte:
if (ArgLive) {
- FI = MFI->CreateFixedObject(1, ArgOffset);
+ FI = MFI->CreateFixedObject(4, ArgOffset);
if (GPR_remaining > 0) {
- BuildMI(BB, PPC32::OR, 2, Reg).addReg(GPR[GPR_idx])
+ BuildMI(BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
+ BuildMI(BB, PPC::OR, 2, Reg).addReg(GPR[GPR_idx])
.addReg(GPR[GPR_idx]);
} else {
- addFrameReference(BuildMI(BB, PPC32::LBZ, 2, Reg), FI);
+ addFrameReference(BuildMI(BB, PPC::LBZ, 2, Reg), FI);
}
}
break;
case cShort:
if (ArgLive) {
- FI = MFI->CreateFixedObject(2, ArgOffset);
+ FI = MFI->CreateFixedObject(4, ArgOffset);
if (GPR_remaining > 0) {
- BuildMI(BB, PPC32::OR, 2, Reg).addReg(GPR[GPR_idx])
+ BuildMI(BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
+ BuildMI(BB, PPC::OR, 2, Reg).addReg(GPR[GPR_idx])
.addReg(GPR[GPR_idx]);
} else {
- addFrameReference(BuildMI(BB, PPC32::LHZ, 2, Reg), FI);
+ addFrameReference(BuildMI(BB, PPC::LHZ, 2, Reg), FI);
}
}
break;
if (ArgLive) {
FI = MFI->CreateFixedObject(4, ArgOffset);
if (GPR_remaining > 0) {
- BuildMI(BB, PPC32::OR, 2, Reg).addReg(GPR[GPR_idx])
+ BuildMI(BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
+ BuildMI(BB, PPC::OR, 2, Reg).addReg(GPR[GPR_idx])
.addReg(GPR[GPR_idx]);
} else {
- addFrameReference(BuildMI(BB, PPC32::LWZ, 2, Reg), FI);
+ addFrameReference(BuildMI(BB, PPC::LWZ, 2, Reg), FI);
}
}
break;
if (ArgLive) {
FI = MFI->CreateFixedObject(8, ArgOffset);
if (GPR_remaining > 1) {
- BuildMI(BB, PPC32::OR, 2, Reg).addReg(GPR[GPR_idx])
+ BuildMI(BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
+ BuildMI(BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx+1]);
+ BuildMI(BB, PPC::OR, 2, Reg).addReg(GPR[GPR_idx])
.addReg(GPR[GPR_idx]);
- BuildMI(BB, PPC32::OR, 2, Reg+1).addReg(GPR[GPR_idx+1])
+ BuildMI(BB, PPC::OR, 2, Reg+1).addReg(GPR[GPR_idx+1])
.addReg(GPR[GPR_idx+1]);
} else {
- addFrameReference(BuildMI(BB, PPC32::LWZ, 2, Reg), FI);
- addFrameReference(BuildMI(BB, PPC32::LWZ, 2, Reg+1), FI, 4);
+ addFrameReference(BuildMI(BB, PPC::LWZ, 2, Reg), FI);
+ addFrameReference(BuildMI(BB, PPC::LWZ, 2, Reg+1), FI, 4);
}
}
- ArgOffset += 4; // longs require 4 additional bytes
+ // longs require 4 additional bytes and use 2 GPRs
+ ArgOffset += 4;
if (GPR_remaining > 1) {
- GPR_remaining--; // uses up 2 GPRs
+ GPR_remaining--;
GPR_idx++;
}
break;
- case cFP:
- if (ArgLive) {
- unsigned Opcode;
- if (I->getType() == Type::FloatTy) {
- Opcode = PPC32::LFS;
- FI = MFI->CreateFixedObject(4, ArgOffset);
+ case cFP32:
+ if (ArgLive) {
+ FI = MFI->CreateFixedObject(4, ArgOffset);
+
+ if (FPR_remaining > 0) {
+ BuildMI(BB, PPC::IMPLICIT_DEF, 0, FPR[FPR_idx]);
+ BuildMI(BB, PPC::FMR, 1, Reg).addReg(FPR[FPR_idx]);
+ FPR_remaining--;
+ FPR_idx++;
} else {
- Opcode = PPC32::LFD;
- FI = MFI->CreateFixedObject(8, ArgOffset);
+ addFrameReference(BuildMI(BB, PPC::LFS, 2, Reg), FI);
}
+ }
+ break;
+ case cFP64:
+ if (ArgLive) {
+ FI = MFI->CreateFixedObject(8, ArgOffset);
+
if (FPR_remaining > 0) {
- BuildMI(BB, PPC32::FMR, 1, Reg).addReg(FPR[FPR_idx]);
+ BuildMI(BB, PPC::IMPLICIT_DEF, 0, FPR[FPR_idx]);
+ BuildMI(BB, PPC::FMR, 1, Reg).addReg(FPR[FPR_idx]);
FPR_remaining--;
FPR_idx++;
} else {
- addFrameReference(BuildMI(BB, Opcode, 2, Reg), FI);
+ addFrameReference(BuildMI(BB, PPC::LFD, 2, Reg), FI);
}
}
- if (I->getType() == Type::DoubleTy) {
- ArgOffset += 4; // doubles require 4 additional bytes
- if (GPR_remaining > 0) {
- GPR_remaining--; // uses up 2 GPRs
- GPR_idx++;
- }
+
+ // doubles require 4 additional bytes and use 2 GPRs of param space
+ ArgOffset += 4;
+ if (GPR_remaining > 0) {
+ GPR_remaining--;
+ GPR_idx++;
}
break;
default:
// the start of the first vararg value... this is used to expand
// llvm.va_start.
if (Fn.getFunctionType()->isVarArg())
- VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
+ VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
}
// Create a new machine instr PHI node, and insert it.
unsigned PHIReg = getReg(*PN);
MachineInstr *PhiMI = BuildMI(MBB, PHIInsertPoint,
- PPC32::PHI, PN->getNumOperands(), PHIReg);
+ PPC::PHI, PN->getNumOperands(), PHIReg);
MachineInstr *LongPhiMI = 0;
if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy)
LongPhiMI = BuildMI(MBB, PHIInsertPoint,
- PPC32::PHI, PN->getNumOperands(), PHIReg+1);
+ PPC::PHI, PN->getNumOperands(), PHIReg+1);
// PHIValues - Map of blocks to incoming virtual registers. We use this
// so that we only initialize one incoming value for a particular block,
// We already inserted an initialization of the register for this
// predecessor. Recycle it.
ValReg = EntryIt->second;
-
- } else {
+ } else {
// Get the incoming value into a virtual register.
//
Value *Val = PN->getIncomingValue(i);
// might be arbitrarily complex if it is a constant expression),
// just insert the computation at the top of the basic block.
MachineBasicBlock::iterator PI = PredMBB->begin();
-
+
// Skip over any PHI nodes though!
- while (PI != PredMBB->end() && PI->getOpcode() == PPC32::PHI)
+ while (PI != PredMBB->end() && PI->getOpcode() == PPC::PHI)
++PI;
-
+
ValReg = getReg(Val, PredMBB, PI);
}
// it into the conditional branch or select instruction which is the only user
// of the cc instruction. This is the case if the conditional branch is the
// only user of the setcc, and if the setcc is in the same basic block as the
-// conditional branch. We also don't handle long arguments below, so we reject
-// them here as well.
+// conditional branch.
//
static SetCondInst *canFoldSetCCIntoBranchOrSelect(Value *V) {
if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
if (SCI->hasOneUse()) {
Instruction *User = cast<Instruction>(SCI->use_back());
if ((isa<BranchInst>(User) || isa<SelectInst>(User)) &&
- SCI->getParent() == User->getParent() &&
- (getClassB(SCI->getOperand(0)->getType()) != cLong ||
- SCI->getOpcode() == Instruction::SetEQ ||
- SCI->getOpcode() == Instruction::SetNE))
+ SCI->getParent() == User->getParent())
return SCI;
}
return 0;
}
+
+// canFoldGEPIntoLoadOrStore - Return the GEP instruction if we can fold it into
+// the load or store instruction that is the only user of the GEP.
+//
+static GetElementPtrInst *canFoldGEPIntoLoadOrStore(Value *V) {
+ if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(V))
+ if (GEPI->hasOneUse()) {
+ Instruction *User = cast<Instruction>(GEPI->use_back());
+ if (isa<StoreInst>(User) &&
+ GEPI->getParent() == User->getParent() &&
+ User->getOperand(0) != GEPI &&
+ User->getOperand(1) == GEPI) {
+ ++GEPFolds;
+ return GEPI;
+ }
+ if (isa<LoadInst>(User) &&
+ GEPI->getParent() == User->getParent() &&
+ User->getOperand(0) == GEPI) {
+ ++GEPFolds;
+ return GEPI;
+ }
+ }
+ return 0;
+}
+
+
// Return a fixed numbering for setcc instructions which does not depend on the
// order of the opcodes.
//
static unsigned getPPCOpcodeForSetCCNumber(unsigned Opcode) {
switch (Opcode) {
default: assert(0 && "Unknown setcc instruction!");
- case Instruction::SetEQ: return PPC32::BEQ;
- case Instruction::SetNE: return PPC32::BNE;
- case Instruction::SetLT: return PPC32::BLT;
- case Instruction::SetGE: return PPC32::BGE;
- case Instruction::SetGT: return PPC32::BGT;
- case Instruction::SetLE: return PPC32::BLE;
- }
-}
-
-static unsigned invertPPCBranchOpcode(unsigned Opcode) {
- switch (Opcode) {
- default: assert(0 && "Unknown PPC32 branch opcode!");
- case PPC32::BEQ: return PPC32::BNE;
- case PPC32::BNE: return PPC32::BEQ;
- case PPC32::BLT: return PPC32::BGE;
- case PPC32::BGE: return PPC32::BLT;
- case PPC32::BGT: return PPC32::BLE;
- case PPC32::BLE: return PPC32::BGT;
+ case Instruction::SetEQ: return PPC::BEQ;
+ case Instruction::SetNE: return PPC::BNE;
+ case Instruction::SetLT: return PPC::BLT;
+ case Instruction::SetGE: return PPC::BGE;
+ case Instruction::SetGT: return PPC::BGT;
+ case Instruction::SetLE: return PPC::BLE;
}
}
/// emitUCOM - emits an unordered FP compare.
void ISel::emitUCOM(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
unsigned LHS, unsigned RHS) {
- BuildMI(*MBB, IP, PPC32::FCMPU, 2, PPC32::CR0).addReg(LHS).addReg(RHS);
+ BuildMI(*MBB, IP, PPC::FCMPU, 2, PPC::CR0).addReg(LHS).addReg(RHS);
}
-// EmitComparison - This function emits a comparison of the two operands,
-// returning the extended setcc code to use.
+/// EmitComparison - emits a comparison of the two operands, returning the
+/// extended setcc code to use. The result is in CR0.
+///
unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
MachineBasicBlock *MBB,
MachineBasicBlock::iterator IP) {
unsigned Class = getClassB(CompTy);
unsigned Op0r = getReg(Op0, MBB, IP);
+ // Before we do a comparison, we have to make sure that we're truncating our
+ // registers appropriately.
+ if (Class == cByte) {
+ unsigned TmpReg = makeAnotherReg(CompTy);
+ if (CompTy->isSigned())
+ BuildMI(*MBB, IP, PPC::EXTSB, 1, TmpReg).addReg(Op0r);
+ else
+ BuildMI(*MBB, IP, PPC::RLWINM, 4, TmpReg).addReg(Op0r).addImm(0)
+ .addImm(24).addImm(31);
+ Op0r = TmpReg;
+ } else if (Class == cShort) {
+ unsigned TmpReg = makeAnotherReg(CompTy);
+ if (CompTy->isSigned())
+ BuildMI(*MBB, IP, PPC::EXTSH, 1, TmpReg).addReg(Op0r);
+ else
+ BuildMI(*MBB, IP, PPC::RLWINM, 4, TmpReg).addReg(Op0r).addImm(0)
+ .addImm(16).addImm(31);
+ Op0r = TmpReg;
+ }
+
+ // Use crand for lt, gt and crandc for le, ge
+ unsigned CROpcode = (OpNum == 2 || OpNum == 4) ? PPC::CRAND : PPC::CRANDC;
+ // ? cr1[lt] : cr1[gt]
+ unsigned CR1field = (OpNum == 2 || OpNum == 3) ? 4 : 5;
+ // ? cr0[lt] : cr0[gt]
+ unsigned CR0field = (OpNum == 2 || OpNum == 5) ? 0 : 1;
+ unsigned Opcode = CompTy->isSigned() ? PPC::CMPW : PPC::CMPLW;
+ unsigned OpcodeImm = CompTy->isSigned() ? PPC::CMPWI : PPC::CMPLWI;
+
// Special case handling of: cmp R, i
- if (isa<ConstantPointerNull>(Op1)) {
- BuildMI(*MBB, IP, PPC32::CMPI, 2, PPC32::CR0).addReg(Op0r).addImm(0);
- } else if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
+ if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
if (Class == cByte || Class == cShort || Class == cInt) {
- unsigned Op1v = CI->getRawValue();
-
- // Mask off any upper bits of the constant, if there are any...
- Op1v &= (1ULL << (8 << Class)) - 1;
+ unsigned Op1v = CI->getRawValue() & 0xFFFF;
- // Compare immediate or promote to reg?
- if (Op1v <= 32767) {
- BuildMI(*MBB, IP, CompTy->isSigned() ? PPC32::CMPI : PPC32::CMPLI, 3,
- PPC32::CR0).addImm(0).addReg(Op0r).addImm(Op1v);
+ // Treat compare like ADDI for the purposes of immediate suitability
+ if (canUseAsImmediateForOpcode(CI, 0)) {
+ BuildMI(*MBB, IP, OpcodeImm, 2, PPC::CR0).addReg(Op0r).addSImm(Op1v);
} else {
unsigned Op1r = getReg(Op1, MBB, IP);
- BuildMI(*MBB, IP, CompTy->isSigned() ? PPC32::CMP : PPC32::CMPL, 3,
- PPC32::CR0).addImm(0).addReg(Op0r).addReg(Op1r);
+ BuildMI(*MBB, IP, Opcode, 2, PPC::CR0).addReg(Op0r).addReg(Op1r);
}
return OpNum;
} else {
unsigned LowCst = CI->getRawValue();
unsigned HiCst = CI->getRawValue() >> 32;
if (OpNum < 2) { // seteq, setne
- unsigned LoTmp = Op0r;
- if (LowCst != 0) {
- unsigned LoLow = makeAnotherReg(Type::IntTy);
- unsigned LoTmp = makeAnotherReg(Type::IntTy);
- BuildMI(*MBB, IP, PPC32::XORI, 2, LoLow).addReg(Op0r).addImm(LowCst);
- BuildMI(*MBB, IP, PPC32::XORIS, 2, LoTmp).addReg(LoLow)
- .addImm(LowCst >> 16);
- }
- unsigned HiTmp = Op0r+1;
- if (HiCst != 0) {
- unsigned HiLow = makeAnotherReg(Type::IntTy);
- unsigned HiTmp = makeAnotherReg(Type::IntTy);
- BuildMI(*MBB, IP, PPC32::XORI, 2, HiLow).addReg(Op0r+1).addImm(HiCst);
- BuildMI(*MBB, IP, PPC32::XORIS, 2, HiTmp).addReg(HiLow)
- .addImm(HiCst >> 16);
- }
+ unsigned LoLow = makeAnotherReg(Type::IntTy);
+ unsigned LoTmp = makeAnotherReg(Type::IntTy);
+ unsigned HiLow = makeAnotherReg(Type::IntTy);
+ unsigned HiTmp = makeAnotherReg(Type::IntTy);
unsigned FinalTmp = makeAnotherReg(Type::IntTy);
- BuildMI(*MBB, IP, PPC32::ORo, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
- //BuildMI(*MBB, IP, PPC32::CMPLI, 2, PPC32::CR0).addReg(FinalTmp).addImm(0);
+
+ BuildMI(*MBB, IP, PPC::XORI, 2, LoLow).addReg(Op0r+1)
+ .addImm(LowCst & 0xFFFF);
+ BuildMI(*MBB, IP, PPC::XORIS, 2, LoTmp).addReg(LoLow)
+ .addImm(LowCst >> 16);
+ BuildMI(*MBB, IP, PPC::XORI, 2, HiLow).addReg(Op0r)
+ .addImm(HiCst & 0xFFFF);
+ BuildMI(*MBB, IP, PPC::XORIS, 2, HiTmp).addReg(HiLow)
+ .addImm(HiCst >> 16);
+ BuildMI(*MBB, IP, PPC::ORo, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
return OpNum;
} else {
- // FIXME: Not Yet Implemented
- std::cerr << "EmitComparison unimplemented: Opnum >= 2\n";
- abort();
+ unsigned ConstReg = makeAnotherReg(CompTy);
+ copyConstantToRegister(MBB, IP, CI, ConstReg);
+
+ // cr0 = r3 ccOpcode r5 or (r3 == r5 AND r4 ccOpcode r6)
+ BuildMI(*MBB, IP, Opcode, 2, PPC::CR0).addReg(Op0r)
+ .addReg(ConstReg);
+ BuildMI(*MBB, IP, Opcode, 2, PPC::CR1).addReg(Op0r+1)
+ .addReg(ConstReg+1);
+ BuildMI(*MBB, IP, PPC::CRAND, 3).addImm(2).addImm(2).addImm(CR1field);
+ BuildMI(*MBB, IP, PPC::CROR, 3).addImm(CR0field).addImm(CR0field)
+ .addImm(2);
return OpNum;
}
}
}
unsigned Op1r = getReg(Op1, MBB, IP);
+
switch (Class) {
default: assert(0 && "Unknown type class!");
case cByte:
case cShort:
case cInt:
- BuildMI(*MBB, IP, CompTy->isSigned() ? PPC32::CMP : PPC32::CMPL, 2,
- PPC32::CR0).addReg(Op0r).addReg(Op1r);
+ BuildMI(*MBB, IP, Opcode, 2, PPC::CR0).addReg(Op0r).addReg(Op1r);
break;
- case cFP:
+ case cFP32:
+ case cFP64:
emitUCOM(MBB, IP, Op0r, Op1r);
break;
unsigned LoTmp = makeAnotherReg(Type::IntTy);
unsigned HiTmp = makeAnotherReg(Type::IntTy);
unsigned FinalTmp = makeAnotherReg(Type::IntTy);
- BuildMI(*MBB, IP, PPC32::XOR, 2, LoTmp).addReg(Op0r).addReg(Op1r);
- BuildMI(*MBB, IP, PPC32::XOR, 2, HiTmp).addReg(Op0r+1).addReg(Op1r+1);
- BuildMI(*MBB, IP, PPC32::ORo, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
- //BuildMI(*MBB, IP, PPC32::CMPLI, 2, PPC32::CR0).addReg(FinalTmp).addImm(0);
+ BuildMI(*MBB, IP, PPC::XOR, 2, HiTmp).addReg(Op0r).addReg(Op1r);
+ BuildMI(*MBB, IP, PPC::XOR, 2, LoTmp).addReg(Op0r+1).addReg(Op1r+1);
+ BuildMI(*MBB, IP, PPC::ORo, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
break; // Allow the sete or setne to be generated from flags set by OR
} else {
- // FIXME: Not Yet Implemented
- std::cerr << "EmitComparison (cLong) unimplemented: Opnum >= 2\n";
- abort();
+ unsigned TmpReg1 = makeAnotherReg(Type::IntTy);
+ unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
+
+ // cr0 = r3 ccOpcode r5 or (r3 == r5 AND r4 ccOpcode r6)
+ BuildMI(*MBB, IP, Opcode, 2, PPC::CR0).addReg(Op0r).addReg(Op1r);
+ BuildMI(*MBB, IP, Opcode, 2, PPC::CR1).addReg(Op0r+1).addReg(Op1r+1);
+ BuildMI(*MBB, IP, PPC::CRAND, 3).addImm(2).addImm(2).addImm(CR1field);
+ BuildMI(*MBB, IP, PPC::CROR, 3).addImm(CR0field).addImm(CR0field)
+ .addImm(2);
return OpNum;
}
}
void ISel::visitSetCondInst(SetCondInst &I) {
if (canFoldSetCCIntoBranchOrSelect(&I))
return;
-
- unsigned Op0Reg = getReg(I.getOperand(0));
- unsigned Op1Reg = getReg(I.getOperand(1));
+
unsigned DestReg = getReg(I);
unsigned OpNum = I.getOpcode();
const Type *Ty = I.getOperand (0)->getType();
-
+
EmitComparison(OpNum, I.getOperand(0), I.getOperand(1), BB, BB->end());
-
+
unsigned Opcode = getPPCOpcodeForSetCCNumber(OpNum);
MachineBasicBlock *thisMBB = BB;
const BasicBlock *LLVM_BB = BB->getBasicBlock();
+ ilist<MachineBasicBlock>::iterator It = BB;
+ ++It;
+
// thisMBB:
// ...
// cmpTY cr0, r1, r2
// if we could insert other, non-terminator instructions after the
// bCC. But MBB->getFirstTerminator() can't understand this.
MachineBasicBlock *copy1MBB = new MachineBasicBlock(LLVM_BB);
- F->getBasicBlockList().push_back(copy1MBB);
- BuildMI(BB, Opcode, 2).addReg(PPC32::CR0).addMBB(copy1MBB);
+ F->getBasicBlockList().insert(It, copy1MBB);
+ BuildMI(BB, Opcode, 2).addReg(PPC::CR0).addMBB(copy1MBB);
MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
- F->getBasicBlockList().push_back(copy0MBB);
- BuildMI(BB, PPC32::B, 1).addMBB(copy0MBB);
+ F->getBasicBlockList().insert(It, copy0MBB);
+ BuildMI(BB, PPC::B, 1).addMBB(copy0MBB);
+ MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
+ F->getBasicBlockList().insert(It, sinkMBB);
// Update machine-CFG edges
BB->addSuccessor(copy1MBB);
BB->addSuccessor(copy0MBB);
- // copy0MBB:
- // %FalseValue = li 0
- // b sinkMBB
- BB = copy0MBB;
- unsigned FalseValue = makeAnotherReg(I.getType());
- BuildMI(BB, PPC32::LI, 1, FalseValue).addZImm(0);
- MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
- F->getBasicBlockList().push_back(sinkMBB);
- BuildMI(BB, PPC32::B, 1).addMBB(sinkMBB);
- // Update machine-CFG edges
- BB->addSuccessor(sinkMBB);
-
- DEBUG(std::cerr << "thisMBB is at " << (void*)thisMBB << "\n");
- DEBUG(std::cerr << "copy1MBB is at " << (void*)copy1MBB << "\n");
- DEBUG(std::cerr << "copy0MBB is at " << (void*)copy0MBB << "\n");
- DEBUG(std::cerr << "sinkMBB is at " << (void*)sinkMBB << "\n");
-
// copy1MBB:
// %TrueValue = li 1
// b sinkMBB
BB = copy1MBB;
- unsigned TrueValue = makeAnotherReg (I.getType ());
- BuildMI(BB, PPC32::LI, 1, TrueValue).addZImm(1);
- BuildMI(BB, PPC32::B, 1).addMBB(sinkMBB);
+ unsigned TrueValue = makeAnotherReg(I.getType());
+ BuildMI(BB, PPC::LI, 1, TrueValue).addSImm(1);
+ BuildMI(BB, PPC::B, 1).addMBB(sinkMBB);
+ // Update machine-CFG edges
+ BB->addSuccessor(sinkMBB);
+
+ // copy0MBB:
+ // %FalseValue = li 0
+ // fallthrough
+ BB = copy0MBB;
+ unsigned FalseValue = makeAnotherReg(I.getType());
+ BuildMI(BB, PPC::LI, 1, FalseValue).addSImm(0);
// Update machine-CFG edges
BB->addSuccessor(sinkMBB);
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, copy1MBB ]
// ...
BB = sinkMBB;
- BuildMI(BB, PPC32::PHI, 4, DestReg).addReg(FalseValue)
+ BuildMI(BB, PPC::PHI, 4, DestReg).addReg(FalseValue)
.addMBB(copy0MBB).addReg(TrueValue).addMBB(copy1MBB);
}
Value *Cond, Value *TrueVal, Value *FalseVal,
unsigned DestReg) {
unsigned SelectClass = getClassB(TrueVal->getType());
+ unsigned Opcode;
+
+ // See if we can fold the setcc into the select instruction, or if we have
+ // to get the register of the Cond value
+ if (SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(Cond)) {
+ // We successfully folded the setcc into the select instruction.
+ unsigned OpNum = getSetCCNumber(SCI->getOpcode());
+ OpNum = EmitComparison(OpNum, SCI->getOperand(0),SCI->getOperand(1),MBB,IP);
+ Opcode = getPPCOpcodeForSetCCNumber(SCI->getOpcode());
+ } else {
+ unsigned CondReg = getReg(Cond, MBB, IP);
+ BuildMI(*MBB, IP, PPC::CMPI, 2, PPC::CR0).addReg(CondReg).addSImm(0);
+ Opcode = getPPCOpcodeForSetCCNumber(Instruction::SetNE);
+ }
- unsigned TrueReg = getReg(TrueVal, MBB, IP);
- unsigned FalseReg = getReg(FalseVal, MBB, IP);
+ // thisMBB:
+ // ...
+ // cmpTY cr0, r1, r2
+ // bCC copy1MBB
+ // b copy0MBB
- if (TrueReg == FalseReg) {
- if (SelectClass == cFP) {
- BuildMI(*MBB, IP, PPC32::FMR, 1, DestReg).addReg(TrueReg);
- } else {
- BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(TrueReg).addReg(TrueReg);
- }
-
- if (SelectClass == cLong)
- BuildMI(*MBB, IP, PPC32::OR, 2, DestReg+1).addReg(TrueReg+1)
- .addReg(TrueReg+1);
- return;
- }
+ MachineBasicBlock *thisMBB = BB;
+ const BasicBlock *LLVM_BB = BB->getBasicBlock();
+ ilist<MachineBasicBlock>::iterator It = BB;
+ ++It;
- unsigned CondReg = getReg(Cond, MBB, IP);
- unsigned numZeros = makeAnotherReg(Type::IntTy);
- unsigned falseHi = makeAnotherReg(Type::IntTy);
- unsigned falseAll = makeAnotherReg(Type::IntTy);
- unsigned trueAll = makeAnotherReg(Type::IntTy);
- unsigned Temp1 = makeAnotherReg(Type::IntTy);
- unsigned Temp2 = makeAnotherReg(Type::IntTy);
-
- BuildMI(*MBB, IP, PPC32::CNTLZW, 1, numZeros).addReg(CondReg);
- BuildMI(*MBB, IP, PPC32::RLWINM, 4, falseHi).addReg(numZeros).addImm(26)
- .addImm(0).addImm(0);
- BuildMI(*MBB, IP, PPC32::SRAWI, 2, falseAll).addReg(falseHi).addImm(31);
- BuildMI(*MBB, IP, PPC32::NOR, 2, trueAll).addReg(falseAll).addReg(falseAll);
- BuildMI(*MBB, IP, PPC32::AND, 2, Temp1).addReg(TrueReg).addReg(trueAll);
- BuildMI(*MBB, IP, PPC32::AND, 2, Temp2).addReg(FalseReg).addReg(falseAll);
- BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(Temp1).addReg(Temp2);
-
- if (SelectClass == cLong) {
- unsigned Temp3 = makeAnotherReg(Type::IntTy);
- unsigned Temp4 = makeAnotherReg(Type::IntTy);
- BuildMI(*MBB, IP, PPC32::AND, 2, Temp3).addReg(TrueReg+1).addReg(trueAll);
- BuildMI(*MBB, IP, PPC32::AND, 2, Temp4).addReg(FalseReg+1).addReg(falseAll);
- BuildMI(*MBB, IP, PPC32::OR, 2, DestReg+1).addReg(Temp3).addReg(Temp4);
- }
-
+ // FIXME: we wouldn't need copy0MBB (we could fold it into thisMBB)
+ // if we could insert other, non-terminator instructions after the
+ // bCC. But MBB->getFirstTerminator() can't understand this.
+ MachineBasicBlock *copy1MBB = new MachineBasicBlock(LLVM_BB);
+ F->getBasicBlockList().insert(It, copy1MBB);
+ BuildMI(BB, Opcode, 2).addReg(PPC::CR0).addMBB(copy1MBB);
+ MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
+ F->getBasicBlockList().insert(It, copy0MBB);
+ BuildMI(BB, PPC::B, 1).addMBB(copy0MBB);
+ MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
+ F->getBasicBlockList().insert(It, sinkMBB);
+ // Update machine-CFG edges
+ BB->addSuccessor(copy1MBB);
+ BB->addSuccessor(copy0MBB);
+
+ // copy1MBB:
+ // %TrueValue = ...
+ // b sinkMBB
+ BB = copy1MBB;
+ unsigned TrueValue = getReg(TrueVal, BB, BB->begin());
+ BuildMI(BB, PPC::B, 1).addMBB(sinkMBB);
+ // Update machine-CFG edges
+ BB->addSuccessor(sinkMBB);
+
+ // copy0MBB:
+ // %FalseValue = ...
+ // fallthrough
+ BB = copy0MBB;
+ unsigned FalseValue = getReg(FalseVal, BB, BB->begin());
+ // Update machine-CFG edges
+ BB->addSuccessor(sinkMBB);
+
+ // sinkMBB:
+ // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, copy1MBB ]
+ // ...
+ BB = sinkMBB;
+ BuildMI(BB, PPC::PHI, 4, DestReg).addReg(FalseValue)
+ .addMBB(copy0MBB).addReg(TrueValue).addMBB(copy1MBB);
+ // For a register pair representing a long value, define the second reg
+ if (getClassB(TrueVal->getType()) == cLong)
+ BuildMI(BB, PPC::LI, 1, DestReg+1).addImm(0);
return;
}
if (Val) {
if (Constant *C = dyn_cast<Constant>(Val)) {
Val = ConstantExpr::getCast(C, Type::IntTy);
- Ty = Type::IntTy;
+ if (isa<ConstantExpr>(Val)) // Could not fold
+ Val = C;
+ else
+ Ty = Type::IntTy; // Folded!
}
// If this is a simple constant, just emit a load directly to avoid the copy
int TheVal = CI->getRawValue() & 0xFFFFFFFF;
if (TheVal < 32768 && TheVal >= -32768) {
- BuildMI(BB, PPC32::ADDI, 2, targetReg).addReg(PPC32::R0).addImm(TheVal);
+ BuildMI(BB, PPC::LI, 1, targetReg).addSImm(TheVal);
} else {
unsigned TmpReg = makeAnotherReg(Type::IntTy);
- BuildMI(BB, PPC32::ADDIS, 2, TmpReg).addReg(PPC32::R0)
- .addImm(TheVal >> 16);
- BuildMI(BB, PPC32::ORI, 2, targetReg).addReg(TmpReg)
+ BuildMI(BB, PPC::LIS, 1, TmpReg).addSImm(TheVal >> 16);
+ BuildMI(BB, PPC::ORI, 2, targetReg).addReg(TmpReg)
.addImm(TheVal & 0xFFFF);
}
return;
// Make sure we have the register number for this value...
unsigned Reg = Val ? getReg(Val) : VR.Reg;
-
switch (getClassB(Ty)) {
case cByte:
// Extend value into target register (8->32)
if (isUnsigned)
- BuildMI(BB, PPC32::RLWINM, 4, targetReg).addReg(Reg).addZImm(0)
+ BuildMI(BB, PPC::RLWINM, 4, targetReg).addReg(Reg).addZImm(0)
.addZImm(24).addZImm(31);
else
- BuildMI(BB, PPC32::EXTSB, 1, targetReg).addReg(Reg);
+ BuildMI(BB, PPC::EXTSB, 1, targetReg).addReg(Reg);
break;
case cShort:
// Extend value into target register (16->32)
if (isUnsigned)
- BuildMI(BB, PPC32::RLWINM, 4, targetReg).addReg(Reg).addZImm(0)
+ BuildMI(BB, PPC::RLWINM, 4, targetReg).addReg(Reg).addZImm(0)
.addZImm(16).addZImm(31);
else
- BuildMI(BB, PPC32::EXTSH, 1, targetReg).addReg(Reg);
+ BuildMI(BB, PPC::EXTSH, 1, targetReg).addReg(Reg);
break;
case cInt:
// Move value into target register (32->32)
- BuildMI(BB, PPC32::OR, 2, targetReg).addReg(Reg).addReg(Reg);
+ BuildMI(BB, PPC::OR, 2, targetReg).addReg(Reg).addReg(Reg);
break;
default:
assert(0 && "Unpromotable operand class in promote32");
case cByte: // integral return values: extend or move into r3 and return
case cShort:
case cInt:
- promote32(PPC32::R3, ValueRecord(RetVal));
+ promote32(PPC::R3, ValueRecord(RetVal));
break;
- case cFP: { // Floats & Doubles: Return in f1
+ case cFP32:
+ case cFP64: { // Floats & Doubles: Return in f1
unsigned RetReg = getReg(RetVal);
- BuildMI(BB, PPC32::FMR, 1, PPC32::F1).addReg(RetReg);
+ BuildMI(BB, PPC::FMR, 1, PPC::F1).addReg(RetReg);
break;
}
case cLong: {
unsigned RetReg = getReg(RetVal);
- BuildMI(BB, PPC32::OR, 2, PPC32::R3).addReg(RetReg).addReg(RetReg);
- BuildMI(BB, PPC32::OR, 2, PPC32::R4).addReg(RetReg+1).addReg(RetReg+1);
+ BuildMI(BB, PPC::OR, 2, PPC::R3).addReg(RetReg).addReg(RetReg);
+ BuildMI(BB, PPC::OR, 2, PPC::R4).addReg(RetReg+1).addReg(RetReg+1);
break;
}
default:
visitInstruction(I);
}
}
- BuildMI(BB, PPC32::BLR, 1).addImm(0);
+ BuildMI(BB, PPC::BLR, 1).addImm(0);
}
// getBlockAfter - Return the basic block which occurs lexically after the
///
void ISel::visitBranchInst(BranchInst &BI) {
// Update machine-CFG edges
- BB->addSuccessor (MBBMap[BI.getSuccessor(0)]);
+ BB->addSuccessor(MBBMap[BI.getSuccessor(0)]);
if (BI.isConditional())
- BB->addSuccessor (MBBMap[BI.getSuccessor(1)]);
+ BB->addSuccessor(MBBMap[BI.getSuccessor(1)]);
BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
if (!BI.isConditional()) { // Unconditional branch?
if (BI.getSuccessor(0) != NextBB)
- BuildMI(BB, PPC32::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
+ BuildMI(BB, PPC::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
return;
}
// Nope, cannot fold setcc into this branch. Emit a branch on a condition
// computed some other way...
unsigned condReg = getReg(BI.getCondition());
- BuildMI(BB, PPC32::CMPLI, 3, PPC32::CR1).addImm(0).addReg(condReg)
+ BuildMI(BB, PPC::CMPLI, 3, PPC::CR0).addImm(0).addReg(condReg)
.addImm(0);
if (BI.getSuccessor(1) == NextBB) {
if (BI.getSuccessor(0) != NextBB)
- BuildMI(BB, PPC32::BNE, 2).addReg(PPC32::CR1)
- .addMBB(MBBMap[BI.getSuccessor(0)]);
+ BuildMI(BB, PPC::COND_BRANCH, 3).addReg(PPC::CR0).addImm(PPC::BNE)
+ .addMBB(MBBMap[BI.getSuccessor(0)])
+ .addMBB(MBBMap[BI.getSuccessor(1)]);
} else {
- BuildMI(BB, PPC32::BNE, 2).addReg(PPC32::CR1)
- .addMBB(MBBMap[BI.getSuccessor(1)]);
-
+ BuildMI(BB, PPC::COND_BRANCH, 3).addReg(PPC::CR0).addImm(PPC::BEQ)
+ .addMBB(MBBMap[BI.getSuccessor(1)])
+ .addMBB(MBBMap[BI.getSuccessor(0)]);
if (BI.getSuccessor(0) != NextBB)
- BuildMI(BB, PPC32::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
+ BuildMI(BB, PPC::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
}
return;
}
OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
if (BI.getSuccessor(0) != NextBB) {
- BuildMI(BB, Opcode, 2).addReg(PPC32::CR0)
- .addMBB(MBBMap[BI.getSuccessor(0)]);
+ BuildMI(BB, PPC::COND_BRANCH, 3).addReg(PPC::CR0).addImm(Opcode)
+ .addMBB(MBBMap[BI.getSuccessor(0)])
+ .addMBB(MBBMap[BI.getSuccessor(1)]);
if (BI.getSuccessor(1) != NextBB)
- BuildMI(BB, PPC32::B, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
+ BuildMI(BB, PPC::B, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
} else {
// Change to the inverse condition...
if (BI.getSuccessor(1) != NextBB) {
- Opcode = invertPPCBranchOpcode(Opcode);
- BuildMI(BB, Opcode, 2).addReg(PPC32::CR0)
- .addMBB(MBBMap[BI.getSuccessor(1)]);
+ Opcode = PowerPCInstrInfo::invertPPCBranchOpcode(Opcode);
+ BuildMI(BB, PPC::COND_BRANCH, 3).addReg(PPC::CR0).addImm(Opcode)
+ .addMBB(MBBMap[BI.getSuccessor(1)])
+ .addMBB(MBBMap[BI.getSuccessor(0)]);
}
}
}
-static Constant* minUConstantForValue(uint64_t val) {
- if (val <= 1)
- return ConstantBool::get(val);
- else if (ConstantUInt::isValueValidForType(Type::UShortTy, val))
- return ConstantUInt::get(Type::UShortTy, val);
- else if (ConstantUInt::isValueValidForType(Type::UIntTy, val))
- return ConstantUInt::get(Type::UIntTy, val);
- else if (ConstantUInt::isValueValidForType(Type::ULongTy, val))
- return ConstantUInt::get(Type::ULongTy, val);
-
- std::cerr << "Value: " << val << " not accepted for any integral type!\n";
- abort();
-}
-
/// doCall - This emits an abstract call instruction, setting up the arguments
/// and the return value as appropriate. For the actual function call itself,
/// it inserts the specified CallMI instruction into the stream.
/// <http://developer.apple.com/documentation/DeveloperTools/Conceptual/MachORuntime/2rt_powerpc_abi/chapter_9_section_5.html>
void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
const std::vector<ValueRecord> &Args, bool isVarArg) {
- // Count how many bytes are to be pushed on the stack...
- unsigned NumBytes = 0;
+ // Count how many bytes are to be pushed on the stack, including the linkage
+ // area, and parameter passing area.
+ unsigned NumBytes = 24;
+ unsigned ArgOffset = 24;
if (!Args.empty()) {
for (unsigned i = 0, e = Args.size(); i != e; ++i)
NumBytes += 4; break;
case cLong:
NumBytes += 8; break;
- case cFP:
- NumBytes += Args[i].Ty == Type::FloatTy ? 4 : 8;
+ case cFP32:
+ NumBytes += 4; break;
+ case cFP64:
+ NumBytes += 8; break;
break;
default: assert(0 && "Unknown class!");
}
+ // Just to be safe, we'll always reserve the full 32 bytes worth of
+ // argument passing space in case any called code gets funky on us.
+ if (NumBytes < 24 + 32) NumBytes = 24 + 32;
+
// Adjust the stack pointer for the new arguments...
- BuildMI(BB, PPC32::ADJCALLSTACKDOWN, 1).addImm(NumBytes);
+ // These functions are automatically eliminated by the prolog/epilog pass
+ BuildMI(BB, PPC::ADJCALLSTACKDOWN, 1).addImm(NumBytes);
// Arguments go on the stack in reverse order, as specified by the ABI.
- unsigned ArgOffset = 0;
+ // Offset to the paramater area on the stack is 24.
int GPR_remaining = 8, FPR_remaining = 13;
unsigned GPR_idx = 0, FPR_idx = 0;
static const unsigned GPR[] = {
- PPC32::R3, PPC32::R4, PPC32::R5, PPC32::R6,
- PPC32::R7, PPC32::R8, PPC32::R9, PPC32::R10,
+ PPC::R3, PPC::R4, PPC::R5, PPC::R6,
+ PPC::R7, PPC::R8, PPC::R9, PPC::R10,
};
static const unsigned FPR[] = {
- PPC32::F1, PPC32::F2, PPC32::F3, PPC32::F4, PPC32::F5, PPC32::F6,
- PPC32::F7, PPC32::F8, PPC32::F9, PPC32::F10, PPC32::F11, PPC32::F12,
- PPC32::F13
+ PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6,
+ PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12,
+ PPC::F13
};
for (unsigned i = 0, e = Args.size(); i != e; ++i) {
// Reg or stack?
if (GPR_remaining > 0) {
- BuildMI(BB, PPC32::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
+ BuildMI(BB, PPC::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
.addReg(ArgReg);
- } else {
- BuildMI(BB, PPC32::STW, 3).addReg(ArgReg).addImm(ArgOffset)
- .addReg(PPC32::R1);
+ CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
+ }
+ if (GPR_remaining <= 0 || isVarArg) {
+ BuildMI(BB, PPC::STW, 3).addReg(ArgReg).addSImm(ArgOffset)
+ .addReg(PPC::R1);
}
break;
case cInt:
// Reg or stack?
if (GPR_remaining > 0) {
- BuildMI(BB, PPC32::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
+ BuildMI(BB, PPC::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
.addReg(ArgReg);
- } else {
- BuildMI(BB, PPC32::STW, 3).addReg(ArgReg).addImm(ArgOffset)
- .addReg(PPC32::R1);
+ CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
+ }
+ if (GPR_remaining <= 0 || isVarArg) {
+ BuildMI(BB, PPC::STW, 3).addReg(ArgReg).addSImm(ArgOffset)
+ .addReg(PPC::R1);
}
break;
case cLong:
ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
- // Reg or stack?
+ // Reg or stack? Note that PPC calling conventions state that long args
+ // are passed rN = hi, rN+1 = lo, opposite of LLVM.
if (GPR_remaining > 1) {
- BuildMI(BB, PPC32::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
+ BuildMI(BB, PPC::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
.addReg(ArgReg);
- BuildMI(BB, PPC32::OR, 2, GPR[GPR_idx + 1]).addReg(ArgReg+1)
+ BuildMI(BB, PPC::OR, 2, GPR[GPR_idx+1]).addReg(ArgReg+1)
.addReg(ArgReg+1);
- } else {
- BuildMI(BB, PPC32::STW, 3).addReg(ArgReg).addImm(ArgOffset)
- .addReg(PPC32::R1);
- BuildMI(BB, PPC32::STW, 3).addReg(ArgReg+1).addImm(ArgOffset+4)
- .addReg(PPC32::R1);
+ CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
+ CallMI->addRegOperand(GPR[GPR_idx+1], MachineOperand::Use);
+ }
+ if (GPR_remaining <= 1 || isVarArg) {
+ BuildMI(BB, PPC::STW, 3).addReg(ArgReg).addSImm(ArgOffset)
+ .addReg(PPC::R1);
+ BuildMI(BB, PPC::STW, 3).addReg(ArgReg+1).addSImm(ArgOffset+4)
+ .addReg(PPC::R1);
}
ArgOffset += 4; // 8 byte entry, not 4.
GPR_remaining -= 1; // uses up 2 GPRs
GPR_idx += 1;
break;
- case cFP:
+ case cFP32:
ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
- if (Args[i].Ty == Type::FloatTy) {
- assert(!isVarArg && "Cannot pass floats to vararg functions!");
- // Reg or stack?
- if (FPR_remaining > 0) {
- BuildMI(BB, PPC32::FMR, 1, FPR[FPR_idx]).addReg(ArgReg);
- FPR_remaining--;
- FPR_idx++;
- } else {
- BuildMI(BB, PPC32::STFS, 3).addReg(ArgReg).addImm(ArgOffset)
- .addReg(PPC32::R1);
+ // Reg or stack?
+ if (FPR_remaining > 0) {
+ BuildMI(BB, PPC::FMR, 1, FPR[FPR_idx]).addReg(ArgReg);
+ CallMI->addRegOperand(FPR[FPR_idx], MachineOperand::Use);
+ FPR_remaining--;
+ FPR_idx++;
+
+ // If this is a vararg function, and there are GPRs left, also
+ // pass the float in an int. Otherwise, put it on the stack.
+ if (isVarArg) {
+ BuildMI(BB, PPC::STFS, 3).addReg(ArgReg).addSImm(ArgOffset)
+ .addReg(PPC::R1);
+ if (GPR_remaining > 0) {
+ BuildMI(BB, PPC::LWZ, 2, GPR[GPR_idx])
+ .addSImm(ArgOffset).addReg(PPC::R1);
+ CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
+ }
}
} else {
- assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!");
- // Reg or stack?
- if (FPR_remaining > 0) {
- BuildMI(BB, PPC32::FMR, 1, FPR[FPR_idx]).addReg(ArgReg);
- FPR_remaining--;
- FPR_idx++;
- // For vararg functions, must pass doubles via int regs as well
- if (isVarArg) {
- Value *Val = Args[i].Val;
- if (ConstantFP *CFP = dyn_cast<ConstantFP>(Val)) {
- union DU {
- double FVal;
- struct {
- uint32_t hi32;
- uint32_t lo32;
- } UVal;
- } U;
- U.FVal = CFP->getValue();
- if (GPR_remaining > 0) {
- Constant *hi32 = minUConstantForValue(U.UVal.hi32);
- copyConstantToRegister(BB, BB->end(), hi32, GPR[GPR_idx]);
- }
- if (GPR_remaining > 1) {
- Constant *lo32 = minUConstantForValue(U.UVal.lo32);
- copyConstantToRegister(BB, BB->end(), lo32, GPR[GPR_idx+1]);
- }
- } else {
- // Since this is not a constant, we must load it into int regs
- // via memory
- BuildMI(BB, PPC32::STFD, 3).addReg(ArgReg).addImm(ArgOffset)
- .addReg(PPC32::R1);
- if (GPR_remaining > 0)
- BuildMI(BB, PPC32::LWZ, 2, GPR[GPR_idx]).addImm(ArgOffset)
- .addReg(PPC32::R1);
- if (GPR_remaining > 1)
- BuildMI(BB, PPC32::LWZ, 2, GPR[GPR_idx+1])
- .addImm(ArgOffset+4).addReg(PPC32::R1);
- }
+ BuildMI(BB, PPC::STFS, 3).addReg(ArgReg).addSImm(ArgOffset)
+ .addReg(PPC::R1);
+ }
+ break;
+ case cFP64:
+ ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
+ // Reg or stack?
+ if (FPR_remaining > 0) {
+ BuildMI(BB, PPC::FMR, 1, FPR[FPR_idx]).addReg(ArgReg);
+ CallMI->addRegOperand(FPR[FPR_idx], MachineOperand::Use);
+ FPR_remaining--;
+ FPR_idx++;
+ // For vararg functions, must pass doubles via int regs as well
+ if (isVarArg) {
+ BuildMI(BB, PPC::STFD, 3).addReg(ArgReg).addSImm(ArgOffset)
+ .addReg(PPC::R1);
+
+ // Doubles can be split across reg + stack for varargs
+ if (GPR_remaining > 0) {
+ BuildMI(BB, PPC::LWZ, 2, GPR[GPR_idx]).addSImm(ArgOffset)
+ .addReg(PPC::R1);
+ CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
+ }
+ if (GPR_remaining > 1) {
+ BuildMI(BB, PPC::LWZ, 2, GPR[GPR_idx+1])
+ .addSImm(ArgOffset+4).addReg(PPC::R1);
+ CallMI->addRegOperand(GPR[GPR_idx+1], MachineOperand::Use);
}
- } else {
- BuildMI(BB, PPC32::STFD, 3).addReg(ArgReg).addImm(ArgOffset)
- .addReg(PPC32::R1);
}
-
- ArgOffset += 4; // 8 byte entry, not 4.
- GPR_remaining--; // uses up 2 GPRs
- GPR_idx++;
+ } else {
+ BuildMI(BB, PPC::STFD, 3).addReg(ArgReg).addSImm(ArgOffset)
+ .addReg(PPC::R1);
}
+ // Doubles use 8 bytes, and 2 GPRs worth of param space
+ ArgOffset += 4;
+ GPR_remaining--;
+ GPR_idx++;
break;
-
+
default: assert(0 && "Unknown class!");
}
ArgOffset += 4;
GPR_idx++;
}
} else {
- BuildMI(BB, PPC32::ADJCALLSTACKDOWN, 1).addImm(0);
+ BuildMI(BB, PPC::ADJCALLSTACKDOWN, 1).addImm(0);
}
+ BuildMI(BB, PPC::IMPLICIT_DEF, 0, PPC::LR);
BB->push_back(CallMI);
- BuildMI(BB, PPC32::ADJCALLSTACKUP, 1).addImm(NumBytes);
+
+ // These functions are automatically eliminated by the prolog/epilog pass
+ BuildMI(BB, PPC::ADJCALLSTACKUP, 1).addImm(NumBytes);
// If there is a return value, scavenge the result from the location the call
// leaves it in...
case cShort:
case cInt:
// Integral results are in r3
- BuildMI(BB, PPC32::OR, 2, Ret.Reg).addReg(PPC32::R3).addReg(PPC32::R3);
+ BuildMI(BB, PPC::OR, 2, Ret.Reg).addReg(PPC::R3).addReg(PPC::R3);
break;
- case cFP: // Floating-point return values live in f1
- BuildMI(BB, PPC32::FMR, 1, Ret.Reg).addReg(PPC32::F1);
+ case cFP32: // Floating-point return values live in f1
+ case cFP64:
+ BuildMI(BB, PPC::FMR, 1, Ret.Reg).addReg(PPC::F1);
break;
case cLong: // Long values are in r3:r4
- BuildMI(BB, PPC32::OR, 2, Ret.Reg).addReg(PPC32::R3).addReg(PPC32::R3);
- BuildMI(BB, PPC32::OR, 2, Ret.Reg+1).addReg(PPC32::R4).addReg(PPC32::R4);
+ BuildMI(BB, PPC::OR, 2, Ret.Reg).addReg(PPC::R3).addReg(PPC::R3);
+ BuildMI(BB, PPC::OR, 2, Ret.Reg+1).addReg(PPC::R4).addReg(PPC::R4);
break;
default: assert(0 && "Unknown class!");
}
visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here
return;
}
-
// Emit a CALL instruction with PC-relative displacement.
- TheCall = BuildMI(PPC32::CALLpcrel, 1).addGlobalAddress(F, true);
+ TheCall = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(F, true);
+ // Add it to the set of functions called to be used by the Printer
+ TM.CalledFunctions.insert(F);
} else { // Emit an indirect call through the CTR
unsigned Reg = getReg(CI.getCalledValue());
- BuildMI(PPC32::MTSPR, 2).addZImm(9).addReg(Reg);
- TheCall = BuildMI(PPC32::CALLindirect, 1).addZImm(20).addZImm(0);
+ BuildMI(BB, PPC::MTCTR, 1).addReg(Reg);
+ TheCall = BuildMI(PPC::CALLindirect, 2).addZImm(20).addZImm(0);
}
std::vector<ValueRecord> Args;
case Intrinsic::vaend:
case Intrinsic::returnaddress:
case Intrinsic::frameaddress:
- // FIXME: should lower this ourselves
+ // FIXME: should lower these ourselves
// case Intrinsic::isunordered:
+ // case Intrinsic::memcpy: -> doCall(). system memcpy almost
+ // guaranteed to be faster than anything we generate ourselves
// We directly implement these intrinsics
break;
case Intrinsic::readio: {
// On PPC, memory operations are in-order. Lower this intrinsic
// into a volatile store.
Instruction *Before = CI->getPrev();
- StoreInst *LI = new StoreInst(CI->getOperand(1),
+ StoreInst *SI = new StoreInst(CI->getOperand(1),
CI->getOperand(2), true, CI);
- CI->replaceAllUsesWith(LI);
+ CI->replaceAllUsesWith(SI);
BB->getInstList().erase(CI);
break;
}
case Intrinsic::vastart:
// Get the address of the first vararg value...
TmpReg1 = getReg(CI);
- addFrameReference(BuildMI(BB, PPC32::ADDI, 2, TmpReg1), VarArgsFrameIndex);
+ addFrameReference(BuildMI(BB, PPC::ADDI, 2, TmpReg1), VarArgsFrameIndex,
+ 0, false);
return;
case Intrinsic::vacopy:
TmpReg1 = getReg(CI);
TmpReg2 = getReg(CI.getOperand(1));
- BuildMI(BB, PPC32::OR, 2, TmpReg1).addReg(TmpReg2).addReg(TmpReg2);
+ BuildMI(BB, PPC::OR, 2, TmpReg1).addReg(TmpReg2).addReg(TmpReg2);
return;
case Intrinsic::vaend: return;
case Intrinsic::returnaddress:
- case Intrinsic::frameaddress:
TmpReg1 = getReg(CI);
if (cast<Constant>(CI.getOperand(1))->isNullValue()) {
- if (ID == Intrinsic::returnaddress) {
- // Just load the return address
- addFrameReference(BuildMI(BB, PPC32::LWZ, 2, TmpReg1),
- ReturnAddressIndex);
- } else {
- addFrameReference(BuildMI(BB, PPC32::ADDI, 2, TmpReg1),
- ReturnAddressIndex, -4, false);
- }
+ MachineFrameInfo *MFI = F->getFrameInfo();
+ unsigned NumBytes = MFI->getStackSize();
+
+ BuildMI(BB, PPC::LWZ, 2, TmpReg1).addSImm(NumBytes+8)
+ .addReg(PPC::R1);
} else {
// Values other than zero are not implemented yet.
- BuildMI(BB, PPC32::ADDI, 2, TmpReg1).addReg(PPC32::R0).addImm(0);
+ BuildMI(BB, PPC::LI, 1, TmpReg1).addSImm(0);
}
return;
+ case Intrinsic::frameaddress:
+ TmpReg1 = getReg(CI);
+ if (cast<Constant>(CI.getOperand(1))->isNullValue()) {
+ BuildMI(BB, PPC::OR, 2, TmpReg1).addReg(PPC::R1).addReg(PPC::R1);
+ } else {
+ // Values other than zero are not implemented yet.
+ BuildMI(BB, PPC::LI, 1, TmpReg1).addSImm(0);
+ }
+ return;
+
#if 0
// This may be useful for supporting isunordered
case Intrinsic::isnan:
TmpReg1 = getReg(CI.getOperand(1));
emitUCOM(BB, BB->end(), TmpReg1, TmpReg1);
TmpReg2 = makeAnotherReg(Type::IntTy);
- BuildMI(BB, PPC32::MFCR, TmpReg2);
+ BuildMI(BB, PPC::MFCR, TmpReg2);
TmpReg3 = getReg(CI);
- BuildMI(BB, PPC32::RLWINM, 4, TmpReg3).addReg(TmpReg2).addImm(4).addImm(31).addImm(31);
+ BuildMI(BB, PPC::RLWINM, 4, TmpReg3).addReg(TmpReg2).addImm(4).addImm(31).addImm(31);
return;
#endif
Value *Op0, Value *Op1,
unsigned OperatorClass, unsigned DestReg) {
+ static const unsigned OpcodeTab[][4] = {
+ { PPC::FADDS, PPC::FSUBS, PPC::FMULS, PPC::FDIVS }, // Float
+ { PPC::FADD, PPC::FSUB, PPC::FMUL, PPC::FDIV }, // Double
+ };
+
// Special case: op Reg, <const fp>
if (ConstantFP *Op1C = dyn_cast<ConstantFP>(Op1)) {
// Create a constant pool entry for this constant.
MachineConstantPool *CP = F->getConstantPool();
unsigned CPI = CP->getConstantPoolIndex(Op1C);
const Type *Ty = Op1->getType();
-
- static const unsigned OpcodeTab[][4] = {
- { PPC32::FADDS, PPC32::FSUBS, PPC32::FMULS, PPC32::FDIVS }, // Float
- { PPC32::FADD, PPC32::FSUB, PPC32::FMUL, PPC32::FDIV }, // Double
- };
-
assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
- unsigned TempReg = makeAnotherReg(Ty);
- unsigned LoadOpcode = (Ty == Type::FloatTy) ? PPC32::LFS : PPC32::LFD;
- addConstantPoolReference(BuildMI(*BB, IP, LoadOpcode, 2, TempReg), CPI);
- unsigned Opcode = OpcodeTab[Ty != Type::FloatTy][OperatorClass];
- unsigned Op0r = getReg(Op0, BB, IP);
- BuildMI(*BB, IP, Opcode, DestReg).addReg(Op0r).addReg(TempReg);
+ unsigned Opcode = OpcodeTab[1][OperatorClass];
+ unsigned Op1Reg = getReg(Op1C, BB, IP);
+ unsigned Op0Reg = getReg(Op0, BB, IP);
+ if (Ty == Type::DoubleTy) {
+ BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg);
+ } else {
+ unsigned TmpReg = makeAnotherReg(Type::DoubleTy);
+ BuildMI(*BB, IP, Opcode, 2, TmpReg).addReg(Op0Reg).addReg(Op1Reg);
+ BuildMI(*BB, IP, PPC::FRSP, 1, DestReg).addReg(TmpReg);
+ }
return;
}
// Special case: R1 = op <const fp>, R2
- if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op0))
- if (CFP->isExactlyValue(-0.0) && OperatorClass == 1) {
+ if (ConstantFP *Op0C = dyn_cast<ConstantFP>(Op0))
+ if (Op0C->isExactlyValue(-0.0) && OperatorClass == 1) {
// -0.0 - X === -X
unsigned op1Reg = getReg(Op1, BB, IP);
- BuildMI(*BB, IP, PPC32::FNEG, 1, DestReg).addReg(op1Reg);
+ BuildMI(*BB, IP, PPC::FNEG, 1, DestReg).addReg(op1Reg);
return;
} else {
- // R1 = op CST, R2 --> R1 = opr R2, CST
-
// Create a constant pool entry for this constant.
MachineConstantPool *CP = F->getConstantPool();
- unsigned CPI = CP->getConstantPoolIndex(CFP);
- const Type *Ty = CFP->getType();
-
- static const unsigned OpcodeTab[][4] = {
- { PPC32::FADDS, PPC32::FSUBS, PPC32::FMULS, PPC32::FDIVS }, // Float
- { PPC32::FADD, PPC32::FSUB, PPC32::FMUL, PPC32::FDIV }, // Double
- };
-
+ unsigned CPI = CP->getConstantPoolIndex(Op0C);
+ const Type *Ty = Op0C->getType();
assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
- unsigned TempReg = makeAnotherReg(Ty);
- unsigned LoadOpcode = (Ty == Type::FloatTy) ? PPC32::LFS : PPC32::LFD;
- addConstantPoolReference(BuildMI(*BB, IP, LoadOpcode, 2, TempReg), CPI);
- unsigned Opcode = OpcodeTab[Ty != Type::FloatTy][OperatorClass];
- unsigned Op1r = getReg(Op1, BB, IP);
- BuildMI(*BB, IP, Opcode, DestReg).addReg(TempReg).addReg(Op1r);
+ unsigned Opcode = OpcodeTab[1][OperatorClass];
+ unsigned Op0Reg = getReg(Op0C, BB, IP);
+ unsigned Op1Reg = getReg(Op1, BB, IP);
+ if (Ty == Type::DoubleTy) {
+ BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg);
+ } else {
+ unsigned TmpReg = makeAnotherReg(Type::DoubleTy);
+ BuildMI(*BB, IP, Opcode, 2, TmpReg).addReg(Op0Reg).addReg(Op1Reg);
+ BuildMI(*BB, IP, PPC::FRSP, 1, DestReg).addReg(TmpReg);
+ }
return;
}
- // General case.
- static const unsigned OpcodeTab[] = {
- PPC32::FADD, PPC32::FSUB, PPC32::FMUL, PPC32::FDIV
- };
-
- unsigned Opcode = OpcodeTab[OperatorClass];
+ unsigned Opcode = OpcodeTab[Op0->getType() != Type::FloatTy][OperatorClass];
+ //unsigned Opcode = OpcodeTab[OperatorClass];
unsigned Op0r = getReg(Op0, BB, IP);
unsigned Op1r = getReg(Op1, BB, IP);
BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
// Arithmetic and Bitwise operators
static const unsigned OpcodeTab[] = {
- PPC32::ADD, PPC32::SUB, PPC32::AND, PPC32::OR, PPC32::XOR
+ PPC::ADD, PPC::SUB, PPC::AND, PPC::OR, PPC::XOR
+ };
+ static const unsigned ImmOpcodeTab[] = {
+ PPC::ADDI, PPC::SUBI, PPC::ANDIo, PPC::ORI, PPC::XORI
};
+ static const unsigned RImmOpcodeTab[] = {
+ PPC::ADDI, PPC::SUBFIC, PPC::ANDIo, PPC::ORI, PPC::XORI
+ };
+
// Otherwise, code generate the full operation with a constant.
static const unsigned BottomTab[] = {
- PPC32::ADDC, PPC32::SUBC, PPC32::AND, PPC32::OR, PPC32::XOR
+ PPC::ADDC, PPC::SUBC, PPC::AND, PPC::OR, PPC::XOR
};
static const unsigned TopTab[] = {
- PPC32::ADDE, PPC32::SUBFE, PPC32::AND, PPC32::OR, PPC32::XOR
+ PPC::ADDE, PPC::SUBFE, PPC::AND, PPC::OR, PPC::XOR
};
- if (Class == cFP) {
+ if (Class == cFP32 || Class == cFP64) {
assert(OperatorClass < 2 && "No logical ops for FP!");
emitBinaryFPOperation(MBB, IP, Op0, Op1, OperatorClass, DestReg);
return;
unsigned Op0Reg = getReg(RHS, MBB, IP), Op1Reg = getReg(LHS, MBB, IP);
unsigned TmpReg = makeAnotherReg(Type::IntTy);
emitUCOM(MBB, IP, Op0Reg, Op1Reg);
- BuildMI(*MBB, IP, PPC32::MFCR, TmpReg);
- BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(TmpReg).addImm(4)
+ BuildMI(*MBB, IP, PPC::MFCR, TmpReg);
+ BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(TmpReg).addImm(4)
.addImm(31).addImm(31);
return;
}
}
- // sub 0, X -> neg X
- if (ConstantInt *CI = dyn_cast<ConstantInt>(Op0))
- if (OperatorClass == 1 && CI->isNullValue()) {
- unsigned op1Reg = getReg(Op1, MBB, IP);
- BuildMI(*MBB, IP, PPC32::NEG, 1, DestReg).addReg(op1Reg);
-
+ // Special case: op <const int>, Reg
+ if (ConstantInt *CI = dyn_cast<ConstantInt>(Op0)) {
+ // sub 0, X -> subfic
+ if (OperatorClass == 1 && canUseAsImmediateForOpcode(CI, 0)) {
+ unsigned Op1r = getReg(Op1, MBB, IP);
+ int imm = CI->getRawValue() & 0xFFFF;
+
if (Class == cLong) {
- unsigned zeroes = makeAnotherReg(Type::IntTy);
- unsigned overflow = makeAnotherReg(Type::IntTy);
- unsigned T = makeAnotherReg(Type::IntTy);
- BuildMI(*MBB, IP, PPC32::CNTLZW, 1, zeroes).addReg(op1Reg);
- BuildMI(*MBB, IP, PPC32::RLWINM, 4, overflow).addReg(zeroes).addImm(27)
- .addImm(5).addImm(31);
- BuildMI(*MBB, IP, PPC32::ADD, 2, T).addReg(op1Reg+1).addReg(overflow);
- BuildMI(*MBB, IP, PPC32::NEG, 1, DestReg+1).addReg(T);
+ BuildMI(*MBB, IP, PPC::SUBFIC, 2, DestReg+1).addReg(Op1r+1)
+ .addSImm(imm);
+ BuildMI(*MBB, IP, PPC::SUBFZE, 1, DestReg).addReg(Op1r);
+ } else {
+ BuildMI(*MBB, IP, PPC::SUBFIC, 2, DestReg).addReg(Op1r).addSImm(imm);
}
return;
}
+
+ // If it is easy to do, swap the operands and emit an immediate op
+ if (Class != cLong && OperatorClass != 1 &&
+ canUseAsImmediateForOpcode(CI, OperatorClass)) {
+ unsigned Op1r = getReg(Op1, MBB, IP);
+ int imm = CI->getRawValue() & 0xFFFF;
+
+ if (OperatorClass < 2)
+ BuildMI(*MBB, IP, RImmOpcodeTab[OperatorClass], 2, DestReg).addReg(Op1r)
+ .addSImm(imm);
+ else
+ BuildMI(*MBB, IP, RImmOpcodeTab[OperatorClass], 2, DestReg).addReg(Op1r)
+ .addZImm(imm);
+ return;
+ }
+ }
// Special case: op Reg, <const int>
if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
// xor X, -1 -> not X
if (OperatorClass == 4 && Op1C->isAllOnesValue()) {
- BuildMI(*MBB, IP, PPC32::NOR, 2, DestReg).addReg(Op0r).addReg(Op0r);
- if (Class == cLong) // Invert the top part too
- BuildMI(*MBB, IP, PPC32::NOR, 2, DestReg+1).addReg(Op0r+1)
+ BuildMI(*MBB, IP, PPC::NOR, 2, DestReg).addReg(Op0r).addReg(Op0r);
+ if (Class == cLong) // Invert the low part too
+ BuildMI(*MBB, IP, PPC::NOR, 2, DestReg+1).addReg(Op0r+1)
.addReg(Op0r+1);
return;
}
-
- unsigned Opcode = OpcodeTab[OperatorClass];
- unsigned Op1r = getReg(Op1, MBB, IP);
-
- if (Class != cLong) {
- BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
- return;
- }
- // If the constant is zero in the low 32-bits, just copy the low part
- // across and apply the normal 32-bit operation to the high parts. There
- // will be no carry or borrow into the top.
- if (cast<ConstantInt>(Op1C)->getRawValue() == 0) {
- if (OperatorClass != 2) // All but and...
- BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(Op0r).addReg(Op0r);
- else
- BuildMI(*MBB, IP, PPC32::ADDI, 2, DestReg).addReg(PPC32::R0).addImm(0);
- BuildMI(*MBB, IP, Opcode, 2, DestReg+1).addReg(Op0r+1).addReg(Op1r+1);
- return;
- }
-
- // If this is a long value and the high or low bits have a special
- // property, emit some special cases.
- unsigned Op1h = cast<ConstantInt>(Op1C)->getRawValue() >> 32LL;
-
- // If this is a logical operation and the top 32-bits are zero, just
- // operate on the lower 32.
- if (Op1h == 0 && OperatorClass > 1) {
- BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
- if (OperatorClass != 2) // All but and
- BuildMI(*MBB, IP, PPC32::OR, 2,DestReg+1).addReg(Op0r+1).addReg(Op0r+1);
- else
- BuildMI(*MBB, IP, PPC32::ADDI, 2,DestReg+1).addReg(PPC32::R0).addImm(0);
+ if (Class != cLong) {
+ if (canUseAsImmediateForOpcode(Op1C, OperatorClass)) {
+ int immediate = Op1C->getRawValue() & 0xFFFF;
+
+ if (OperatorClass < 2)
+ BuildMI(*MBB, IP, ImmOpcodeTab[OperatorClass], 2,DestReg).addReg(Op0r)
+ .addSImm(immediate);
+ else
+ BuildMI(*MBB, IP, ImmOpcodeTab[OperatorClass], 2,DestReg).addReg(Op0r)
+ .addZImm(immediate);
+ } else {
+ unsigned Op1r = getReg(Op1, MBB, IP);
+ BuildMI(*MBB, IP, OpcodeTab[OperatorClass], 2, DestReg).addReg(Op0r)
+ .addReg(Op1r);
+ }
return;
}
-
- // TODO: We could handle lots of other special cases here, such as AND'ing
- // with 0xFFFFFFFF00000000 -> noop, etc.
-
- BuildMI(*MBB, IP, BottomTab[OperatorClass], 2, DestReg).addReg(Op0r)
- .addImm(Op1r);
- BuildMI(*MBB, IP, TopTab[OperatorClass], 2, DestReg+1).addReg(Op0r+1)
- .addImm(Op1r+1);
+
+ unsigned Op1r = getReg(Op1, MBB, IP);
+
+ BuildMI(*MBB, IP, BottomTab[OperatorClass], 2, DestReg+1).addReg(Op0r+1)
+ .addReg(Op1r+1);
+ BuildMI(*MBB, IP, TopTab[OperatorClass], 2, DestReg).addReg(Op0r)
+ .addReg(Op1r);
return;
}
-
+
+ // We couldn't generate an immediate variant of the op, load both halves into
+ // registers and emit the appropriate opcode.
unsigned Op0r = getReg(Op0, MBB, IP);
unsigned Op1r = getReg(Op1, MBB, IP);
unsigned Opcode = OpcodeTab[OperatorClass];
BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
} else {
- BuildMI(*MBB, IP, BottomTab[OperatorClass], 2, DestReg).addReg(Op0r)
- .addImm(Op1r);
- BuildMI(*MBB, IP, TopTab[OperatorClass], 2, DestReg+1).addReg(Op0r+1)
- .addImm(Op1r+1);
+ BuildMI(*MBB, IP, BottomTab[OperatorClass], 2, DestReg+1).addReg(Op0r+1)
+ .addReg(Op1r+1);
+ BuildMI(*MBB, IP, TopTab[OperatorClass], 2, DestReg).addReg(Op0r)
+ .addReg(Op1r);
}
return;
}
-/// doMultiply - Emit appropriate instructions to multiply together the
-/// registers op0Reg and op1Reg, and put the result in DestReg. The type of the
-/// result should be given as DestTy.
-///
-void ISel::doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
- unsigned DestReg, const Type *DestTy,
- unsigned op0Reg, unsigned op1Reg) {
- unsigned Class = getClass(DestTy);
- switch (Class) {
- case cLong:
- BuildMI(*MBB, MBBI, PPC32::MULHW, 2, DestReg+1).addReg(op0Reg+1)
- .addReg(op1Reg+1);
- case cInt:
- case cShort:
- case cByte:
- BuildMI(*MBB, MBBI, PPC32::MULLW, 2, DestReg).addReg(op0Reg).addReg(op1Reg);
- return;
- default:
- assert(0 && "doMultiply cannot operate on unknown type!");
- }
-}
-
// ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
// returns zero when the input is not exactly a power of two.
static unsigned ExactLog2(unsigned Val) {
Val >>= 1;
++Count;
}
- return Count+1;
+ return Count;
}
-
-/// doMultiplyConst - This function is specialized to efficiently codegen an 8,
-/// 16, or 32-bit integer multiply by a constant.
+/// doMultiply - Emit appropriate instructions to multiply together the
+/// Values Op0 and Op1, and put the result in DestReg.
///
+void ISel::doMultiply(MachineBasicBlock *MBB,
+ MachineBasicBlock::iterator IP,
+ unsigned DestReg, Value *Op0, Value *Op1) {
+ unsigned Class0 = getClass(Op0->getType());
+ unsigned Class1 = getClass(Op1->getType());
+
+ unsigned Op0r = getReg(Op0, MBB, IP);
+ unsigned Op1r = getReg(Op1, MBB, IP);
+
+ // 64 x 64 -> 64
+ if (Class0 == cLong && Class1 == cLong) {
+ unsigned Tmp1 = makeAnotherReg(Type::IntTy);
+ unsigned Tmp2 = makeAnotherReg(Type::IntTy);
+ unsigned Tmp3 = makeAnotherReg(Type::IntTy);
+ unsigned Tmp4 = makeAnotherReg(Type::IntTy);
+ BuildMI(*MBB, IP, PPC::MULHWU, 2, Tmp1).addReg(Op0r+1).addReg(Op1r+1);
+ BuildMI(*MBB, IP, PPC::MULLW, 2, DestReg+1).addReg(Op0r+1).addReg(Op1r+1);
+ BuildMI(*MBB, IP, PPC::MULLW, 2, Tmp2).addReg(Op0r+1).addReg(Op1r);
+ BuildMI(*MBB, IP, PPC::ADD, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
+ BuildMI(*MBB, IP, PPC::MULLW, 2, Tmp4).addReg(Op0r).addReg(Op1r+1);
+ BuildMI(*MBB, IP, PPC::ADD, 2, DestReg).addReg(Tmp3).addReg(Tmp4);
+ return;
+ }
+
+ // 64 x 32 or less, promote 32 to 64 and do a 64 x 64
+ if (Class0 == cLong && Class1 <= cInt) {
+ unsigned Tmp0 = makeAnotherReg(Type::IntTy);
+ unsigned Tmp1 = makeAnotherReg(Type::IntTy);
+ unsigned Tmp2 = makeAnotherReg(Type::IntTy);
+ unsigned Tmp3 = makeAnotherReg(Type::IntTy);
+ unsigned Tmp4 = makeAnotherReg(Type::IntTy);
+ if (Op1->getType()->isSigned())
+ BuildMI(*MBB, IP, PPC::SRAWI, 2, Tmp0).addReg(Op1r).addImm(31);
+ else
+ BuildMI(*MBB, IP, PPC::LI, 2, Tmp0).addSImm(0);
+ BuildMI(*MBB, IP, PPC::MULHWU, 2, Tmp1).addReg(Op0r+1).addReg(Op1r);
+ BuildMI(*MBB, IP, PPC::MULLW, 2, DestReg+1).addReg(Op0r+1).addReg(Op1r);
+ BuildMI(*MBB, IP, PPC::MULLW, 2, Tmp2).addReg(Op0r+1).addReg(Tmp0);
+ BuildMI(*MBB, IP, PPC::ADD, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
+ BuildMI(*MBB, IP, PPC::MULLW, 2, Tmp4).addReg(Op0r).addReg(Op1r);
+ BuildMI(*MBB, IP, PPC::ADD, 2, DestReg).addReg(Tmp3).addReg(Tmp4);
+ return;
+ }
+
+ // 32 x 32 -> 32
+ if (Class0 <= cInt && Class1 <= cInt) {
+ BuildMI(*MBB, IP, PPC::MULLW, 2, DestReg).addReg(Op0r).addReg(Op1r);
+ return;
+ }
+
+ assert(0 && "doMultiply cannot operate on unknown type!");
+}
+
+/// doMultiplyConst - This method will multiply the value in Op0 by the
+/// value of the ContantInt *CI
void ISel::doMultiplyConst(MachineBasicBlock *MBB,
MachineBasicBlock::iterator IP,
- unsigned DestReg, const Type *DestTy,
- unsigned op0Reg, unsigned ConstRHS) {
- unsigned Class = getClass(DestTy);
- // Handle special cases here.
- switch (ConstRHS) {
- case 0:
- BuildMI(*MBB, IP, PPC32::ADDI, 2, DestReg).addReg(PPC32::R0).addImm(0);
+ unsigned DestReg, Value *Op0, ConstantInt *CI) {
+ unsigned Class = getClass(Op0->getType());
+
+ // Mul op0, 0 ==> 0
+ if (CI->isNullValue()) {
+ BuildMI(*MBB, IP, PPC::LI, 1, DestReg).addSImm(0);
+ if (Class == cLong)
+ BuildMI(*MBB, IP, PPC::LI, 1, DestReg+1).addSImm(0);
return;
- case 1:
- BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(op0Reg).addReg(op0Reg);
- return;
- case 2:
- BuildMI(*MBB, IP, PPC32::ADD, 2,DestReg).addReg(op0Reg).addReg(op0Reg);
+ }
+
+ // Mul op0, 1 ==> op0
+ if (CI->equalsInt(1)) {
+ unsigned Op0r = getReg(Op0, MBB, IP);
+ BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(Op0r).addReg(Op0r);
+ if (Class == cLong)
+ BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(Op0r+1).addReg(Op0r+1);
return;
}
// If the element size is exactly a power of 2, use a shift to get it.
- if (unsigned Shift = ExactLog2(ConstRHS)) {
- switch (Class) {
- default: assert(0 && "Unknown class for this function!");
- case cByte:
- case cShort:
- case cInt:
- BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(op0Reg)
- .addImm(Shift-1).addImm(0).addImm(31-Shift-1);
+ if (unsigned Shift = ExactLog2(CI->getRawValue())) {
+ ConstantUInt *ShiftCI = ConstantUInt::get(Type::UByteTy, Shift);
+ emitShiftOperation(MBB, IP, Op0, ShiftCI, true, Op0->getType(), DestReg);
+ return;
+ }
+
+ // If 32 bits or less and immediate is in right range, emit mul by immediate
+ if (Class == cByte || Class == cShort || Class == cInt) {
+ if (canUseAsImmediateForOpcode(CI, 0)) {
+ unsigned Op0r = getReg(Op0, MBB, IP);
+ unsigned imm = CI->getRawValue() & 0xFFFF;
+ BuildMI(*MBB, IP, PPC::MULLI, 2, DestReg).addReg(Op0r).addSImm(imm);
return;
}
}
- // Most general case, emit a normal multiply...
- unsigned TmpReg1 = makeAnotherReg(Type::IntTy);
- unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
- BuildMI(*MBB, IP, PPC32::ADDIS, 2, TmpReg1).addReg(PPC32::R0)
- .addImm(ConstRHS >> 16);
- BuildMI(*MBB, IP, PPC32::ORI, 2, TmpReg2).addReg(TmpReg1).addImm(ConstRHS);
-
- // Emit a MUL to multiply the register holding the index by
- // elementSize, putting the result in OffsetReg.
- doMultiply(MBB, IP, DestReg, DestTy, op0Reg, TmpReg2);
+ doMultiply(MBB, IP, DestReg, Op0, CI);
}
void ISel::visitMul(BinaryOperator &I) {
void ISel::emitMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
Value *Op0, Value *Op1, unsigned DestReg) {
- MachineBasicBlock &BB = *MBB;
TypeClass Class = getClass(Op0->getType());
- // Simple scalar multiply?
- unsigned Op0Reg = getReg(Op0, &BB, IP);
switch (Class) {
case cByte:
case cShort:
case cInt:
+ case cLong:
if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
- unsigned Val = (unsigned)CI->getRawValue(); // Isn't a 64-bit constant
- doMultiplyConst(&BB, IP, DestReg, Op0->getType(), Op0Reg, Val);
+ doMultiplyConst(MBB, IP, DestReg, Op0, CI);
} else {
- unsigned Op1Reg = getReg(Op1, &BB, IP);
- doMultiply(&BB, IP, DestReg, Op1->getType(), Op0Reg, Op1Reg);
+ doMultiply(MBB, IP, DestReg, Op0, Op1);
}
return;
- case cFP:
+ case cFP32:
+ case cFP64:
emitBinaryFPOperation(MBB, IP, Op0, Op1, 2, DestReg);
return;
- case cLong:
break;
}
-
- // Long value. We have to do things the hard way...
- if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
- unsigned CLow = CI->getRawValue();
- unsigned CHi = CI->getRawValue() >> 32;
-
- if (CLow == 0) {
- // If the low part of the constant is all zeros, things are simple.
- BuildMI(BB, IP, PPC32::ADDI, 2, DestReg).addReg(PPC32::R0).addImm(0);
- doMultiplyConst(&BB, IP, DestReg+1, Type::UIntTy, Op0Reg, CHi);
- return;
- }
-
- // Multiply the two low parts
- unsigned OverflowReg = 0;
- if (CLow == 1) {
- BuildMI(BB, IP, PPC32::OR, 2, DestReg).addReg(Op0Reg).addReg(Op0Reg);
- } else {
- unsigned TmpRegL = makeAnotherReg(Type::UIntTy);
- unsigned Op1RegL = makeAnotherReg(Type::UIntTy);
- OverflowReg = makeAnotherReg(Type::UIntTy);
- BuildMI(BB, IP, PPC32::ADDIS, 2, TmpRegL).addReg(PPC32::R0)
- .addImm(CLow >> 16);
- BuildMI(BB, IP, PPC32::ORI, 2, Op1RegL).addReg(TmpRegL).addImm(CLow);
- BuildMI(BB, IP, PPC32::MULLW, 2, DestReg).addReg(Op0Reg).addReg(Op1RegL);
- BuildMI(BB, IP, PPC32::MULHW, 2, OverflowReg).addReg(Op0Reg)
- .addReg(Op1RegL);
- }
-
- unsigned AHBLReg = makeAnotherReg(Type::UIntTy);
- doMultiplyConst(&BB, IP, AHBLReg, Type::UIntTy, Op0Reg+1, CLow);
-
- unsigned AHBLplusOverflowReg;
- if (OverflowReg) {
- AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
- BuildMI(BB, IP, PPC32::ADD, 2,
- AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
- } else {
- AHBLplusOverflowReg = AHBLReg;
- }
-
- if (CHi == 0) {
- BuildMI(BB, IP, PPC32::OR, 2, DestReg+1).addReg(AHBLplusOverflowReg)
- .addReg(AHBLplusOverflowReg);
- } else {
- unsigned ALBHReg = makeAnotherReg(Type::UIntTy);
- doMultiplyConst(&BB, IP, ALBHReg, Type::UIntTy, Op0Reg, CHi);
-
- BuildMI(BB, IP, PPC32::ADD, 2,
- DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
- }
- return;
- }
-
- // General 64x64 multiply
-
- unsigned Op1Reg = getReg(Op1, &BB, IP);
-
- // Multiply the two low parts...
- BuildMI(BB, IP, PPC32::MULLW, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg);
-
- unsigned OverflowReg = makeAnotherReg(Type::UIntTy);
- BuildMI(BB, IP, PPC32::MULHW, 2, OverflowReg).addReg(Op0Reg).addReg(Op1Reg);
-
- unsigned AHBLReg = makeAnotherReg(Type::UIntTy);
- BuildMI(BB, IP, PPC32::MULLW, 2, AHBLReg).addReg(Op0Reg+1).addReg(Op1Reg);
-
- unsigned AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
- BuildMI(BB, IP, PPC32::ADD, 2, AHBLplusOverflowReg).addReg(AHBLReg)
- .addReg(OverflowReg);
-
- unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
- BuildMI(BB, IP, PPC32::MULLW, 2, ALBHReg).addReg(Op0Reg).addReg(Op1Reg+1);
-
- BuildMI(BB, IP, PPC32::ADD, 2,
- DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
}
const Type *Ty = Op0->getType();
unsigned Class = getClass(Ty);
switch (Class) {
- case cFP: // Floating point divide
+ case cFP32:
if (isDiv) {
+ // Floating point divide...
emitBinaryFPOperation(BB, IP, Op0, Op1, 3, ResultReg);
return;
- } else { // Floating point remainder...
+ } else {
+ // Floating point remainder via fmodf(float x, float y);
unsigned Op0Reg = getReg(Op0, BB, IP);
unsigned Op1Reg = getReg(Op1, BB, IP);
MachineInstr *TheCall =
- BuildMI(PPC32::CALLpcrel, 1).addGlobalAddress(fmodFn, true);
+ BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(fmodfFn, true);
+ std::vector<ValueRecord> Args;
+ Args.push_back(ValueRecord(Op0Reg, Type::FloatTy));
+ Args.push_back(ValueRecord(Op1Reg, Type::FloatTy));
+ doCall(ValueRecord(ResultReg, Type::FloatTy), TheCall, Args, false);
+ TM.CalledFunctions.insert(fmodfFn);
+ }
+ return;
+ case cFP64:
+ if (isDiv) {
+ // Floating point divide...
+ emitBinaryFPOperation(BB, IP, Op0, Op1, 3, ResultReg);
+ return;
+ } else {
+ // Floating point remainder via fmod(double x, double y);
+ unsigned Op0Reg = getReg(Op0, BB, IP);
+ unsigned Op1Reg = getReg(Op1, BB, IP);
+ MachineInstr *TheCall =
+ BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(fmodFn, true);
std::vector<ValueRecord> Args;
Args.push_back(ValueRecord(Op0Reg, Type::DoubleTy));
Args.push_back(ValueRecord(Op1Reg, Type::DoubleTy));
doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args, false);
+ TM.CalledFunctions.insert(fmodFn);
}
return;
case cLong: {
- static Function* const Funcs[] =
+ static Function* const Funcs[] =
{ __moddi3Fn, __divdi3Fn, __umoddi3Fn, __udivdi3Fn };
unsigned Op0Reg = getReg(Op0, BB, IP);
unsigned Op1Reg = getReg(Op1, BB, IP);
unsigned NameIdx = Ty->isUnsigned()*2 + isDiv;
MachineInstr *TheCall =
- BuildMI(PPC32::CALLpcrel, 1).addGlobalAddress(Funcs[NameIdx], true);
+ BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(Funcs[NameIdx], true);
std::vector<ValueRecord> Args;
Args.push_back(ValueRecord(Op0Reg, Type::LongTy));
Args.push_back(ValueRecord(Op1Reg, Type::LongTy));
doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args, false);
+ TM.CalledFunctions.insert(Funcs[NameIdx]);
return;
}
case cByte: case cShort: case cInt:
if (V == 1) { // X /s 1 => X
unsigned Op0Reg = getReg(Op0, BB, IP);
- BuildMI(*BB, IP, PPC32::OR, 2, ResultReg).addReg(Op0Reg).addReg(Op0Reg);
+ BuildMI(*BB, IP, PPC::OR, 2, ResultReg).addReg(Op0Reg).addReg(Op0Reg);
return;
}
if (V == -1) { // X /s -1 => -X
unsigned Op0Reg = getReg(Op0, BB, IP);
- BuildMI(*BB, IP, PPC32::NEG, 1, ResultReg).addReg(Op0Reg);
+ BuildMI(*BB, IP, PPC::NEG, 1, ResultReg).addReg(Op0Reg);
return;
}
- bool isNeg = false;
- if (V < 0) { // Not a positive power of 2?
- V = -V;
- isNeg = true; // Maybe it's a negative power of 2.
- }
- if (unsigned Log = ExactLog2(V)) {
- --Log;
+ unsigned log2V = ExactLog2(V);
+ if (log2V != 0 && Ty->isSigned()) {
unsigned Op0Reg = getReg(Op0, BB, IP);
unsigned TmpReg = makeAnotherReg(Op0->getType());
- if (Log != 1)
- BuildMI(*BB, IP, PPC32::SRAWI,2, TmpReg).addReg(Op0Reg).addImm(Log-1);
- else
- BuildMI(*BB, IP, PPC32::OR, 2, TmpReg).addReg(Op0Reg).addReg(Op0Reg);
-
- unsigned TmpReg2 = makeAnotherReg(Op0->getType());
- BuildMI(*BB, IP, PPC32::RLWINM, 4, TmpReg2).addReg(TmpReg).addImm(Log)
- .addImm(32-Log).addImm(31);
-
- unsigned TmpReg3 = makeAnotherReg(Op0->getType());
- BuildMI(*BB, IP, PPC32::ADD, 2, TmpReg3).addReg(Op0Reg).addReg(TmpReg2);
-
- unsigned TmpReg4 = isNeg ? makeAnotherReg(Op0->getType()) : ResultReg;
- BuildMI(*BB, IP, PPC32::SRAWI, 2, TmpReg4).addReg(Op0Reg).addImm(Log);
-
- if (isNeg)
- BuildMI(*BB, IP, PPC32::NEG, 1, ResultReg).addReg(TmpReg4);
+
+ BuildMI(*BB, IP, PPC::SRAWI, 2, TmpReg).addReg(Op0Reg).addImm(log2V);
+ BuildMI(*BB, IP, PPC::ADDZE, 1, ResultReg).addReg(TmpReg);
return;
}
}
unsigned Op0Reg = getReg(Op0, BB, IP);
unsigned Op1Reg = getReg(Op1, BB, IP);
-
+ unsigned Opcode = Ty->isSigned() ? PPC::DIVW : PPC::DIVWU;
+
if (isDiv) {
- if (Ty->isSigned()) {
- BuildMI(*BB, IP, PPC32::DIVW, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
- } else {
- BuildMI(*BB, IP,PPC32::DIVWU, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
- }
+ BuildMI(*BB, IP, Opcode, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
} else { // Remainder
unsigned TmpReg1 = makeAnotherReg(Op0->getType());
unsigned TmpReg2 = makeAnotherReg(Op0->getType());
- if (Ty->isSigned()) {
- BuildMI(*BB, IP, PPC32::DIVW, 2, TmpReg1).addReg(Op0Reg).addReg(Op1Reg);
- } else {
- BuildMI(*BB, IP, PPC32::DIVWU, 2, TmpReg1).addReg(Op0Reg).addReg(Op1Reg);
- }
- BuildMI(*BB, IP, PPC32::MULLW, 2, TmpReg2).addReg(TmpReg1).addReg(Op1Reg);
- BuildMI(*BB, IP, PPC32::SUBF, 2, ResultReg).addReg(TmpReg2).addReg(Op0Reg);
+ BuildMI(*BB, IP, Opcode, 2, TmpReg1).addReg(Op0Reg).addReg(Op1Reg);
+ BuildMI(*BB, IP, PPC::MULLW, 2, TmpReg2).addReg(TmpReg1).addReg(Op1Reg);
+ BuildMI(*BB, IP, PPC::SUBF, 2, ResultReg).addReg(TmpReg2).addReg(Op0Reg);
}
}
/// because the shift amount has to be in CL, not just any old register.
///
void ISel::visitShiftInst(ShiftInst &I) {
- MachineBasicBlock::iterator IP = BB->end ();
- emitShiftOperation(BB, IP, I.getOperand (0), I.getOperand (1),
- I.getOpcode () == Instruction::Shl, I.getType (),
- getReg (I));
+ MachineBasicBlock::iterator IP = BB->end();
+ emitShiftOperation(BB, IP, I.getOperand(0), I.getOperand(1),
+ I.getOpcode() == Instruction::Shl, I.getType(),
+ getReg(I));
}
/// emitShiftOperation - Common code shared between visitShiftInst and
if (Amount < 32) {
if (isLeftShift) {
// FIXME: RLWIMI is a use-and-def of DestReg+1, but that violates SSA
- BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg+1).addReg(SrcReg+1)
+ BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
.addImm(Amount).addImm(0).addImm(31-Amount);
- BuildMI(*MBB, IP, PPC32::RLWIMI, 5).addReg(DestReg+1).addReg(SrcReg)
+ BuildMI(*MBB, IP, PPC::RLWIMI, 5).addReg(DestReg).addReg(SrcReg+1)
.addImm(Amount).addImm(32-Amount).addImm(31);
- BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg)
+ BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg+1).addReg(SrcReg+1)
.addImm(Amount).addImm(0).addImm(31-Amount);
} else {
// FIXME: RLWIMI is a use-and-def of DestReg, but that violates SSA
- BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg)
+ BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg+1).addReg(SrcReg+1)
.addImm(32-Amount).addImm(Amount).addImm(31);
- BuildMI(*MBB, IP, PPC32::RLWIMI, 5).addReg(DestReg).addReg(SrcReg+1)
+ BuildMI(*MBB, IP, PPC::RLWIMI, 5).addReg(DestReg+1).addReg(SrcReg)
.addImm(32-Amount).addImm(0).addImm(Amount-1);
- BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg+1).addReg(SrcReg+1)
+ BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
.addImm(32-Amount).addImm(Amount).addImm(31);
}
} else { // Shifting more than 32 bits
Amount -= 32;
if (isLeftShift) {
if (Amount != 0) {
- BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg+1).addReg(SrcReg)
+ BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg+1)
.addImm(Amount).addImm(0).addImm(31-Amount);
} else {
- BuildMI(*MBB, IP, PPC32::OR, 2, DestReg+1).addReg(SrcReg)
- .addReg(SrcReg);
+ BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg+1)
+ .addReg(SrcReg+1);
}
- BuildMI(*MBB, IP, PPC32::ADDI, 2,DestReg).addReg(PPC32::R0).addImm(0);
+ BuildMI(*MBB, IP, PPC::LI, 1, DestReg+1).addSImm(0);
} else {
if (Amount != 0) {
if (isSigned)
- BuildMI(*MBB, IP, PPC32::SRAWI, 2, DestReg).addReg(SrcReg+1)
+ BuildMI(*MBB, IP, PPC::SRAWI, 2, DestReg+1).addReg(SrcReg)
.addImm(Amount);
else
- BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg+1)
+ BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg+1).addReg(SrcReg)
.addImm(32-Amount).addImm(Amount).addImm(31);
} else {
- BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(SrcReg+1)
- .addReg(SrcReg+1);
+ BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg)
+ .addReg(SrcReg);
}
- BuildMI(*MBB, IP,PPC32::ADDI,2,DestReg+1).addReg(PPC32::R0).addImm(0);
+ BuildMI(*MBB, IP,PPC::LI, 1, DestReg).addSImm(0);
}
}
} else {
unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
if (isLeftShift) {
- BuildMI(*MBB, IP, PPC32::SUBFIC, 2, TmpReg1).addReg(ShiftAmountReg)
- .addImm(32);
- BuildMI(*MBB, IP, PPC32::SLW, 2, TmpReg2).addReg(SrcReg+1)
+ BuildMI(*MBB, IP, PPC::SUBFIC, 2, TmpReg1).addReg(ShiftAmountReg)
+ .addSImm(32);
+ BuildMI(*MBB, IP, PPC::SLW, 2, TmpReg2).addReg(SrcReg)
.addReg(ShiftAmountReg);
- BuildMI(*MBB, IP, PPC32::SRW, 2,TmpReg3).addReg(SrcReg).addReg(TmpReg1);
- BuildMI(*MBB, IP, PPC32::OR, 2,TmpReg4).addReg(TmpReg2).addReg(TmpReg3);
- BuildMI(*MBB, IP, PPC32::ADDI, 2, TmpReg5).addReg(ShiftAmountReg)
- .addImm(-32);
- BuildMI(*MBB, IP, PPC32::SLW, 2,TmpReg6).addReg(SrcReg).addReg(TmpReg5);
- BuildMI(*MBB, IP, PPC32::OR, 2, DestReg+1).addReg(TmpReg4)
+ BuildMI(*MBB, IP, PPC::SRW, 2, TmpReg3).addReg(SrcReg+1)
+ .addReg(TmpReg1);
+ BuildMI(*MBB, IP, PPC::OR, 2,TmpReg4).addReg(TmpReg2).addReg(TmpReg3);
+ BuildMI(*MBB, IP, PPC::ADDI, 2, TmpReg5).addReg(ShiftAmountReg)
+ .addSImm(-32);
+ BuildMI(*MBB, IP, PPC::SLW, 2, TmpReg6).addReg(SrcReg+1)
+ .addReg(TmpReg5);
+ BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(TmpReg4)
.addReg(TmpReg6);
- BuildMI(*MBB, IP, PPC32::SLW, 2, DestReg).addReg(SrcReg)
+ BuildMI(*MBB, IP, PPC::SLW, 2, DestReg+1).addReg(SrcReg+1)
.addReg(ShiftAmountReg);
} else {
if (isSigned) {
// FIXME: Unimplemented
// Page C-3 of the PowerPC 32bit Programming Environments Manual
- std::cerr << "Unimplemented: signed right shift\n";
+ std::cerr << "ERROR: Unimplemented: signed right shift of long\n";
abort();
} else {
- BuildMI(*MBB, IP, PPC32::SUBFIC, 2, TmpReg1).addReg(ShiftAmountReg)
- .addImm(32);
- BuildMI(*MBB, IP, PPC32::SRW, 2, TmpReg2).addReg(SrcReg)
+ BuildMI(*MBB, IP, PPC::SUBFIC, 2, TmpReg1).addReg(ShiftAmountReg)
+ .addSImm(32);
+ BuildMI(*MBB, IP, PPC::SRW, 2, TmpReg2).addReg(SrcReg+1)
.addReg(ShiftAmountReg);
- BuildMI(*MBB, IP, PPC32::SLW, 2, TmpReg3).addReg(SrcReg+1)
+ BuildMI(*MBB, IP, PPC::SLW, 2, TmpReg3).addReg(SrcReg)
.addReg(TmpReg1);
- BuildMI(*MBB, IP, PPC32::OR, 2, TmpReg4).addReg(TmpReg2)
+ BuildMI(*MBB, IP, PPC::OR, 2, TmpReg4).addReg(TmpReg2)
.addReg(TmpReg3);
- BuildMI(*MBB, IP, PPC32::ADDI, 2, TmpReg5).addReg(ShiftAmountReg)
- .addImm(-32);
- BuildMI(*MBB, IP, PPC32::SRW, 2, TmpReg6).addReg(SrcReg+1)
+ BuildMI(*MBB, IP, PPC::ADDI, 2, TmpReg5).addReg(ShiftAmountReg)
+ .addSImm(-32);
+ BuildMI(*MBB, IP, PPC::SRW, 2, TmpReg6).addReg(SrcReg)
.addReg(TmpReg5);
- BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(TmpReg4)
+ BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(TmpReg4)
.addReg(TmpReg6);
- BuildMI(*MBB, IP, PPC32::SRW, 2, DestReg+1).addReg(SrcReg+1)
+ BuildMI(*MBB, IP, PPC::SRW, 2, DestReg).addReg(SrcReg)
.addReg(ShiftAmountReg);
}
}
unsigned Amount = CUI->getValue();
if (isLeftShift) {
- BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg)
+ BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
.addImm(Amount).addImm(0).addImm(31-Amount);
} else {
if (isSigned) {
- BuildMI(*MBB, IP, PPC32::SRAWI,2,DestReg).addReg(SrcReg).addImm(Amount);
+ BuildMI(*MBB, IP, PPC::SRAWI,2,DestReg).addReg(SrcReg).addImm(Amount);
} else {
- BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg)
+ BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
.addImm(32-Amount).addImm(Amount).addImm(31);
}
}
unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
if (isLeftShift) {
- BuildMI(*MBB, IP, PPC32::SLW, 2, DestReg).addReg(SrcReg)
+ BuildMI(*MBB, IP, PPC::SLW, 2, DestReg).addReg(SrcReg)
.addReg(ShiftAmountReg);
} else {
- BuildMI(*MBB, IP, isSigned ? PPC32::SRAW : PPC32::SRW, 2, DestReg)
+ BuildMI(*MBB, IP, isSigned ? PPC::SRAW : PPC::SRW, 2, DestReg)
.addReg(SrcReg).addReg(ShiftAmountReg);
}
}
}
-/// visitLoadInst - Implement LLVM load instructions
+/// visitLoadInst - Implement LLVM load instructions. Pretty straightforward
+/// mapping of LLVM classes to PPC load instructions, with the exception of
+/// signed byte loads, which need a sign extension following them.
///
void ISel::visitLoadInst(LoadInst &I) {
- static const unsigned Opcodes[] = {
- PPC32::LBZ, PPC32::LHZ, PPC32::LWZ, PPC32::LFS
+ // Immediate opcodes, for reg+imm addressing
+ static const unsigned ImmOpcodes[] = {
+ PPC::LBZ, PPC::LHZ, PPC::LWZ,
+ PPC::LFS, PPC::LFD, PPC::LWZ
+ };
+ // Indexed opcodes, for reg+reg addressing
+ static const unsigned IdxOpcodes[] = {
+ PPC::LBZX, PPC::LHZX, PPC::LWZX,
+ PPC::LFSX, PPC::LFDX, PPC::LWZX
};
- unsigned Class = getClassB(I.getType());
- unsigned Opcode = Opcodes[Class];
- if (I.getType() == Type::DoubleTy) Opcode = PPC32::LFD;
- unsigned DestReg = getReg(I);
+ unsigned Class = getClassB(I.getType());
+ unsigned ImmOpcode = ImmOpcodes[Class];
+ unsigned IdxOpcode = IdxOpcodes[Class];
+ unsigned DestReg = getReg(I);
+ Value *SourceAddr = I.getOperand(0);
+
+ if (Class == cShort && I.getType()->isSigned()) ImmOpcode = PPC::LHA;
+ if (Class == cShort && I.getType()->isSigned()) IdxOpcode = PPC::LHAX;
- if (AllocaInst *AI = dyn_castFixedAlloca(I.getOperand(0))) {
+ if (AllocaInst *AI = dyn_castFixedAlloca(SourceAddr)) {
unsigned FI = getFixedSizedAllocaFI(AI);
if (Class == cLong) {
- addFrameReference(BuildMI(BB, PPC32::LWZ, 2, DestReg), FI);
- addFrameReference(BuildMI(BB, PPC32::LWZ, 2, DestReg+1), FI, 4);
+ addFrameReference(BuildMI(BB, ImmOpcode, 2, DestReg), FI);
+ addFrameReference(BuildMI(BB, ImmOpcode, 2, DestReg+1), FI, 4);
+ } else if (Class == cByte && I.getType()->isSigned()) {
+ unsigned TmpReg = makeAnotherReg(I.getType());
+ addFrameReference(BuildMI(BB, ImmOpcode, 2, TmpReg), FI);
+ BuildMI(BB, PPC::EXTSB, 1, DestReg).addReg(TmpReg);
} else {
- addFrameReference(BuildMI(BB, Opcode, 2, DestReg), FI);
+ addFrameReference(BuildMI(BB, ImmOpcode, 2, DestReg), FI);
}
- } else {
- unsigned SrcAddrReg = getReg(I.getOperand(0));
+ return;
+ }
+
+ // If this load is the only use of the GEP instruction that is its address,
+ // then we can fold the GEP directly into the load instruction.
+ // emitGEPOperation with a second to last arg of 'true' will place the
+ // base register for the GEP into baseReg, and the constant offset from that
+ // into offset. If the offset fits in 16 bits, we can emit a reg+imm store
+ // otherwise, we copy the offset into another reg, and use reg+reg addressing.
+ if (GetElementPtrInst *GEPI = canFoldGEPIntoLoadOrStore(SourceAddr)) {
+ unsigned baseReg = getReg(GEPI);
+ unsigned pendingAdd;
+ ConstantSInt *offset;
+ emitGEPOperation(BB, BB->end(), GEPI->getOperand(0), GEPI->op_begin()+1,
+ GEPI->op_end(), baseReg, true, &offset, &pendingAdd);
+
+ if (pendingAdd == 0 && Class != cLong &&
+ canUseAsImmediateForOpcode(offset, 0)) {
+ if (Class == cByte && I.getType()->isSigned()) {
+ unsigned TmpReg = makeAnotherReg(I.getType());
+ BuildMI(BB, ImmOpcode, 2, TmpReg).addSImm(offset->getValue())
+ .addReg(baseReg);
+ BuildMI(BB, PPC::EXTSB, 1, DestReg).addReg(TmpReg);
+ } else {
+ BuildMI(BB, ImmOpcode, 2, DestReg).addSImm(offset->getValue())
+ .addReg(baseReg);
+ }
+ return;
+ }
+
+ unsigned indexReg = (pendingAdd != 0) ? pendingAdd : getReg(offset);
+
if (Class == cLong) {
- BuildMI(BB, PPC32::LWZ, 2, DestReg).addImm(0).addReg(SrcAddrReg);
- BuildMI(BB, PPC32::LWZ, 2, DestReg+1).addImm(4).addReg(SrcAddrReg);
+ unsigned indexPlus4 = makeAnotherReg(Type::IntTy);
+ BuildMI(BB, PPC::ADDI, 2, indexPlus4).addReg(indexReg).addSImm(4);
+ BuildMI(BB, IdxOpcode, 2, DestReg).addReg(indexReg).addReg(baseReg);
+ BuildMI(BB, IdxOpcode, 2, DestReg+1).addReg(indexPlus4).addReg(baseReg);
+ } else if (Class == cByte && I.getType()->isSigned()) {
+ unsigned TmpReg = makeAnotherReg(I.getType());
+ BuildMI(BB, IdxOpcode, 2, TmpReg).addReg(indexReg).addReg(baseReg);
+ BuildMI(BB, PPC::EXTSB, 1, DestReg).addReg(TmpReg);
} else {
- BuildMI(BB, Opcode, 2, DestReg).addImm(0).addReg(SrcAddrReg);
+ BuildMI(BB, IdxOpcode, 2, DestReg).addReg(indexReg).addReg(baseReg);
}
+ return;
+ }
+
+ // The fallback case, where the load was from a source that could not be
+ // folded into the load instruction.
+ unsigned SrcAddrReg = getReg(SourceAddr);
+
+ if (Class == cLong) {
+ BuildMI(BB, ImmOpcode, 2, DestReg).addSImm(0).addReg(SrcAddrReg);
+ BuildMI(BB, ImmOpcode, 2, DestReg+1).addSImm(4).addReg(SrcAddrReg);
+ } else if (Class == cByte && I.getType()->isSigned()) {
+ unsigned TmpReg = makeAnotherReg(I.getType());
+ BuildMI(BB, ImmOpcode, 2, TmpReg).addSImm(0).addReg(SrcAddrReg);
+ BuildMI(BB, PPC::EXTSB, 1, DestReg).addReg(TmpReg);
+ } else {
+ BuildMI(BB, ImmOpcode, 2, DestReg).addSImm(0).addReg(SrcAddrReg);
}
}
/// visitStoreInst - Implement LLVM store instructions
///
void ISel::visitStoreInst(StoreInst &I) {
- unsigned ValReg = getReg(I.getOperand(0));
- unsigned AddressReg = getReg(I.getOperand(1));
-
- const Type *ValTy = I.getOperand(0)->getType();
- unsigned Class = getClassB(ValTy);
+ // Immediate opcodes, for reg+imm addressing
+ static const unsigned ImmOpcodes[] = {
+ PPC::STB, PPC::STH, PPC::STW,
+ PPC::STFS, PPC::STFD, PPC::STW
+ };
+ // Indexed opcodes, for reg+reg addressing
+ static const unsigned IdxOpcodes[] = {
+ PPC::STBX, PPC::STHX, PPC::STWX,
+ PPC::STFSX, PPC::STFDX, PPC::STWX
+ };
+
+ Value *SourceAddr = I.getOperand(1);
+ const Type *ValTy = I.getOperand(0)->getType();
+ unsigned Class = getClassB(ValTy);
+ unsigned ImmOpcode = ImmOpcodes[Class];
+ unsigned IdxOpcode = IdxOpcodes[Class];
+ unsigned ValReg = getReg(I.getOperand(0));
+
+ // If this store is the only use of the GEP instruction that is its address,
+ // then we can fold the GEP directly into the store instruction.
+ // emitGEPOperation with a second to last arg of 'true' will place the
+ // base register for the GEP into baseReg, and the constant offset from that
+ // into offset. If the offset fits in 16 bits, we can emit a reg+imm store
+ // otherwise, we copy the offset into another reg, and use reg+reg addressing.
+ if (GetElementPtrInst *GEPI = canFoldGEPIntoLoadOrStore(SourceAddr)) {
+ unsigned baseReg = getReg(GEPI);
+ unsigned pendingAdd;
+ ConstantSInt *offset;
+
+ emitGEPOperation(BB, BB->end(), GEPI->getOperand(0), GEPI->op_begin()+1,
+ GEPI->op_end(), baseReg, true, &offset, &pendingAdd);
+ if (0 == pendingAdd && Class != cLong &&
+ canUseAsImmediateForOpcode(offset, 0)) {
+ BuildMI(BB, ImmOpcode, 3).addReg(ValReg).addSImm(offset->getValue())
+ .addReg(baseReg);
+ return;
+ }
+
+ unsigned indexReg = (pendingAdd != 0) ? pendingAdd : getReg(offset);
+
+ if (Class == cLong) {
+ unsigned indexPlus4 = makeAnotherReg(Type::IntTy);
+ BuildMI(BB, PPC::ADDI, 2, indexPlus4).addReg(indexReg).addSImm(4);
+ BuildMI(BB, IdxOpcode, 3).addReg(ValReg).addReg(indexReg).addReg(baseReg);
+ BuildMI(BB, IdxOpcode, 3).addReg(ValReg+1).addReg(indexPlus4)
+ .addReg(baseReg);
+ return;
+ }
+ BuildMI(BB, IdxOpcode, 3).addReg(ValReg).addReg(indexReg).addReg(baseReg);
+ return;
+ }
+
+ // If the store address wasn't the only use of a GEP, we fall back to the
+ // standard path: store the ValReg at the value in AddressReg.
+ unsigned AddressReg = getReg(I.getOperand(1));
if (Class == cLong) {
- BuildMI(BB, PPC32::STW, 3).addReg(ValReg).addImm(0).addReg(AddressReg);
- BuildMI(BB, PPC32::STW, 3).addReg(ValReg+1).addImm(4).addReg(AddressReg);
+ BuildMI(BB, ImmOpcode, 3).addReg(ValReg).addSImm(0).addReg(AddressReg);
+ BuildMI(BB, ImmOpcode, 3).addReg(ValReg+1).addSImm(4).addReg(AddressReg);
return;
}
-
- static const unsigned Opcodes[] = {
- PPC32::STB, PPC32::STH, PPC32::STW, PPC32::STFS
- };
- unsigned Opcode = Opcodes[Class];
- if (ValTy == Type::DoubleTy) Opcode = PPC32::STFD;
- BuildMI(BB, Opcode, 3).addReg(ValReg).addImm(0).addReg(AddressReg);
+ BuildMI(BB, ImmOpcode, 3).addReg(ValReg).addSImm(0).addReg(AddressReg);
}
unsigned SrcClass = getClassB(Op->getType());
unsigned DestClass = getClassB(CI.getType());
- // Noop casts are not emitted: getReg will return the source operand as the
- // register to use for any uses of the noop cast.
- if (DestClass == SrcClass)
- return;
// If this is a cast from a 32-bit integer to a Long type, and the only uses
// of the case are GEP instructions, then the cast does not need to be
/// emitCastOperation - Common code shared between visitCastInst and constant
/// expression cast support.
///
-void ISel::emitCastOperation(MachineBasicBlock *BB,
+void ISel::emitCastOperation(MachineBasicBlock *MBB,
MachineBasicBlock::iterator IP,
Value *Src, const Type *DestTy,
unsigned DestReg) {
const Type *SrcTy = Src->getType();
unsigned SrcClass = getClassB(SrcTy);
unsigned DestClass = getClassB(DestTy);
- unsigned SrcReg = getReg(Src, BB, IP);
+ unsigned SrcReg = getReg(Src, MBB, IP);
// Implement casts to bool by using compare on the operand followed by set if
// not zero on the result.
case cShort:
case cInt: {
unsigned TmpReg = makeAnotherReg(Type::IntTy);
- BuildMI(*BB, IP, PPC32::ADDIC, 2, TmpReg).addReg(SrcReg).addImm(-1);
- BuildMI(*BB, IP, PPC32::SUBFE, 2, DestReg).addReg(TmpReg).addReg(SrcReg);
+ BuildMI(*MBB, IP, PPC::ADDIC, 2, TmpReg).addReg(SrcReg).addSImm(-1);
+ BuildMI(*MBB, IP, PPC::SUBFE, 2, DestReg).addReg(TmpReg).addReg(SrcReg);
break;
}
case cLong: {
unsigned TmpReg = makeAnotherReg(Type::IntTy);
unsigned SrcReg2 = makeAnotherReg(Type::IntTy);
- BuildMI(*BB, IP, PPC32::OR, 2, SrcReg2).addReg(SrcReg).addReg(SrcReg+1);
- BuildMI(*BB, IP, PPC32::ADDIC, 2, TmpReg).addReg(SrcReg2).addImm(-1);
- BuildMI(*BB, IP, PPC32::SUBFE, 2, DestReg).addReg(TmpReg).addReg(SrcReg2);
+ BuildMI(*MBB, IP, PPC::OR, 2, SrcReg2).addReg(SrcReg).addReg(SrcReg+1);
+ BuildMI(*MBB, IP, PPC::ADDIC, 2, TmpReg).addReg(SrcReg2).addSImm(-1);
+ BuildMI(*MBB, IP, PPC::SUBFE, 2, DestReg).addReg(TmpReg)
+ .addReg(SrcReg2);
break;
}
- case cFP:
- // FIXME
- // Load -0.0
- // Compare
- // move to CR1
- // Negate -0.0
- // Compare
- // CROR
- // MFCR
- // Left-align
- // SRA ?
- std::cerr << "Cast fp-to-bool not implemented!";
- abort();
- }
- return;
- }
-
- // Implement casts between values of the same type class (as determined by
- // getClass) by using a register-to-register move.
- if (SrcClass == DestClass) {
- if (SrcClass <= cInt) {
- BuildMI(*BB, IP, PPC32::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
- } else if (SrcClass == cFP && SrcTy == DestTy) {
- BuildMI(*BB, IP, PPC32::FMR, 1, DestReg).addReg(SrcReg);
- } else if (SrcClass == cFP) {
- if (SrcTy == Type::FloatTy) { // float -> double
- assert(DestTy == Type::DoubleTy && "Unknown cFP member!");
- BuildMI(*BB, IP, PPC32::FMR, 1, DestReg).addReg(SrcReg);
- } else { // double -> float
- assert(SrcTy == Type::DoubleTy && DestTy == Type::FloatTy &&
- "Unknown cFP member!");
- BuildMI(*BB, IP, PPC32::FRSP, 1, DestReg).addReg(SrcReg);
- }
- } else if (SrcClass == cLong) {
- BuildMI(*BB, IP, PPC32::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
- BuildMI(*BB, IP, PPC32::OR, 2, DestReg+1).addReg(SrcReg+1)
- .addReg(SrcReg+1);
- } else {
- assert(0 && "Cannot handle this type of cast instruction!");
+ case cFP32:
+ case cFP64:
+ // FSEL perhaps?
+ std::cerr << "ERROR: Cast fp-to-bool not implemented!\n";
abort();
}
return;
}
- // Handle cast of SMALLER int to LARGER int using a move with sign extension
- // or zero extension, depending on whether the source type was signed.
- if (SrcClass <= cInt && (DestClass <= cInt || DestClass == cLong) &&
- SrcClass < DestClass) {
- bool isLong = DestClass == cLong;
- if (isLong) DestClass = cInt;
-
- bool isUnsigned = SrcTy->isUnsigned() || SrcTy == Type::BoolTy;
- if (SrcClass < cInt) {
- if (isUnsigned) {
- unsigned shift = (SrcClass == cByte) ? 24 : 16;
- BuildMI(*BB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg).addZImm(0)
- .addImm(shift).addImm(31);
- } else {
- BuildMI(*BB, IP, (SrcClass == cByte) ? PPC32::EXTSB : PPC32::EXTSH,
- 1, DestReg).addReg(SrcReg);
- }
- } else {
- BuildMI(*BB, IP, PPC32::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
- }
-
- if (isLong) { // Handle upper 32 bits as appropriate...
- if (isUnsigned) // Zero out top bits...
- BuildMI(*BB, IP, PPC32::ADDI, 2, DestReg+1).addReg(PPC32::R0).addImm(0);
- else // Sign extend bottom half...
- BuildMI(*BB, IP, PPC32::SRAWI, 2, DestReg+1).addReg(DestReg).addImm(31);
- }
- return;
- }
-
- // Special case long -> int ...
- if (SrcClass == cLong && DestClass == cInt) {
- BuildMI(*BB, IP, PPC32::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
+ // Handle cast of Float -> Double
+ if (SrcClass == cFP32 && DestClass == cFP64) {
+ BuildMI(*MBB, IP, PPC::FMR, 1, DestReg).addReg(SrcReg);
return;
}
- // Handle cast of LARGER int to SMALLER int with a clear or sign extend
- if ((SrcClass <= cInt || SrcClass == cLong) && DestClass <= cInt
- && SrcClass > DestClass) {
- bool isUnsigned = SrcTy->isUnsigned() || SrcTy == Type::BoolTy;
- if (isUnsigned) {
- unsigned shift = (SrcClass == cByte) ? 24 : 16;
- BuildMI(*BB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg).addZImm(0)
- .addImm(shift).addImm(31);
- } else {
- BuildMI(*BB, IP, (SrcClass == cByte) ? PPC32::EXTSB : PPC32::EXTSH, 1,
- DestReg).addReg(SrcReg);
- }
+ // Handle cast of Double -> Float
+ if (SrcClass == cFP64 && DestClass == cFP32) {
+ BuildMI(*MBB, IP, PPC::FRSP, 1, DestReg).addReg(SrcReg);
return;
}
-
+
// Handle casts from integer to floating point now...
- if (DestClass == cFP) {
+ if (DestClass == cFP32 || DestClass == cFP64) {
// Emit a library call for long to float conversion
if (SrcClass == cLong) {
std::vector<ValueRecord> Args;
Args.push_back(ValueRecord(SrcReg, SrcTy));
- Function *floatFn = (SrcTy==Type::FloatTy) ? __floatdisfFn : __floatdidfFn;
+ Function *floatFn = (DestClass == cFP32) ? __floatdisfFn : __floatdidfFn;
MachineInstr *TheCall =
- BuildMI(PPC32::CALLpcrel, 1).addGlobalAddress(floatFn, true);
+ BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(floatFn, true);
doCall(ValueRecord(DestReg, DestTy), TheCall, Args, false);
+ TM.CalledFunctions.insert(floatFn);
return;
}
-
- unsigned TmpReg = makeAnotherReg(Type::IntTy);
- switch (SrcTy->getTypeID()) {
- case Type::BoolTyID:
- case Type::SByteTyID:
- BuildMI(*BB, IP, PPC32::EXTSB, 1, TmpReg).addReg(SrcReg);
- break;
- case Type::UByteTyID:
- BuildMI(*BB, IP, PPC32::RLWINM, 4, TmpReg).addReg(SrcReg).addZImm(0)
- .addImm(24).addImm(31);
- break;
- case Type::ShortTyID:
- BuildMI(*BB, IP, PPC32::EXTSB, 1, TmpReg).addReg(SrcReg);
- break;
- case Type::UShortTyID:
- BuildMI(*BB, IP, PPC32::RLWINM, 4, TmpReg).addReg(SrcReg).addZImm(0)
- .addImm(16).addImm(31);
- break;
- case Type::IntTyID:
- BuildMI(*BB, IP, PPC32::OR, 2, TmpReg).addReg(SrcReg).addReg(SrcReg);
- break;
- case Type::UIntTyID:
- BuildMI(*BB, IP, PPC32::OR, 2, TmpReg).addReg(SrcReg).addReg(SrcReg);
- break;
- default: // No promotion needed...
- break;
- }
+ // Make sure we're dealing with a full 32 bits
+ unsigned TmpReg = makeAnotherReg(Type::IntTy);
+ promote32(TmpReg, ValueRecord(SrcReg, SrcTy));
+
SrcReg = TmpReg;
// Spill the integer to memory and reload it from there.
unsigned TempF = makeAnotherReg(Type::DoubleTy);
if (!SrcTy->isSigned()) {
- BuildMI(*BB, IP, PPC32::ADDIS, 2, constantHi).addReg(PPC32::R0)
- .addImm(0x4330);
- BuildMI(*BB, IP, PPC32::ADDI, 2, constantLo).addReg(PPC32::R0).addImm(0);
- addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantHi),
+ BuildMI(*BB, IP, PPC::LIS, 1, constantHi).addSImm(0x4330);
+ BuildMI(*BB, IP, PPC::LI, 1, constantLo).addSImm(0);
+ addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(constantHi),
ConstantFrameIndex);
- addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantLo),
+ addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(constantLo),
ConstantFrameIndex, 4);
- addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantHi),
+ addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(constantHi),
ValueFrameIdx);
- addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(SrcReg),
+ addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(SrcReg),
ValueFrameIdx, 4);
- addFrameReference(BuildMI(*BB, IP, PPC32::LFD, 2, ConstF),
+ addFrameReference(BuildMI(*BB, IP, PPC::LFD, 2, ConstF),
ConstantFrameIndex);
- addFrameReference(BuildMI(*BB, IP, PPC32::LFD, 2, TempF), ValueFrameIdx);
- BuildMI(*BB, IP, PPC32::FSUB, 2, DestReg).addReg(TempF).addReg(ConstF);
+ addFrameReference(BuildMI(*BB, IP, PPC::LFD, 2, TempF), ValueFrameIdx);
+ BuildMI(*BB, IP, PPC::FSUB, 2, DestReg).addReg(TempF).addReg(ConstF);
} else {
unsigned TempLo = makeAnotherReg(Type::IntTy);
- BuildMI(*BB, IP, PPC32::ADDIS, 2, constantHi).addReg(PPC32::R0)
- .addImm(0x4330);
- BuildMI(*BB, IP, PPC32::ADDIS, 2, constantLo).addReg(PPC32::R0)
- .addImm(0x8000);
- addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantHi),
+ BuildMI(*BB, IP, PPC::LIS, 1, constantHi).addSImm(0x4330);
+ BuildMI(*BB, IP, PPC::LIS, 1, constantLo).addSImm(0x8000);
+ addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(constantHi),
ConstantFrameIndex);
- addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantLo),
+ addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(constantLo),
ConstantFrameIndex, 4);
- addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantHi),
+ addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(constantHi),
ValueFrameIdx);
- BuildMI(*BB, IP, PPC32::XORIS, 2, TempLo).addReg(SrcReg).addImm(0x8000);
- addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(TempLo),
+ BuildMI(*BB, IP, PPC::XORIS, 2, TempLo).addReg(SrcReg).addImm(0x8000);
+ addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(TempLo),
ValueFrameIdx, 4);
- addFrameReference(BuildMI(*BB, IP, PPC32::LFD, 2, ConstF),
+ addFrameReference(BuildMI(*BB, IP, PPC::LFD, 2, ConstF),
ConstantFrameIndex);
- addFrameReference(BuildMI(*BB, IP, PPC32::LFD, 2, TempF), ValueFrameIdx);
- BuildMI(*BB, IP, PPC32::FSUB, 2, DestReg).addReg(TempF ).addReg(ConstF);
+ addFrameReference(BuildMI(*BB, IP, PPC::LFD, 2, TempF), ValueFrameIdx);
+ BuildMI(*BB, IP, PPC::FSUB, 2, DestReg).addReg(TempF).addReg(ConstF);
}
return;
}
// Handle casts from floating point to integer now...
- if (SrcClass == cFP) {
-
+ if (SrcClass == cFP32 || SrcClass == cFP64) {
+ static Function* const Funcs[] =
+ { __fixsfdiFn, __fixdfdiFn, __fixunssfdiFn, __fixunsdfdiFn };
// emit library call
if (DestClass == cLong) {
+ bool isDouble = SrcClass == cFP64;
+ unsigned nameIndex = 2 * DestTy->isSigned() + isDouble;
std::vector<ValueRecord> Args;
Args.push_back(ValueRecord(SrcReg, SrcTy));
+ Function *floatFn = Funcs[nameIndex];
MachineInstr *TheCall =
- BuildMI(PPC32::CALLpcrel, 1).addGlobalAddress(__fixdfdiFn, true);
+ BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(floatFn, true);
doCall(ValueRecord(DestReg, DestTy), TheCall, Args, false);
+ TM.CalledFunctions.insert(floatFn);
return;
}
int ValueFrameIdx =
- F->getFrameInfo()->CreateStackObject(Type::DoubleTy, TM.getTargetData());
+ F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
- // load into 32 bit value, and then truncate as necessary
- // FIXME: This is wrong for unsigned dest types
- //if (DestTy->isSigned()) {
- unsigned TempReg = makeAnotherReg(Type::DoubleTy);
- BuildMI(*BB, IP, PPC32::FCTIWZ, 1, TempReg).addReg(SrcReg);
- addFrameReference(BuildMI(*BB, IP, PPC32::STFD, 3)
- .addReg(TempReg), ValueFrameIdx);
- addFrameReference(BuildMI(*BB, IP, PPC32::LWZ, 2, DestReg),
- ValueFrameIdx+4);
- //} else {
- //}
-
- // FIXME: Truncate return value
+ if (DestTy->isSigned()) {
+ unsigned TempReg = makeAnotherReg(Type::DoubleTy);
+
+ // Convert to integer in the FP reg and store it to a stack slot
+ BuildMI(*BB, IP, PPC::FCTIWZ, 1, TempReg).addReg(SrcReg);
+ addFrameReference(BuildMI(*BB, IP, PPC::STFD, 3)
+ .addReg(TempReg), ValueFrameIdx);
+
+ // There is no load signed byte opcode, so we must emit a sign extend for
+ // that particular size. Make sure to source the new integer from the
+ // correct offset.
+ if (DestClass == cByte) {
+ unsigned TempReg2 = makeAnotherReg(DestTy);
+ addFrameReference(BuildMI(*BB, IP, PPC::LBZ, 2, TempReg2),
+ ValueFrameIdx, 7);
+ BuildMI(*BB, IP, PPC::EXTSB, 1, DestReg).addReg(TempReg2);
+ } else {
+ int offset = (DestClass == cShort) ? 6 : 4;
+ unsigned LoadOp = (DestClass == cShort) ? PPC::LHA : PPC::LWZ;
+ addFrameReference(BuildMI(*BB, IP, LoadOp, 2, DestReg),
+ ValueFrameIdx, offset);
+ }
+ } else {
+ unsigned Zero = getReg(ConstantFP::get(Type::DoubleTy, 0.0f));
+ double maxInt = (1LL << 32) - 1;
+ unsigned MaxInt = getReg(ConstantFP::get(Type::DoubleTy, maxInt));
+ double border = 1LL << 31;
+ unsigned Border = getReg(ConstantFP::get(Type::DoubleTy, border));
+ unsigned UseZero = makeAnotherReg(Type::DoubleTy);
+ unsigned UseMaxInt = makeAnotherReg(Type::DoubleTy);
+ unsigned UseChoice = makeAnotherReg(Type::DoubleTy);
+ unsigned TmpReg = makeAnotherReg(Type::DoubleTy);
+ unsigned TmpReg2 = makeAnotherReg(Type::DoubleTy);
+ unsigned ConvReg = makeAnotherReg(Type::DoubleTy);
+ unsigned IntTmp = makeAnotherReg(Type::IntTy);
+ unsigned XorReg = makeAnotherReg(Type::IntTy);
+ int FrameIdx =
+ F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
+ // Update machine-CFG edges
+ MachineBasicBlock *XorMBB = new MachineBasicBlock(BB->getBasicBlock());
+ MachineBasicBlock *PhiMBB = new MachineBasicBlock(BB->getBasicBlock());
+ MachineBasicBlock *OldMBB = BB;
+ ilist<MachineBasicBlock>::iterator It = BB; ++It;
+ F->getBasicBlockList().insert(It, XorMBB);
+ F->getBasicBlockList().insert(It, PhiMBB);
+ BB->addSuccessor(XorMBB);
+ BB->addSuccessor(PhiMBB);
+
+ // Convert from floating point to unsigned 32-bit value
+ // Use 0 if incoming value is < 0.0
+ BuildMI(*BB, IP, PPC::FSEL, 3, UseZero).addReg(SrcReg).addReg(SrcReg)
+ .addReg(Zero);
+ // Use 2**32 - 1 if incoming value is >= 2**32
+ BuildMI(*BB, IP, PPC::FSUB, 2, UseMaxInt).addReg(MaxInt).addReg(SrcReg);
+ BuildMI(*BB, IP, PPC::FSEL, 3, UseChoice).addReg(UseMaxInt)
+ .addReg(UseZero).addReg(MaxInt);
+ // Subtract 2**31
+ BuildMI(*BB, IP, PPC::FSUB, 2, TmpReg).addReg(UseChoice).addReg(Border);
+ // Use difference if >= 2**31
+ BuildMI(*BB, IP, PPC::FCMPU, 2, PPC::CR0).addReg(UseChoice)
+ .addReg(Border);
+ BuildMI(*BB, IP, PPC::FSEL, 3, TmpReg2).addReg(TmpReg).addReg(TmpReg)
+ .addReg(UseChoice);
+ // Convert to integer
+ BuildMI(*BB, IP, PPC::FCTIWZ, 1, ConvReg).addReg(TmpReg2);
+ addFrameReference(BuildMI(*BB, IP, PPC::STFD, 3).addReg(ConvReg),
+ FrameIdx);
+ if (DestClass == cByte) {
+ addFrameReference(BuildMI(*BB, IP, PPC::LBZ, 2, DestReg),
+ FrameIdx, 7);
+ } else if (DestClass == cShort) {
+ addFrameReference(BuildMI(*BB, IP, PPC::LHZ, 2, DestReg),
+ FrameIdx, 6);
+ } if (DestClass == cInt) {
+ addFrameReference(BuildMI(*BB, IP, PPC::LWZ, 2, IntTmp),
+ FrameIdx, 4);
+ BuildMI(*BB, IP, PPC::BLT, 2).addReg(PPC::CR0).addMBB(PhiMBB);
+ BuildMI(*BB, IP, PPC::B, 1).addMBB(XorMBB);
+
+ // XorMBB:
+ // add 2**31 if input was >= 2**31
+ BB = XorMBB;
+ BuildMI(BB, PPC::XORIS, 2, XorReg).addReg(IntTmp).addImm(0x8000);
+ XorMBB->addSuccessor(PhiMBB);
+
+ // PhiMBB:
+ // DestReg = phi [ IntTmp, OldMBB ], [ XorReg, XorMBB ]
+ BB = PhiMBB;
+ BuildMI(BB, PPC::PHI, 2, DestReg).addReg(IntTmp).addMBB(OldMBB)
+ .addReg(XorReg).addMBB(XorMBB);
+ }
+ }
+ return;
+ }
+
+ // Check our invariants
+ assert((SrcClass <= cInt || SrcClass == cLong) &&
+ "Unhandled source class for cast operation!");
+ assert((DestClass <= cInt || DestClass == cLong) &&
+ "Unhandled destination class for cast operation!");
+
+ bool sourceUnsigned = SrcTy->isUnsigned() || SrcTy == Type::BoolTy;
+ bool destUnsigned = DestTy->isUnsigned();
+
+ // Unsigned -> Unsigned, clear if larger,
+ if (sourceUnsigned && destUnsigned) {
+ // handle long dest class now to keep switch clean
+ if (DestClass == cLong) {
+ if (SrcClass == cLong) {
+ BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
+ BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg+1)
+ .addReg(SrcReg+1);
+ } else {
+ BuildMI(*MBB, IP, PPC::LI, 1, DestReg).addSImm(0);
+ BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg)
+ .addReg(SrcReg);
+ }
+ return;
+ }
+
+ // handle u{ byte, short, int } x u{ byte, short, int }
+ unsigned clearBits = (SrcClass == cByte || DestClass == cByte) ? 24 : 16;
+ switch (SrcClass) {
+ case cByte:
+ case cShort:
+ if (SrcClass == DestClass)
+ BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
+ else
+ BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
+ .addImm(0).addImm(clearBits).addImm(31);
+ break;
+ case cLong:
+ ++SrcReg;
+ // Fall through
+ case cInt:
+ if (DestClass == cInt)
+ BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
+ else
+ BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
+ .addImm(0).addImm(clearBits).addImm(31);
+ break;
+ }
+ return;
+ }
+
+ // Signed -> Signed
+ if (!sourceUnsigned && !destUnsigned) {
+ // handle long dest class now to keep switch clean
+ if (DestClass == cLong) {
+ if (SrcClass == cLong) {
+ BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
+ BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg+1)
+ .addReg(SrcReg+1);
+ } else {
+ BuildMI(*MBB, IP, PPC::SRAWI, 2, DestReg).addReg(SrcReg).addImm(31);
+ BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg)
+ .addReg(SrcReg);
+ }
+ return;
+ }
+
+ // handle { byte, short, int } x { byte, short, int }
+ switch (SrcClass) {
+ case cByte:
+ if (DestClass == cByte)
+ BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
+ else
+ BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
+ break;
+ case cShort:
+ if (DestClass == cByte)
+ BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
+ else if (DestClass == cShort)
+ BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
+ else
+ BuildMI(*MBB, IP, PPC::EXTSH, 1, DestReg).addReg(SrcReg);
+ break;
+ case cLong:
+ ++SrcReg;
+ // Fall through
+ case cInt:
+ if (DestClass == cByte)
+ BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
+ else if (DestClass == cShort)
+ BuildMI(*MBB, IP, PPC::EXTSH, 1, DestReg).addReg(SrcReg);
+ else
+ BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
+ break;
+ }
+ return;
+ }
+
+ // Unsigned -> Signed
+ if (sourceUnsigned && !destUnsigned) {
+ // handle long dest class now to keep switch clean
+ if (DestClass == cLong) {
+ if (SrcClass == cLong) {
+ BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
+ BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg+1).
+ addReg(SrcReg+1);
+ } else {
+ BuildMI(*MBB, IP, PPC::LI, 1, DestReg).addSImm(0);
+ BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg)
+ .addReg(SrcReg);
+ }
+ return;
+ }
+
+ // handle u{ byte, short, int } -> { byte, short, int }
+ switch (SrcClass) {
+ case cByte:
+ if (DestClass == cByte)
+ // uByte 255 -> signed byte == -1
+ BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
+ else
+ // uByte 255 -> signed short/int == 255
+ BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg).addImm(0)
+ .addImm(24).addImm(31);
+ break;
+ case cShort:
+ if (DestClass == cByte)
+ BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
+ else if (DestClass == cShort)
+ BuildMI(*MBB, IP, PPC::EXTSH, 1, DestReg).addReg(SrcReg);
+ else
+ BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg).addImm(0)
+ .addImm(16).addImm(31);
+ break;
+ case cLong:
+ ++SrcReg;
+ // Fall through
+ case cInt:
+ if (DestClass == cByte)
+ BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
+ else if (DestClass == cShort)
+ BuildMI(*MBB, IP, PPC::EXTSH, 1, DestReg).addReg(SrcReg);
+ else
+ BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
+ break;
+ }
+ return;
+ }
+
+ // Signed -> Unsigned
+ if (!sourceUnsigned && destUnsigned) {
+ // handle long dest class now to keep switch clean
+ if (DestClass == cLong) {
+ if (SrcClass == cLong) {
+ BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
+ BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg+1)
+ .addReg(SrcReg+1);
+ } else {
+ BuildMI(*MBB, IP, PPC::SRAWI, 2, DestReg).addReg(SrcReg).addImm(31);
+ BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg)
+ .addReg(SrcReg);
+ }
+ return;
+ }
+
+ // handle { byte, short, int } -> u{ byte, short, int }
+ unsigned clearBits = (DestClass == cByte) ? 24 : 16;
+ switch (SrcClass) {
+ case cByte:
+ case cShort:
+ if (DestClass == cByte || DestClass == cShort)
+ // sbyte -1 -> ubyte 0x000000FF
+ BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
+ .addImm(0).addImm(clearBits).addImm(31);
+ else
+ // sbyte -1 -> ubyte 0xFFFFFFFF
+ BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
+ break;
+ case cLong:
+ ++SrcReg;
+ // Fall through
+ case cInt:
+ if (DestClass == cInt)
+ BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
+ else
+ BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
+ .addImm(0).addImm(clearBits).addImm(31);
+ break;
+ }
return;
}
// Anything we haven't handled already, we can't (yet) handle at all.
- assert(0 && "Unhandled cast instruction!");
+ std::cerr << "Unhandled cast from " << SrcTy->getDescription()
+ << "to " << DestTy->getDescription() << '\n';
abort();
}
}
// Increment the VAList pointer...
- BuildMI(BB, PPC32::ADDI, 2, DestReg).addReg(VAList).addImm(Size);
+ BuildMI(BB, PPC::ADDI, 2, DestReg).addReg(VAList).addSImm(Size);
}
void ISel::visitVAArgInst(VAArgInst &I) {
case Type::PointerTyID:
case Type::UIntTyID:
case Type::IntTyID:
- BuildMI(BB, PPC32::LWZ, 2, DestReg).addImm(0).addReg(VAList);
+ BuildMI(BB, PPC::LWZ, 2, DestReg).addSImm(0).addReg(VAList);
break;
case Type::ULongTyID:
case Type::LongTyID:
- BuildMI(BB, PPC32::LWZ, 2, DestReg).addImm(0).addReg(VAList);
- BuildMI(BB, PPC32::LWZ, 2, DestReg+1).addImm(4).addReg(VAList);
+ BuildMI(BB, PPC::LWZ, 2, DestReg).addSImm(0).addReg(VAList);
+ BuildMI(BB, PPC::LWZ, 2, DestReg+1).addSImm(4).addReg(VAList);
+ break;
+ case Type::FloatTyID:
+ BuildMI(BB, PPC::LFS, 2, DestReg).addSImm(0).addReg(VAList);
break;
case Type::DoubleTyID:
- BuildMI(BB, PPC32::LFD, 2, DestReg).addImm(0).addReg(VAList);
+ BuildMI(BB, PPC::LFD, 2, DestReg).addSImm(0).addReg(VAList);
break;
}
}
/// visitGetElementPtrInst - instruction-select GEP instructions
///
void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
+ if (canFoldGEPIntoLoadOrStore(&I))
+ return;
+
unsigned outputReg = getReg(I);
emitGEPOperation(BB, BB->end(), I.getOperand(0), I.op_begin()+1, I.op_end(),
- outputReg);
+ outputReg, false, 0, 0);
}
+/// emitGEPOperation - Common code shared between visitGetElementPtrInst and
+/// constant expression GEP support.
+///
void ISel::emitGEPOperation(MachineBasicBlock *MBB,
MachineBasicBlock::iterator IP,
Value *Src, User::op_iterator IdxBegin,
- User::op_iterator IdxEnd, unsigned TargetReg) {
+ User::op_iterator IdxEnd, unsigned TargetReg,
+ bool GEPIsFolded, ConstantSInt **RemainderPtr,
+ unsigned *PendingAddReg) {
const TargetData &TD = TM.getTargetData();
- if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(Src))
- Src = CPR->getValue();
-
- std::vector<Value*> GEPOps;
- GEPOps.resize(IdxEnd-IdxBegin+1);
- GEPOps[0] = Src;
- std::copy(IdxBegin, IdxEnd, GEPOps.begin()+1);
+ const Type *Ty = Src->getType();
+ unsigned basePtrReg = getReg(Src, MBB, IP);
+ int64_t constValue = 0;
- std::vector<const Type*> GEPTypes;
- GEPTypes.assign(gep_type_begin(Src->getType(), IdxBegin, IdxEnd),
- gep_type_end(Src->getType(), IdxBegin, IdxEnd));
-
- // Keep emitting instructions until we consume the entire GEP instruction.
- while (!GEPOps.empty()) {
- if (GEPTypes.empty()) {
- // Load the base pointer into a register.
- unsigned Reg = getReg(Src, MBB, IP);
- BuildMI(*MBB, IP, PPC32::OR, 2, TargetReg).addReg(Reg).addReg(Reg);
- break; // we are now done
- }
- if (const StructType *StTy = dyn_cast<StructType>(GEPTypes.back())) {
- // It's a struct access. CUI is the index into the structure,
- // which names the field. This index must have unsigned type.
- const ConstantUInt *CUI = cast<ConstantUInt>(GEPOps.back());
-
- // Use the TargetData structure to pick out what the layout of the
- // structure is in memory. Since the structure index must be constant, we
- // can get its value and use it to find the right byte offset from the
- // StructLayout class's list of structure member offsets.
- unsigned Disp = TD.getStructLayout(StTy)->MemberOffsets[CUI->getValue()];
- GEPOps.pop_back(); // Consume a GEP operand
- GEPTypes.pop_back();
- unsigned Reg = makeAnotherReg(Type::UIntTy);
- unsigned DispReg = makeAnotherReg(Type::UIntTy);
- BuildMI(*MBB, IP, PPC32::LI, 2, DispReg).addImm(Disp);
- BuildMI(*MBB, IP, PPC32::ADD, 2, TargetReg).addReg(Reg).addReg(DispReg);
- --IP; // Insert the next instruction before this one.
- TargetReg = Reg; // Codegen the rest of the GEP into this
- } else {
- // It's an array or pointer access: [ArraySize x ElementType].
- const SequentialType *SqTy = cast<SequentialType>(GEPTypes.back());
- Value *idx = GEPOps.back();
- GEPOps.pop_back(); // Consume a GEP operand
- GEPTypes.pop_back();
-
+ // Record the operations to emit the GEP in a vector so that we can emit them
+ // after having analyzed the entire instruction.
+ std::vector<CollapsedGepOp> ops;
+
+ // GEPs have zero or more indices; we must perform a struct access
+ // or array access for each one.
+ for (GetElementPtrInst::op_iterator oi = IdxBegin, oe = IdxEnd; oi != oe;
+ ++oi) {
+ Value *idx = *oi;
+ if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
+ // It's a struct access. idx is the index into the structure,
+ // which names the field. Use the TargetData structure to
+ // pick out what the layout of the structure is in memory.
+ // Use the (constant) structure index's value to find the
+ // right byte offset from the StructLayout class's list of
+ // structure member offsets.
+ unsigned fieldIndex = cast<ConstantUInt>(idx)->getValue();
+ unsigned memberOffset =
+ TD.getStructLayout(StTy)->MemberOffsets[fieldIndex];
+
+ // StructType member offsets are always constant values. Add it to the
+ // running total.
+ constValue += memberOffset;
+
+ // The next type is the member of the structure selected by the
+ // index.
+ Ty = StTy->getElementType (fieldIndex);
+ } else if (const SequentialType *SqTy = dyn_cast<SequentialType> (Ty)) {
// Many GEP instructions use a [cast (int/uint) to LongTy] as their
// operand. Handle this case directly now...
if (CastInst *CI = dyn_cast<CastInst>(idx))
if (CI->getOperand(0)->getType() == Type::IntTy ||
CI->getOperand(0)->getType() == Type::UIntTy)
idx = CI->getOperand(0);
-
- // We want to add BaseReg to(idxReg * sizeof ElementType). First, we
+
+ // It's an array or pointer access: [ArraySize x ElementType].
+ // We want to add basePtrReg to (idxReg * sizeof ElementType). First, we
// must find the size of the pointed-to type (Not coincidentally, the next
// type is the type of the elements in the array).
- const Type *ElTy = SqTy->getElementType();
- unsigned elementSize = TD.getTypeSize(ElTy);
-
- if (idx == Constant::getNullValue(idx->getType())) {
- // GEP with idx 0 is a no-op
- } else if (elementSize == 1) {
- // If the element size is 1, we don't have to multiply, just add
- unsigned idxReg = getReg(idx, MBB, IP);
- unsigned Reg = makeAnotherReg(Type::UIntTy);
- BuildMI(*MBB, IP, PPC32::ADD, 2,TargetReg).addReg(Reg).addReg(idxReg);
- --IP; // Insert the next instruction before this one.
- TargetReg = Reg; // Codegen the rest of the GEP into this
- } else {
- unsigned idxReg = getReg(idx, MBB, IP);
- unsigned OffsetReg = makeAnotherReg(Type::UIntTy);
-
- // Make sure we can back the iterator up to point to the first
- // instruction emitted.
- MachineBasicBlock::iterator BeforeIt = IP;
- if (IP == MBB->begin())
- BeforeIt = MBB->end();
- else
- --BeforeIt;
- doMultiplyConst(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSize);
-
- // Emit an ADD to add OffsetReg to the basePtr.
- unsigned Reg = makeAnotherReg(Type::UIntTy);
- BuildMI(*MBB, IP, PPC32::ADD, 2, TargetReg).addReg(Reg).addReg(OffsetReg);
-
- // Step to the first instruction of the multiply.
- if (BeforeIt == MBB->end())
- IP = MBB->begin();
+ Ty = SqTy->getElementType();
+ unsigned elementSize = TD.getTypeSize(Ty);
+
+ if (ConstantInt *C = dyn_cast<ConstantInt>(idx)) {
+ if (ConstantSInt *CS = dyn_cast<ConstantSInt>(C))
+ constValue += CS->getValue() * elementSize;
+ else if (ConstantUInt *CU = dyn_cast<ConstantUInt>(C))
+ constValue += CU->getValue() * elementSize;
else
- IP = ++BeforeIt;
-
- TargetReg = Reg; // Codegen the rest of the GEP into this
+ assert(0 && "Invalid ConstantInt GEP index type!");
+ } else {
+ // Push current gep state to this point as an add
+ ops.push_back(CollapsedGepOp(false, 0,
+ ConstantSInt::get(Type::IntTy,constValue)));
+
+ // Push multiply gep op and reset constant value
+ ops.push_back(CollapsedGepOp(true, idx,
+ ConstantSInt::get(Type::IntTy, elementSize)));
+
+ constValue = 0;
}
}
}
+ // Emit instructions for all the collapsed ops
+ bool pendingAdd = false;
+ unsigned pendingAddReg = 0;
+
+ for(std::vector<CollapsedGepOp>::iterator cgo_i = ops.begin(),
+ cgo_e = ops.end(); cgo_i != cgo_e; ++cgo_i) {
+ CollapsedGepOp& cgo = *cgo_i;
+ unsigned nextBasePtrReg = makeAnotherReg(Type::IntTy);
+
+ // If we didn't emit an add last time through the loop, we need to now so
+ // that the base reg is updated appropriately.
+ if (pendingAdd) {
+ assert(pendingAddReg != 0 && "Uninitialized register in pending add!");
+ BuildMI(*MBB, IP, PPC::ADD, 2, nextBasePtrReg).addReg(basePtrReg)
+ .addReg(pendingAddReg);
+ basePtrReg = nextBasePtrReg;
+ nextBasePtrReg = makeAnotherReg(Type::IntTy);
+ pendingAddReg = 0;
+ pendingAdd = false;
+ }
+
+ if (cgo.isMul) {
+ // We know the elementSize is a constant, so we can emit a constant mul
+ unsigned TmpReg = makeAnotherReg(Type::IntTy);
+ doMultiplyConst(MBB, IP, nextBasePtrReg, cgo.index, cgo.size);
+ pendingAddReg = basePtrReg;
+ pendingAdd = true;
+ } else {
+ // Try and generate an immediate addition if possible
+ if (cgo.size->isNullValue()) {
+ BuildMI(*MBB, IP, PPC::OR, 2, nextBasePtrReg).addReg(basePtrReg)
+ .addReg(basePtrReg);
+ } else if (canUseAsImmediateForOpcode(cgo.size, 0)) {
+ BuildMI(*MBB, IP, PPC::ADDI, 2, nextBasePtrReg).addReg(basePtrReg)
+ .addSImm(cgo.size->getValue());
+ } else {
+ unsigned Op1r = getReg(cgo.size, MBB, IP);
+ BuildMI(*MBB, IP, PPC::ADD, 2, nextBasePtrReg).addReg(basePtrReg)
+ .addReg(Op1r);
+ }
+ }
+
+ basePtrReg = nextBasePtrReg;
+ }
+ // Add the current base register plus any accumulated constant value
+ ConstantSInt *remainder = ConstantSInt::get(Type::IntTy, constValue);
+
+ // If we are emitting this during a fold, copy the current base register to
+ // the target, and save the current constant offset so the folding load or
+ // store can try and use it as an immediate.
+ if (GEPIsFolded) {
+ // If this is a folded GEP and the last element was an index, then we need
+ // to do some extra work to turn a shift/add/stw into a shift/stwx
+ if (pendingAdd && 0 == remainder->getValue()) {
+ assert(pendingAddReg != 0 && "Uninitialized register in pending add!");
+ *PendingAddReg = pendingAddReg;
+ } else {
+ *PendingAddReg = 0;
+ if (pendingAdd) {
+ unsigned nextBasePtrReg = makeAnotherReg(Type::IntTy);
+ assert(pendingAddReg != 0 && "Uninitialized register in pending add!");
+ BuildMI(*MBB, IP, PPC::ADD, 2, nextBasePtrReg).addReg(basePtrReg)
+ .addReg(pendingAddReg);
+ basePtrReg = nextBasePtrReg;
+ }
+ }
+ BuildMI (*MBB, IP, PPC::OR, 2, TargetReg).addReg(basePtrReg)
+ .addReg(basePtrReg);
+ *RemainderPtr = remainder;
+ return;
+ }
+
+ // If we still have a pending add at this point, emit it now
+ if (pendingAdd) {
+ unsigned TmpReg = makeAnotherReg(Type::IntTy);
+ BuildMI(*MBB, IP, PPC::ADD, 2, TmpReg).addReg(pendingAddReg)
+ .addReg(basePtrReg);
+ basePtrReg = TmpReg;
+ }
+
+ // After we have processed all the indices, the result is left in
+ // basePtrReg. Move it to the register where we were expected to
+ // put the answer.
+ if (remainder->isNullValue()) {
+ BuildMI (*MBB, IP, PPC::OR, 2, TargetReg).addReg(basePtrReg)
+ .addReg(basePtrReg);
+ } else if (canUseAsImmediateForOpcode(remainder, 0)) {
+ BuildMI(*MBB, IP, PPC::ADDI, 2, TargetReg).addReg(basePtrReg)
+ .addSImm(remainder->getValue());
+ } else {
+ unsigned Op1r = getReg(remainder, MBB, IP);
+ BuildMI(*MBB, IP, PPC::ADD, 2, TargetReg).addReg(basePtrReg).addReg(Op1r);
+ }
}
/// visitAllocaInst - If this is a fixed size alloca, allocate space from the
// Create a register to hold the temporary result of multiplying the type size
// constant by the variable amount.
unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
- unsigned SrcReg1 = getReg(I.getArraySize());
// TotalSizeReg = mul <numelements>, <TypeSize>
MachineBasicBlock::iterator MBBI = BB->end();
- doMultiplyConst(BB, MBBI, TotalSizeReg, Type::UIntTy, SrcReg1, TySize);
+ ConstantUInt *CUI = ConstantUInt::get(Type::UIntTy, TySize);
+ doMultiplyConst(BB, MBBI, TotalSizeReg, I.getArraySize(), CUI);
// AddedSize = add <TotalSizeReg>, 15
unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy);
- BuildMI(BB, PPC32::ADD, 2, AddedSizeReg).addReg(TotalSizeReg).addImm(15);
+ BuildMI(BB, PPC::ADDI, 2, AddedSizeReg).addReg(TotalSizeReg).addSImm(15);
// AlignedSize = and <AddedSize>, ~15
unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
- BuildMI(BB, PPC32::RLWNM, 4, AlignedSize).addReg(AddedSizeReg).addImm(0)
+ BuildMI(BB, PPC::RLWINM, 4, AlignedSize).addReg(AddedSizeReg).addImm(0)
.addImm(0).addImm(27);
// Subtract size from stack pointer, thereby allocating some space.
- BuildMI(BB, PPC32::SUB, 2, PPC32::R1).addReg(PPC32::R1).addReg(AlignedSize);
+ BuildMI(BB, PPC::SUB, 2, PPC::R1).addReg(PPC::R1).addReg(AlignedSize);
// Put a pointer to the space into the result register, by copying
// the stack pointer.
- BuildMI(BB, PPC32::OR, 2, getReg(I)).addReg(PPC32::R1).addReg(PPC32::R1);
+ BuildMI(BB, PPC::OR, 2, getReg(I)).addReg(PPC::R1).addReg(PPC::R1);
// Inform the Frame Information that we have just allocated a variable-sized
// object.
Arg = getReg(ConstantUInt::get(Type::UIntTy, C->getValue() * AllocSize));
} else {
Arg = makeAnotherReg(Type::UIntTy);
- unsigned Op0Reg = getReg(I.getOperand(0));
MachineBasicBlock::iterator MBBI = BB->end();
- doMultiplyConst(BB, MBBI, Arg, Type::UIntTy, Op0Reg, AllocSize);
+ ConstantUInt *CUI = ConstantUInt::get(Type::UIntTy, AllocSize);
+ doMultiplyConst(BB, MBBI, Arg, I.getOperand(0), CUI);
}
std::vector<ValueRecord> Args;
Args.push_back(ValueRecord(Arg, Type::UIntTy));
MachineInstr *TheCall =
- BuildMI(PPC32::CALLpcrel, 1).addGlobalAddress(mallocFn, true);
+ BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(mallocFn, true);
doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args, false);
+ TM.CalledFunctions.insert(mallocFn);
}
std::vector<ValueRecord> Args;
Args.push_back(ValueRecord(I.getOperand(0)));
MachineInstr *TheCall =
- BuildMI(PPC32::CALLpcrel, 1).addGlobalAddress(freeFn, true);
+ BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(freeFn, true);
doCall(ValueRecord(0, Type::VoidTy), TheCall, Args, false);
+ TM.CalledFunctions.insert(freeFn);
}
-/// createPPC32SimpleInstructionSelector - This pass converts an LLVM function
-/// into a machine code representation is a very simple peep-hole fashion. The
-/// generated code sucks but the implementation is nice and simple.
+/// createPPC32ISelSimple - This pass converts an LLVM function into a machine
+/// code representation is a very simple peep-hole fashion.
///
-FunctionPass *llvm::createPPCSimpleInstructionSelector(TargetMachine &TM) {
+FunctionPass *llvm::createPPC32ISelSimple(TargetMachine &TM) {
return new ISel(TM);
}
projects / oota-llvm.git / blobdiff