// MCInst records.
//
//===----------------------------------------------------------------------===//
-
#include "MipsMCInstLower.h"
+#include "MCTargetDesc/MipsBaseInfo.h"
#include "MipsAsmPrinter.h"
#include "MipsInstrInfo.h"
-#include "MCTargetDesc/MipsBaseInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/IR/Mangler.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
-#include "llvm/Target/Mangler.h"
+#include "llvm/MC/MCStreamer.h"
using namespace llvm;
MipsMCInstLower::MipsMCInstLower(MipsAsmPrinter &asmprinter)
: AsmPrinter(asmprinter) {}
-void MipsMCInstLower::Initialize(Mangler *M, MCContext* C) {
- Mang = M;
+void MipsMCInstLower::Initialize(MCContext *C) {
Ctx = C;
}
case MipsII::MO_GOT_DISP: Kind = MCSymbolRefExpr::VK_Mips_GOT_DISP; break;
case MipsII::MO_GOT_PAGE: Kind = MCSymbolRefExpr::VK_Mips_GOT_PAGE; break;
case MipsII::MO_GOT_OFST: Kind = MCSymbolRefExpr::VK_Mips_GOT_OFST; break;
+ case MipsII::MO_HIGHER: Kind = MCSymbolRefExpr::VK_Mips_HIGHER; break;
+ case MipsII::MO_HIGHEST: Kind = MCSymbolRefExpr::VK_Mips_HIGHEST; break;
+ case MipsII::MO_GOT_HI16: Kind = MCSymbolRefExpr::VK_Mips_GOT_HI16; break;
+ case MipsII::MO_GOT_LO16: Kind = MCSymbolRefExpr::VK_Mips_GOT_LO16; break;
+ case MipsII::MO_CALL_HI16: Kind = MCSymbolRefExpr::VK_Mips_CALL_HI16; break;
+ case MipsII::MO_CALL_LO16: Kind = MCSymbolRefExpr::VK_Mips_CALL_LO16; break;
}
switch (MOTy) {
break;
case MachineOperand::MO_GlobalAddress:
- Symbol = Mang->getSymbol(MO.getGlobal());
+ Symbol = AsmPrinter.getSymbol(MO.getGlobal());
+ Offset += MO.getOffset();
break;
case MachineOperand::MO_BlockAddress:
Symbol = AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress());
+ Offset += MO.getOffset();
break;
case MachineOperand::MO_ExternalSymbol:
Symbol = AsmPrinter.GetExternalSymbolSymbol(MO.getSymbolName());
+ Offset += MO.getOffset();
break;
case MachineOperand::MO_JumpTableIndex:
case MachineOperand::MO_ConstantPoolIndex:
Symbol = AsmPrinter.GetCPISymbol(MO.getIndex());
- if (MO.getOffset())
- Offset += MO.getOffset();
+ Offset += MO.getOffset();
break;
default:
llvm_unreachable("<unknown operand type>");
}
- const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::Create(Symbol, Kind, *Ctx);
+ const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::create(Symbol, Kind, *Ctx);
if (!Offset)
- return MCOperand::CreateExpr(MCSym);
+ return MCOperand::createExpr(MCSym);
// Assume offset is never negative.
assert(Offset > 0);
- const MCConstantExpr *OffsetExpr = MCConstantExpr::Create(Offset, *Ctx);
- const MCBinaryExpr *AddExpr = MCBinaryExpr::CreateAdd(MCSym, OffsetExpr, *Ctx);
- return MCOperand::CreateExpr(AddExpr);
+ const MCConstantExpr *OffsetExpr = MCConstantExpr::create(Offset, *Ctx);
+ const MCBinaryExpr *Add = MCBinaryExpr::createAdd(MCSym, OffsetExpr, *Ctx);
+ return MCOperand::createExpr(Add);
}
-static void CreateMCInst(MCInst& Inst, unsigned Opc, const MCOperand& Opnd0,
- const MCOperand& Opnd1,
- const MCOperand& Opnd2 = MCOperand()) {
+/*
+static void CreateMCInst(MCInst& Inst, unsigned Opc, const MCOperand &Opnd0,
+ const MCOperand &Opnd1,
+ const MCOperand &Opnd2 = MCOperand()) {
Inst.setOpcode(Opc);
Inst.addOperand(Opnd0);
Inst.addOperand(Opnd1);
if (Opnd2.isValid())
Inst.addOperand(Opnd2);
}
+*/
-// Lower ".cpload $reg" to
-// "lui $gp, %hi(_gp_disp)"
-// "addiu $gp, $gp, %lo(_gp_disp)"
-// "addu $gp, $gp, $t9"
-void MipsMCInstLower::LowerCPLOAD(SmallVector<MCInst, 4>& MCInsts) {
- MCOperand GPReg = MCOperand::CreateReg(Mips::GP);
- MCOperand T9Reg = MCOperand::CreateReg(Mips::T9);
- StringRef SymName("_gp_disp");
- const MCSymbol *Sym = Ctx->GetOrCreateSymbol(SymName);
- const MCSymbolRefExpr *MCSym;
-
- MCSym = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_Mips_ABS_HI, *Ctx);
- MCOperand SymHi = MCOperand::CreateExpr(MCSym);
- MCSym = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_Mips_ABS_LO, *Ctx);
- MCOperand SymLo = MCOperand::CreateExpr(MCSym);
-
- MCInsts.resize(3);
-
- CreateMCInst(MCInsts[0], Mips::LUi, GPReg, SymHi);
- CreateMCInst(MCInsts[1], Mips::ADDiu, GPReg, GPReg, SymLo);
- CreateMCInst(MCInsts[2], Mips::ADDu, GPReg, GPReg, T9Reg);
-}
-
-// Lower ".cprestore offset" to "sw $gp, offset($sp)".
-void MipsMCInstLower::LowerCPRESTORE(int64_t Offset,
- SmallVector<MCInst, 4>& MCInsts) {
- assert(isInt<32>(Offset) && (Offset >= 0) &&
- "Imm operand of .cprestore must be a non-negative 32-bit value.");
-
- MCOperand SPReg = MCOperand::CreateReg(Mips::SP), BaseReg = SPReg;
- MCOperand GPReg = MCOperand::CreateReg(Mips::GP);
-
- if (!isInt<16>(Offset)) {
- unsigned Hi = ((Offset + 0x8000) >> 16) & 0xffff;
- Offset &= 0xffff;
- MCOperand ATReg = MCOperand::CreateReg(Mips::AT);
- BaseReg = ATReg;
-
- // lui at,hi
- // addu at,at,sp
- MCInsts.resize(2);
- CreateMCInst(MCInsts[0], Mips::LUi, ATReg, MCOperand::CreateImm(Hi));
- CreateMCInst(MCInsts[1], Mips::ADDu, ATReg, ATReg, SPReg);
- }
-
- MCInst Sw;
- CreateMCInst(Sw, Mips::SW, GPReg, BaseReg, MCOperand::CreateImm(Offset));
- MCInsts.push_back(Sw);
-}
-
-MCOperand MipsMCInstLower::LowerOperand(const MachineOperand& MO,
+MCOperand MipsMCInstLower::LowerOperand(const MachineOperand &MO,
unsigned offset) const {
MachineOperandType MOTy = MO.getType();
case MachineOperand::MO_Register:
// Ignore all implicit register operands.
if (MO.isImplicit()) break;
- return MCOperand::CreateReg(MO.getReg());
+ return MCOperand::createReg(MO.getReg());
case MachineOperand::MO_Immediate:
- return MCOperand::CreateImm(MO.getImm() + offset);
+ return MCOperand::createImm(MO.getImm() + offset);
case MachineOperand::MO_MachineBasicBlock:
case MachineOperand::MO_GlobalAddress:
case MachineOperand::MO_ExternalSymbol:
return MCOperand();
}
+MCOperand MipsMCInstLower::createSub(MachineBasicBlock *BB1,
+ MachineBasicBlock *BB2,
+ MCSymbolRefExpr::VariantKind Kind) const {
+ const MCSymbolRefExpr *Sym1 = MCSymbolRefExpr::create(BB1->getSymbol(), *Ctx);
+ const MCSymbolRefExpr *Sym2 = MCSymbolRefExpr::create(BB2->getSymbol(), *Ctx);
+ const MCBinaryExpr *Sub = MCBinaryExpr::createSub(Sym1, Sym2, *Ctx);
+
+ return MCOperand::createExpr(MipsMCExpr::create(Kind, Sub, *Ctx));
+}
+
+void MipsMCInstLower::
+lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const {
+ OutMI.setOpcode(Mips::LUi);
+
+ // Lower register operand.
+ OutMI.addOperand(LowerOperand(MI->getOperand(0)));
+
+ // Create %hi($tgt-$baltgt).
+ OutMI.addOperand(createSub(MI->getOperand(1).getMBB(),
+ MI->getOperand(2).getMBB(),
+ MCSymbolRefExpr::VK_Mips_ABS_HI));
+}
+
+void MipsMCInstLower::
+lowerLongBranchADDiu(const MachineInstr *MI, MCInst &OutMI, int Opcode,
+ MCSymbolRefExpr::VariantKind Kind) const {
+ OutMI.setOpcode(Opcode);
+
+ // Lower two register operands.
+ for (unsigned I = 0, E = 2; I != E; ++I) {
+ const MachineOperand &MO = MI->getOperand(I);
+ OutMI.addOperand(LowerOperand(MO));
+ }
+
+ // Create %lo($tgt-$baltgt) or %hi($tgt-$baltgt).
+ OutMI.addOperand(createSub(MI->getOperand(2).getMBB(),
+ MI->getOperand(3).getMBB(), Kind));
+}
+
+bool MipsMCInstLower::lowerLongBranch(const MachineInstr *MI,
+ MCInst &OutMI) const {
+ switch (MI->getOpcode()) {
+ default:
+ return false;
+ case Mips::LONG_BRANCH_LUi:
+ lowerLongBranchLUi(MI, OutMI);
+ return true;
+ case Mips::LONG_BRANCH_ADDiu:
+ lowerLongBranchADDiu(MI, OutMI, Mips::ADDiu,
+ MCSymbolRefExpr::VK_Mips_ABS_LO);
+ return true;
+ case Mips::LONG_BRANCH_DADDiu:
+ unsigned TargetFlags = MI->getOperand(2).getTargetFlags();
+ if (TargetFlags == MipsII::MO_ABS_HI)
+ lowerLongBranchADDiu(MI, OutMI, Mips::DADDiu,
+ MCSymbolRefExpr::VK_Mips_ABS_HI);
+ else if (TargetFlags == MipsII::MO_ABS_LO)
+ lowerLongBranchADDiu(MI, OutMI, Mips::DADDiu,
+ MCSymbolRefExpr::VK_Mips_ABS_LO);
+ else
+ report_fatal_error("Unexpected flags for LONG_BRANCH_DADDiu");
+ return true;
+ }
+}
+
void MipsMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
+ if (lowerLongBranch(MI, OutMI))
+ return;
+
OutMI.setOpcode(MI->getOpcode());
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
}
}
-void MipsMCInstLower::LowerUnalignedLoadStore(const MachineInstr *MI,
- SmallVector<MCInst,
- 4>& MCInsts) {
- unsigned Opc = MI->getOpcode();
- MCInst Instr1, Instr2, Instr3, Move;
-
- bool TwoInstructions = false;
-
- assert(MI->getNumOperands() == 3);
- assert(MI->getOperand(0).isReg());
- assert(MI->getOperand(1).isReg());
-
- MCOperand Target = LowerOperand(MI->getOperand(0));
- MCOperand Base = LowerOperand(MI->getOperand(1));
- MCOperand ATReg = MCOperand::CreateReg(Mips::AT);
- MCOperand ZeroReg = MCOperand::CreateReg(Mips::ZERO);
-
- MachineOperand UnLoweredName = MI->getOperand(2);
- MCOperand Name = LowerOperand(UnLoweredName);
-
- Move.setOpcode(Mips::ADDu);
- Move.addOperand(Target);
- Move.addOperand(ATReg);
- Move.addOperand(ZeroReg);
-
- switch (Opc) {
- case Mips::ULW: {
- // FIXME: only works for little endian right now
- MCOperand AdjName = LowerOperand(UnLoweredName, 3);
- if (Base.getReg() == (Target.getReg())) {
- Instr1.setOpcode(Mips::LWL);
- Instr1.addOperand(ATReg);
- Instr1.addOperand(Base);
- Instr1.addOperand(AdjName);
- Instr2.setOpcode(Mips::LWR);
- Instr2.addOperand(ATReg);
- Instr2.addOperand(Base);
- Instr2.addOperand(Name);
- Instr3 = Move;
- } else {
- TwoInstructions = true;
- Instr1.setOpcode(Mips::LWL);
- Instr1.addOperand(Target);
- Instr1.addOperand(Base);
- Instr1.addOperand(AdjName);
- Instr2.setOpcode(Mips::LWR);
- Instr2.addOperand(Target);
- Instr2.addOperand(Base);
- Instr2.addOperand(Name);
- }
- break;
- }
- case Mips::ULHu: {
- // FIXME: only works for little endian right now
- MCOperand AdjName = LowerOperand(UnLoweredName, 1);
- Instr1.setOpcode(Mips::LBu);
- Instr1.addOperand(ATReg);
- Instr1.addOperand(Base);
- Instr1.addOperand(AdjName);
- Instr2.setOpcode(Mips::LBu);
- Instr2.addOperand(Target);
- Instr2.addOperand(Base);
- Instr2.addOperand(Name);
- Instr3.setOpcode(Mips::INS);
- Instr3.addOperand(Target);
- Instr3.addOperand(ATReg);
- Instr3.addOperand(MCOperand::CreateImm(0x8));
- Instr3.addOperand(MCOperand::CreateImm(0x18));
- break;
- }
-
- case Mips::USW: {
- // FIXME: only works for little endian right now
- assert (Base.getReg() != Target.getReg());
- TwoInstructions = true;
- MCOperand AdjName = LowerOperand(UnLoweredName, 3);
- Instr1.setOpcode(Mips::SWL);
- Instr1.addOperand(Target);
- Instr1.addOperand(Base);
- Instr1.addOperand(AdjName);
- Instr2.setOpcode(Mips::SWR);
- Instr2.addOperand(Target);
- Instr2.addOperand(Base);
- Instr2.addOperand(Name);
- break;
- }
- case Mips::USH: {
- MCOperand AdjName = LowerOperand(UnLoweredName, 1);
- Instr1.setOpcode(Mips::SB);
- Instr1.addOperand(Target);
- Instr1.addOperand(Base);
- Instr1.addOperand(Name);
- Instr2.setOpcode(Mips::SRL);
- Instr2.addOperand(ATReg);
- Instr2.addOperand(Target);
- Instr2.addOperand(MCOperand::CreateImm(8));
- Instr3.setOpcode(Mips::SB);
- Instr3.addOperand(ATReg);
- Instr3.addOperand(Base);
- Instr3.addOperand(AdjName);
- break;
- }
- default:
- // FIXME: need to add others
- llvm_unreachable("unaligned instruction not processed");
- }
-
- MCInsts.push_back(Instr1);
- MCInsts.push_back(Instr2);
- if (!TwoInstructions) MCInsts.push_back(Instr3);
-}
-
-// Convert
-// "setgp01 $reg"
-// to
-// "lui $reg, %hi(_gp_disp)"
-// "addiu $reg, $reg, %lo(_gp_disp)"
-void MipsMCInstLower::LowerSETGP01(const MachineInstr *MI,
- SmallVector<MCInst, 4>& MCInsts) {
- const MachineOperand &MO = MI->getOperand(0);
- assert(MO.isReg());
- MCOperand RegOpnd = MCOperand::CreateReg(MO.getReg());
- StringRef SymName("_gp_disp");
- const MCSymbol *Sym = Ctx->GetOrCreateSymbol(SymName);
- const MCSymbolRefExpr *MCSym;
-
- MCSym = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_Mips_ABS_HI, *Ctx);
- MCOperand SymHi = MCOperand::CreateExpr(MCSym);
- MCSym = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_Mips_ABS_LO, *Ctx);
- MCOperand SymLo = MCOperand::CreateExpr(MCSym);
-
- MCInsts.resize(2);
-
- CreateMCInst(MCInsts[0], Mips::LUi, RegOpnd, SymHi);
- CreateMCInst(MCInsts[1], Mips::ADDiu, RegOpnd, RegOpnd, SymLo);
-}
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