Move all of the header files which are involved in modelling the LLVM IR

[oota-llvm.git] / lib / Target / Mips / MipsISelLowering.cpp

diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index f9a4d4acff4f302c316a1aaed42b0e2ddf6fe7e8..af7498b0e943fc6f3f591de636f47ba390b9f62b 100644 (file)
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -21,7 +21,6 @@
 #include "MipsTargetMachine.h"
 #include "MipsTargetObjectFile.h"
 #include "llvm/ADT/Statistic.h"
-#include "llvm/CallingConv.h"
 #include "llvm/CodeGen/CallingConvLower.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
@@ -29,10 +28,11 @@
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/SelectionDAGISel.h"
 #include "llvm/CodeGen/ValueTypes.h"
-#include "llvm/DerivedTypes.h"
-#include "llvm/Function.h"
-#include "llvm/GlobalVariable.h"
-#include "llvm/Intrinsics.h"
+#include "llvm/IR/CallingConv.h"
+#include "llvm/IR/DerivedTypes.h"
+#include "llvm/IR/Function.h"
+#include "llvm/IR/GlobalVariable.h"
+#include "llvm/IR/Intrinsics.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
@@ -50,6 +50,13 @@ static cl::opt<bool>
 LargeGOT("mxgot", cl::Hidden,
          cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
 
+static cl::opt<bool>
+Mips16HardFloat("mips16-hard-float", cl::NotHidden,
+                cl::desc("MIPS: mips16 hard float enable."),
+                cl::init(false));
+
+
+
 static const uint16_t O32IntRegs[4] = {
   Mips::A0, Mips::A1, Mips::A2, Mips::A3
 };
@@ -198,6 +205,41 @@ const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
   }
 }
 
+void MipsTargetLowering::setMips16HardFloatLibCalls() {
+  setLibcallName(RTLIB::ADD_F32, "__mips16_addsf3");
+  setLibcallName(RTLIB::ADD_F64, "__mips16_adddf3");
+  setLibcallName(RTLIB::SUB_F32, "__mips16_subsf3");
+  setLibcallName(RTLIB::SUB_F64, "__mips16_subdf3");
+  setLibcallName(RTLIB::MUL_F32, "__mips16_mulsf3");
+  setLibcallName(RTLIB::MUL_F64, "__mips16_muldf3");
+  setLibcallName(RTLIB::DIV_F32, "__mips16_divsf3");
+  setLibcallName(RTLIB::DIV_F64, "__mips16_divdf3");
+  setLibcallName(RTLIB::FPEXT_F32_F64, "__mips16_extendsfdf2");
+  setLibcallName(RTLIB::FPROUND_F64_F32, "__mips16_truncdfsf2");
+  setLibcallName(RTLIB::FPTOSINT_F32_I32, "__mips16_fix_truncsfsi");
+  setLibcallName(RTLIB::FPTOSINT_F64_I32, "__mips16_fix_truncdfsi");
+  setLibcallName(RTLIB::SINTTOFP_I32_F32, "__mips16_floatsisf");
+  setLibcallName(RTLIB::SINTTOFP_I32_F64, "__mips16_floatsidf");
+  setLibcallName(RTLIB::UINTTOFP_I32_F32, "__mips16_floatunsisf");
+  setLibcallName(RTLIB::UINTTOFP_I32_F64, "__mips16_floatunsidf");
+  setLibcallName(RTLIB::OEQ_F32, "__mips16_eqsf2");
+  setLibcallName(RTLIB::OEQ_F64, "__mips16_eqdf2");
+  setLibcallName(RTLIB::UNE_F32, "__mips16_nesf2");
+  setLibcallName(RTLIB::UNE_F64, "__mips16_nedf2");
+  setLibcallName(RTLIB::OGE_F32, "__mips16_gesf2");
+  setLibcallName(RTLIB::OGE_F64, "__mips16_gedf2");
+  setLibcallName(RTLIB::OLT_F32, "__mips16_ltsf2");
+  setLibcallName(RTLIB::OLT_F64, "__mips16_ltdf2");
+  setLibcallName(RTLIB::OLE_F32, "__mips16_lesf2");
+  setLibcallName(RTLIB::OLE_F64, "__mips16_ledf2");
+  setLibcallName(RTLIB::OGT_F32, "__mips16_gtsf2");
+  setLibcallName(RTLIB::OGT_F64, "__mips16_gtdf2");
+  setLibcallName(RTLIB::UO_F32, "__mips16_unordsf2");
+  setLibcallName(RTLIB::UO_F64, "__mips16_unorddf2");
+  setLibcallName(RTLIB::O_F32, "__mips16_unordsf2");
+  setLibcallName(RTLIB::O_F64, "__mips16_unorddf2");
+}
+
 MipsTargetLowering::
 MipsTargetLowering(MipsTargetMachine &TM)
   : TargetLowering(TM, new MipsTargetObjectFile()),
@@ -218,6 +260,8 @@ MipsTargetLowering(MipsTargetMachine &TM)
 
   if (Subtarget->inMips16Mode()) {
     addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
+    if (Mips16HardFloat)
+      setMips16HardFloatLibCalls();
   }
 
   if (Subtarget->hasDSP()) {
@@ -1004,7 +1048,6 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const
 static unsigned
 AddLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
 {
-  assert(RC->contains(PReg) && "Not the correct regclass!");
   unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
   MF.getRegInfo().addLiveIn(PReg, VReg);
   return VReg;
@@ -2155,7 +2198,7 @@ SDValue MipsTargetLowering::LowerRETURNADDR(SDValue Op,
 
   MachineFunction &MF = DAG.getMachineFunction();
   MachineFrameInfo *MFI = MF.getFrameInfo();
-  EVT VT = Op.getValueType();
+  MVT VT = Op.getSimpleValueType();
   unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA;
   MFI->setReturnAddressIsTaken(true);
 
@@ -3056,7 +3099,8 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain,
       const TargetRegisterClass *RC;
 
       if (RegVT == MVT::i32)
-        RC = &Mips::CPURegsRegClass;
+        RC = Subtarget->inMips16Mode()? &Mips::CPU16RegsRegClass :
+                                        &Mips::CPURegsRegClass;
       else if (RegVT == MVT::i64)
         RC = &Mips::CPU64RegsRegClass;
       else if (RegVT == MVT::f32)
@@ -3661,7 +3705,7 @@ copyByValRegs(SDValue Chain, DebugLoc DL, std::vector<SDValue> &OutChains,
     return;
 
   // Copy arg registers.
-  EVT RegTy = MVT::getIntegerVT(CC.regSize() * 8);
+  MVT RegTy = MVT::getIntegerVT(CC.regSize() * 8);
   const TargetRegisterClass *RC = getRegClassFor(RegTy);
 
   for (unsigned I = 0; I < ByVal.NumRegs; ++I) {
@@ -3783,7 +3827,7 @@ MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
   const CCState &CCInfo = CC.getCCInfo();
   unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs);
   unsigned RegSize = CC.regSize();
-  EVT RegTy = MVT::getIntegerVT(RegSize * 8);
+  MVT RegTy = MVT::getIntegerVT(RegSize * 8);
   const TargetRegisterClass *RC = getRegClassFor(RegTy);
   MachineFunction &MF = DAG.getMachineFunction();
   MachineFrameInfo *MFI = MF.getFrameInfo();