TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
Context = &funcInfo.Fn->getContext();
+ bool ISASupported = !Subtarget->hasMips32r6() && Subtarget->hasMips32();
TargetSupported =
- ((TM.getRelocationModel() == Reloc::PIC_) &&
- ((Subtarget->hasMips32r2() || Subtarget->hasMips32()) &&
- (static_cast<const MipsTargetMachine &>(TM).getABI().IsO32())));
+ ISASupported && (TM.getRelocationModel() == Reloc::PIC_) &&
+ (static_cast<const MipsTargetMachine &>(TM).getABI().IsO32());
UnsupportedFPMode = Subtarget->isFP64bit();
}
unsigned Opc;
switch (ISDOpc) {
- case ISD::AND:
- Opc = Mips::AND;
- break;
- case ISD::OR:
- Opc = Mips::OR;
- break;
- case ISD::XOR:
- Opc = Mips::XOR;
- break;
- default:
+ case ISD::AND:
+ Opc = Mips::AND;
+ break;
+ case ISD::OR:
+ Opc = Mips::OR;
+ break;
+ case ISD::XOR:
+ Opc = Mips::XOR;
+ break;
+ default:
llvm_unreachable("unexpected opcode");
}
if (!MTI->getLength()->getType()->isIntegerTy(32))
return false;
const char *IntrMemName = isa<MemCpyInst>(II) ? "memcpy" : "memmove";
- return lowerCallTo(II, IntrMemName, II->getNumArgOperands() - 2);
+ return lowerCallTo(II, IntrMemName, II->getNumArgOperands() - 1);
}
case Intrinsic::memset: {
const MemSetInst *MSI = cast<MemSetInst>(II);
return false;
if (!MSI->getLength()->getType()->isIntegerTy(32))
return false;
- return lowerCallTo(II, "memset", II->getNumArgOperands() - 2);
+ return lowerCallTo(II, "memset", II->getNumArgOperands() - 1);
}
}
return false;