def REGIMM_OPCODE : Field6<0b000001>;
class DSPInst<string opstr = "">
- : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
- let Predicates = [HasDSP];
+ : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, PredicateControl {
+ let InsnPredicates = [HasDSP];
string BaseOpcode = opstr;
string Arch = "dsp";
}
class PseudoDSP<dag outs, dag ins, list<dag> pattern,
- InstrItinClass itin = IIPseudo>:
- MipsPseudo<outs, ins, pattern, itin> {
- let Predicates = [HasDSP];
+ InstrItinClass itin = IIPseudo>
+ : MipsPseudo<outs, ins, pattern, itin>, PredicateControl {
+ let InsnPredicates = [HasDSP];
+}
+
+class DSPInstAlias<string Asm, dag Result, bit Emit = 0b1>
+ : InstAlias<Asm, Result, Emit>, PredicateControl {
+ let InsnPredicates = [HasDSP];
}
// ADDU.QB sub-class format.