split LowerMEMCPY into LowerMEMCPYCall and LowerMEMCPYInline in the ARM backend.

[oota-llvm.git] / lib / Target / MRegisterInfo.cpp

diff --git a/lib/Target/MRegisterInfo.cpp b/lib/Target/MRegisterInfo.cpp
index 515ff9af7376049cfd3afd01c38f5016a7999ab9..c5a1251ac14111436fadee46a47d9cfe0add770c 100644 (file)
--- a/lib/Target/MRegisterInfo.cpp
+++ b/lib/Target/MRegisterInfo.cpp
@@ -14,10 +14,10 @@
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/MRegisterInfo.h"
 #include "llvm/Target/TargetFrameInfo.h"
-
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineLocation.h"
+#include "llvm/ADT/BitVector.h"
 
 using namespace llvm;
 
@@ -34,15 +34,41 @@ MRegisterInfo::MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
 
 MRegisterInfo::~MRegisterInfo() {}
 
-std::vector<bool> MRegisterInfo::getAllocatableSet(MachineFunction &MF) const {
-  std::vector<bool> Allocatable(NumRegs);
-  for (MRegisterInfo::regclass_iterator I = regclass_begin(),
-         E = regclass_end(); I != E; ++I) {
-    const TargetRegisterClass *RC = *I;
-    for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
-           E = RC->allocation_order_end(MF); I != E; ++I)
-      Allocatable[*I] = true;
+/// getPhysicalRegisterRegClass - Returns the Register Class of a physical
+/// register.
+const TargetRegisterClass *
+MRegisterInfo::getPhysicalRegisterRegClass(MVT::ValueType VT,
+                                           unsigned reg) const {
+  assert(isPhysicalRegister(reg) && "reg must be a physical register");
+  // Pick the register class of the right type that contains this physreg.
+  for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I)
+    if ((*I)->hasType(VT) && (*I)->contains(reg))
+      return *I;
+  assert(false && "Couldn't find the register class");
+  return 0;
+}
+
+
+/// getAllocatableSetForRC - Toggle the bits that represent allocatable
+/// registers for the specific register class.
+static void getAllocatableSetForRC(MachineFunction &MF,
+                                   const TargetRegisterClass *RC, BitVector &R){  
+  for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
+         E = RC->allocation_order_end(MF); I != E; ++I)
+    R.set(*I);
+}
+
+BitVector MRegisterInfo::getAllocatableSet(MachineFunction &MF,
+                                           const TargetRegisterClass *RC) const {
+  BitVector Allocatable(NumRegs);
+  if (RC) {
+    getAllocatableSetForRC(MF, RC, Allocatable);
+    return Allocatable;
   }
+
+  for (MRegisterInfo::regclass_iterator I = regclass_begin(),
+         E = regclass_end(); I != E; ++I)
+    getAllocatableSetForRC(MF, *I, Allocatable);
   return Allocatable;
 }
 
@@ -64,7 +90,7 @@ void MRegisterInfo::getLocation(MachineFunction &MF, unsigned Index,
 /// getInitialFrameState - Returns a list of machine moves that are assumed
 /// on entry to a function.
 void
-MRegisterInfo::getInitialFrameState(std::vector<MachineMove *> &Moves) const {
+MRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
   // Default is to do nothing.
 }