#include "llvm/Intrinsics.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
-#include <iostream>
#include <queue>
#include <set>
using namespace llvm;
namespace {
- Statistic<> FusedFP ("ia64-codegen", "Number of fused fp operations");
- Statistic<> FrameOff("ia64-codegen", "Number of frame idx offsets collapsed");
+ Statistic FusedFP ("ia64-codegen", "Number of fused fp operations");
+ Statistic FrameOff("ia64-codegen", "Number of frame idx offsets collapsed");
//===--------------------------------------------------------------------===//
/// IA64DAGToDAGISel - IA64 specific code to select IA64 machine
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
- SDNode *Select(SDOperand &Result, SDOperand N);
+ SDNode *Select(SDOperand N);
SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
unsigned OCHi, unsigned OCLo,
#include "IA64GenDAGISel.inc"
private:
- SDOperand SelectDIV(SDOperand Op);
+ SDNode *SelectDIV(SDOperand Op);
};
}
ScheduleAndEmitDAG(DAG);
}
-SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
+SDNode *IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
SDNode *N = Op.Val;
- SDOperand Chain, Tmp1, Tmp2;
- AddToQueue(Chain, N->getOperand(0));
+ SDOperand Chain = N->getOperand(0);
+ SDOperand Tmp1 = N->getOperand(0);
+ SDOperand Tmp2 = N->getOperand(1);
+ AddToISelQueue(Chain);
- AddToQueue(Tmp1, N->getOperand(0));
- AddToQueue(Tmp2, N->getOperand(1));
+ AddToISelQueue(Tmp1);
+ AddToISelQueue(Tmp2);
bool isFP=false;
}
SDOperand TmpE0, TmpY1, TmpE1, TmpY2;
-
+
+ SDOperand OpsE0[] = { TmpF4, TmpF5, F1, TmpPR };
TmpE0 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
- TmpF4, TmpF5, F1, TmpPR), 0);
+ OpsE0, 4), 0);
Chain = TmpE0.getValue(1);
+ SDOperand OpsY1[] = { TmpF5, TmpE0, TmpF5, TmpPR };
TmpY1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
- TmpF5, TmpE0, TmpF5, TmpPR), 0);
+ OpsY1, 4), 0);
Chain = TmpY1.getValue(1);
+ SDOperand OpsE1[] = { TmpE0, TmpE0, F0, TmpPR };
TmpE1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
- TmpE0, TmpE0, F0, TmpPR), 0);
+ OpsE1, 4), 0);
Chain = TmpE1.getValue(1);
+ SDOperand OpsY2[] = { TmpY1, TmpE1, TmpY1, TmpPR };
TmpY2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
- TmpY1, TmpE1, TmpY1, TmpPR), 0);
+ OpsY2, 4), 0);
Chain = TmpY2.getValue(1);
if(isFP) { // if this is an FP divide, we finish up here and exit early
assert(0 && "Sorry, try another FORTRAN compiler.");
SDOperand TmpE2, TmpY3, TmpQ0, TmpR0;
-
+
+ SDOperand OpsE2[] = { TmpE1, TmpE1, F0, TmpPR };
TmpE2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
- TmpE1, TmpE1, F0, TmpPR), 0);
+ OpsE2, 4), 0);
Chain = TmpE2.getValue(1);
+ SDOperand OpsY3[] = { TmpY2, TmpE2, TmpY2, TmpPR };
TmpY3 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
- TmpY2, TmpE2, TmpY2, TmpPR), 0);
+ OpsY3, 4), 0);
Chain = TmpY3.getValue(1);
+ SDOperand OpsQ0[] = { Tmp1, TmpY3, F0, TmpPR };
TmpQ0 =
SDOperand(CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double prec!
- Tmp1, TmpY3, F0, TmpPR), 0);
+ OpsQ0, 4), 0);
Chain = TmpQ0.getValue(1);
+ SDOperand OpsR0[] = { Tmp2, TmpQ0, Tmp1, TmpPR };
TmpR0 =
SDOperand(CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double prec!
- Tmp2, TmpQ0, Tmp1, TmpPR), 0);
+ OpsR0, 4), 0);
Chain = TmpR0.getValue(1);
// we want Result to have the same target register as the frcpa, so
// we two-address hack it. See the comment "for this to work..." on
// page 48 of Intel application note #245415
+ SDOperand Ops[] = { TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR };
Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg!
- TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR);
+ Ops, 5);
Chain = SDOperand(Result, 1);
- return SDOperand(Result, 0); // XXX: early exit!
+ return Result; // XXX: early exit!
} else { // this is *not* an FP divide, so there's a bit left to do:
SDOperand TmpQ2, TmpR2, TmpQ3, TmpQ;
-
+
+ SDOperand OpsQ2[] = { TmpF3, TmpY2, F0, TmpPR };
TmpQ2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
- TmpF3, TmpY2, F0, TmpPR), 0);
+ OpsQ2, 4), 0);
Chain = TmpQ2.getValue(1);
+ SDOperand OpsR2[] = { TmpF4, TmpQ2, TmpF3, TmpPR };
TmpR2 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
- TmpF4, TmpQ2, TmpF3, TmpPR), 0);
+ OpsR2, 4), 0);
Chain = TmpR2.getValue(1);
// we want TmpQ3 to have the same target register as the frcpa? maybe we
// should two-address hack it. See the comment "for this to work..." on page
// 48 of Intel application note #245415
+ SDOperand OpsQ3[] = { TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR };
TmpQ3 = SDOperand(CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64,
- TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR), 0);
+ OpsQ3, 5), 0);
Chain = TmpQ3.getValue(1);
// STORY: without these two-address instructions (TCFMAS1 and TCFMADS0)
Chain = SDOperand(Result, 1);
}
- return SDOperand(Result, 0);
+ return Result;
} // wasn't an FP divide
}
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
-SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
+SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
SDNode *N = Op.Val;
if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
- N->getOpcode() < IA64ISD::FIRST_NUMBER) {
- Result = Op;
+ N->getOpcode() < IA64ISD::FIRST_NUMBER)
return NULL; // Already selected.
- }
switch (N->getOpcode()) {
default: break;
case IA64ISD::BRCALL: { // XXX: this is also a hack!
- SDOperand Chain;
+ SDOperand Chain = N->getOperand(0);
SDOperand InFlag; // Null incoming flag value.
- AddToQueue(Chain, N->getOperand(0));
- if(N->getNumOperands()==3) // we have an incoming chain, callee and flag
- AddToQueue(InFlag, N->getOperand(2));
+ AddToISelQueue(Chain);
+ if(N->getNumOperands()==3) { // we have an incoming chain, callee and flag
+ InFlag = N->getOperand(2);
+ AddToISelQueue(InFlag);
+ }
unsigned CallOpcode;
SDOperand CallOperand;
dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
CallOpcode = IA64::BRCALL_IPREL_GA;
CallOperand = CurDAG->getTargetGlobalAddress(GASD->getGlobal(), MVT::i64);
- } else if (ExternalSymbolSDNode *ESSDN = // FIXME: we currently NEED this
- // case for correctness, to avoid
- // "non-pic code with imm reloc.n
- // against dynamic symbol" errors
- dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) {
+ } else if (isa<ExternalSymbolSDNode>(N->getOperand(1))) {
+ // FIXME: we currently NEED this case for correctness, to avoid
+ // "non-pic code with imm reloc.n against dynamic symbol" errors
CallOpcode = IA64::BRCALL_IPREL_ES;
CallOperand = N->getOperand(1);
} else {
// otherwise we need to load the function descriptor,
// load the branch target (function)'s entry point and GP,
// branch (call) then restore the GP
- SDOperand FnDescriptor;
- AddToQueue(FnDescriptor, N->getOperand(1));
+ SDOperand FnDescriptor = N->getOperand(1);
+ AddToISelQueue(FnDescriptor);
// load the branch target's entry point [mem] and
// GP value [mem+8]
for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
ReplaceUses(Op.getValue(i), CallResults[i]);
- Result = CallResults[Op.ResNo];
return NULL;
}
case IA64ISD::GETFD: {
- SDOperand Input;
- AddToQueue(Input, N->getOperand(0));
- Result = SDOperand(CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input), 0);
- return Result.Val;
+ SDOperand Input = N->getOperand(0);
+ AddToISelQueue(Input);
+ return CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input);
}
case ISD::FDIV:
case ISD::UDIV:
case ISD::SREM:
case ISD::UREM:
- Result = SelectDIV(Op);
- return Result.Val;
+ return SelectDIV(Op);
case ISD::TargetConstantFP: {
SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
+ SDOperand V;
if (cast<ConstantFPSDNode>(N)->isExactlyValue(+0.0)) {
- Result = CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64);
+ V = CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64);
} else if (cast<ConstantFPSDNode>(N)->isExactlyValue(+1.0)) {
- Result = CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64);
+ V = CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64);
} else
assert(0 && "Unexpected FP constant!");
- return Result.Val;
+
+ ReplaceUses(SDOperand(N, 0), V);
+ return 0;
}
case ISD::FrameIndex: { // TODO: reduce creepyness
int FI = cast<FrameIndexSDNode>(N)->getIndex();
- if (N->hasOneUse()) {
- Result = CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
- CurDAG->getTargetFrameIndex(FI, MVT::i64));
- return NULL;
- } else {
- Result = SDOperand(CurDAG->getTargetNode(IA64::MOV, MVT::i64,
- CurDAG->getTargetFrameIndex(FI, MVT::i64)), 0);
- return Result.Val;
- }
+ if (N->hasOneUse())
+ return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
+ CurDAG->getTargetFrameIndex(FI, MVT::i64));
+ else
+ return CurDAG->getTargetNode(IA64::MOV, MVT::i64,
+ CurDAG->getTargetFrameIndex(FI, MVT::i64));
}
case ISD::ConstantPool: { // TODO: nuke the constant pool
// (ia64 doesn't need one)
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N);
- Constant *C = CP->get();
+ Constant *C = CP->getConstVal();
SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64,
CP->getAlignment());
- Result = SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
- CurDAG->getRegister(IA64::r1, MVT::i64), CPI), 0);
- return Result.Val;
+ return CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
+ CurDAG->getRegister(IA64::r1, MVT::i64), CPI);
}
case ISD::GlobalAddress: {
SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
SDOperand Tmp = SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
CurDAG->getRegister(IA64::r1, MVT::i64), GA), 0);
- Result = SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp), 0);
- return Result.Val;
+ return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
}
/* XXX case ISD::ExternalSymbol: {
}
*/
- case ISD::LOAD:
- case ISD::EXTLOAD: // FIXME: load -1, not 1, for bools?
- case ISD::ZEXTLOAD: {
- SDOperand Chain, Address;
- AddToQueue(Chain, N->getOperand(0));
- AddToQueue(Address, N->getOperand(1));
+ case ISD::LOAD: { // FIXME: load -1, not 1, for bools?
+ LoadSDNode *LD = cast<LoadSDNode>(N);
+ SDOperand Chain = LD->getChain();
+ SDOperand Address = LD->getBasePtr();
+ AddToISelQueue(Chain);
+ AddToISelQueue(Address);
- MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ?
- N->getValueType(0) : cast<VTSDNode>(N->getOperand(3))->getVT();
+ MVT::ValueType TypeBeingLoaded = LD->getLoadedVT();
unsigned Opc;
switch (TypeBeingLoaded) {
default:
case MVT::i1: { // this is a bool
Opc = IA64::LD1; // first we load a byte, then compare for != 0
if(N->getValueType(0) == MVT::i1) { // XXX: early exit!
- Result = CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
+ return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
SDOperand(CurDAG->getTargetNode(Opc, MVT::i64, Address), 0),
- CurDAG->getRegister(IA64::r0, MVT::i64),
- Chain).getValue(Op.ResNo);
- return NULL;
+ CurDAG->getRegister(IA64::r0, MVT::i64),
+ Chain);
}
/* otherwise, we want to load a bool into something bigger: LD1
will do that for us, so we just fall through */
}
// TODO: comment this
- Result = CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
- Address, Chain).getValue(Op.ResNo);
- return NULL;
+ return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
+ Address, Chain);
}
- case ISD::TRUNCSTORE:
case ISD::STORE: {
- SDOperand Address, Chain;
- AddToQueue(Address, N->getOperand(2));
- AddToQueue(Chain, N->getOperand(0));
+ StoreSDNode *ST = cast<StoreSDNode>(N);
+ SDOperand Address = ST->getBasePtr();
+ SDOperand Chain = ST->getChain();
+ AddToISelQueue(Address);
+ AddToISelQueue(Chain);
unsigned Opc;
- if (N->getOpcode() == ISD::STORE) {
+ if (ISD::isNON_TRUNCStore(N)) {
switch (N->getOperand(1).getValueType()) {
default: assert(0 && "unknown type in store");
case MVT::i1: { // this is a bool
SDOperand Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64);
Chain = Initial.getValue(1);
// then load 1 into the same reg iff the predicate to store is 1
- SDOperand Tmp;
- AddToQueue(Tmp, N->getOperand(1));
+ SDOperand Tmp = ST->getValue();
+ AddToISelQueue(Tmp);
Tmp = SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
- CurDAG->getConstant(1, MVT::i64),
+ CurDAG->getTargetConstant(1, MVT::i64),
Tmp), 0);
- Result = CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
- return NULL;
+ return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
}
case MVT::i64: Opc = IA64::ST8; break;
case MVT::f64: Opc = IA64::STF8; break;
}
- } else { //ISD::TRUNCSTORE
- switch(cast<VTSDNode>(N->getOperand(4))->getVT()) {
+ } else { // Truncating store
+ switch(ST->getStoredVT()) {
default: assert(0 && "unknown type in truncstore");
case MVT::i8: Opc = IA64::ST1; break;
case MVT::i16: Opc = IA64::ST2; break;
}
}
- SDOperand N1, N2;
- AddToQueue(N1, N->getOperand(1));
- AddToQueue(N2, N->getOperand(2));
- Result = CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain);
- return NULL;
+ SDOperand N1 = N->getOperand(1);
+ SDOperand N2 = N->getOperand(2);
+ AddToISelQueue(N1);
+ AddToISelQueue(N2);
+ return CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain);
}
case ISD::BRCOND: {
- SDOperand Chain, CC;
- AddToQueue(Chain, N->getOperand(0));
- AddToQueue(CC, N->getOperand(1));
+ SDOperand Chain = N->getOperand(0);
+ SDOperand CC = N->getOperand(1);
+ AddToISelQueue(Chain);
+ AddToISelQueue(CC);
MachineBasicBlock *Dest =
cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
//FIXME - we do NOT need long branches all the time
- Result = CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC,
+ return CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC,
CurDAG->getBasicBlock(Dest), Chain);
- return NULL;
}
case ISD::CALLSEQ_START:
int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
- SDOperand N0;
- AddToQueue(N0, N->getOperand(0));
- Result = CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0);
- return NULL;
+ SDOperand N0 = N->getOperand(0);
+ AddToISelQueue(N0);
+ return CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0);
}
case ISD::BR:
// FIXME: we don't need long branches all the time!
- SDOperand N0;
- AddToQueue(N0, N->getOperand(0));
- Result = CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
+ SDOperand N0 = N->getOperand(0);
+ AddToISelQueue(N0);
+ return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
N->getOperand(1), N0);
- return NULL;
}
- return SelectCode(Result, Op);
+ return SelectCode(Op);
}
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