//
// The LLVM Compiler Infrastructure
//
-// This file was developed by Duraid Madina and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
//
//===----------------------------------------------------------------------===//
+#define DEBUG_TYPE "ia64-codegen"
#include "IA64.h"
#include "IA64TargetMachine.h"
#include "IA64ISelLowering.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/ADT/Statistic.h"
#include "llvm/Constants.h"
#include "llvm/GlobalValue.h"
+#include "llvm/Intrinsics.h"
+#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
+#include "llvm/Support/raw_ostream.h"
using namespace llvm;
namespace {
- Statistic<> FusedFP ("ia64-codegen", "Number of fused fp operations");
- Statistic<> FrameOff("ia64-codegen", "Number of frame idx offsets collapsed");
-
//===--------------------------------------------------------------------===//
/// IA64DAGToDAGISel - IA64 specific code to select IA64 machine
/// instructions for SelectionDAG operations.
///
class IA64DAGToDAGISel : public SelectionDAGISel {
- IA64TargetLowering IA64Lowering;
unsigned GlobalBaseReg;
public:
- IA64DAGToDAGISel(TargetMachine &TM)
- : SelectionDAGISel(IA64Lowering), IA64Lowering(TM) {}
+ explicit IA64DAGToDAGISel(IA64TargetMachine &TM)
+ : SelectionDAGISel(TM) {}
virtual bool runOnFunction(Function &Fn) {
// Make sure we re-emit a set of the global base reg if necessary
/// getI64Imm - Return a target constant with the specified value, of type
/// i64.
- inline SDOperand getI64Imm(uint64_t Imm) {
+ inline SDValue getI64Imm(uint64_t Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i64);
}
/// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
/// base register. Return the virtual register that holds this value.
- // SDOperand getGlobalBaseReg(); TODO: hmm
+ // SDValue getGlobalBaseReg(); TODO: hmm
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
- SDOperand Select(SDOperand Op);
+ SDNode *Select(SDValue N);
- SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
+ SDNode *SelectIntImmediateExpr(SDValue LHS, SDValue RHS,
unsigned OCHi, unsigned OCLo,
bool IsArithmetic = false,
bool Negate = false);
/// SelectCC - Select a comparison of the specified values with the
/// specified condition code, returning the CR# of the expression.
- SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
+ SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC);
/// SelectAddr - Given the specified address, return the two operands for a
/// load/store instruction, and return true if it should be an indexed [r+r]
/// operation.
- bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
+ bool SelectAddr(SDValue Addr, SDValue &Op1, SDValue &Op2);
- SDOperand BuildSDIVSequence(SDNode *N);
- SDOperand BuildUDIVSequence(SDNode *N);
-
- /// InstructionSelectBasicBlock - This callback is invoked by
+ /// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
- virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
+ virtual void InstructionSelect();
virtual const char *getPassName() const {
return "IA64 (Itanium) DAG->DAG Instruction Selector";
#include "IA64GenDAGISel.inc"
private:
- SDOperand SelectCALL(SDOperand Op);
+ SDNode *SelectDIV(SDValue Op);
};
}
-/// InstructionSelectBasicBlock - This callback is invoked by
+/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
-void IA64DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
+void IA64DAGToDAGISel::InstructionSelect() {
DEBUG(BB->dump());
-
- // The selection process is inherently a bottom-up recursive process (users
- // select their uses before themselves). Given infinite stack space, we
- // could just start selecting on the root and traverse the whole graph. In
- // practice however, this causes us to run out of stack space on large basic
- // blocks. To avoid this problem, select the entry node, then all its uses,
- // iteratively instead of recursively.
- std::vector<SDOperand> Worklist;
- Worklist.push_back(DAG.getEntryNode());
-
- // Note that we can do this in the IA64 target (scanning forward across token
- // chain edges) because no nodes ever get folded across these edges. On a
- // target like X86 which supports load/modify/store operations, this would
- // have to be more careful.
- while (!Worklist.empty()) {
- SDOperand Node = Worklist.back();
- Worklist.pop_back();
-
- // Chose from the least deep of the top two nodes.
- if (!Worklist.empty() &&
- Worklist.back().Val->getNodeDepth() < Node.Val->getNodeDepth())
- std::swap(Worklist.back(), Node);
-
- if ((Node.Val->getOpcode() >= ISD::BUILTIN_OP_END &&
- Node.Val->getOpcode() < IA64ISD::FIRST_NUMBER) ||
- CodeGenMap.count(Node)) continue;
-
- for (SDNode::use_iterator UI = Node.Val->use_begin(),
- E = Node.Val->use_end(); UI != E; ++UI) {
- // Scan the values. If this use has a value that is a token chain, add it
- // to the worklist.
- SDNode *User = *UI;
- for (unsigned i = 0, e = User->getNumValues(); i != e; ++i)
- if (User->getValueType(i) == MVT::Other) {
- Worklist.push_back(SDOperand(User, i));
- break;
- }
- }
- // Finally, legalize this node.
- Select(Node);
- }
-
// Select target instructions for the DAG.
- DAG.setRoot(Select(DAG.getRoot()));
- CodeGenMap.clear();
- DAG.RemoveDeadNodes();
-
- // Emit machine code to BB.
- ScheduleAndEmitDAG(DAG);
+ SelectRoot(*CurDAG);
+ CurDAG->RemoveDeadNodes();
}
+SDNode *IA64DAGToDAGISel::SelectDIV(SDValue Op) {
+ SDNode *N = Op.getNode();
+ SDValue Chain = N->getOperand(0);
+ SDValue Tmp1 = N->getOperand(0);
+ SDValue Tmp2 = N->getOperand(1);
+ DebugLoc dl = N->getDebugLoc();
-SDOperand IA64DAGToDAGISel::SelectCALL(SDOperand Op) {
- SDNode *N = Op.Val;
- SDOperand Chain = Select(N->getOperand(0));
-
- unsigned CallOpcode;
- std::vector<SDOperand> CallOperands;
-
- // save the current GP, SP and RP : FIXME: do we need to do all 3 always?
- SDOperand GPBeforeCall = CurDAG->getCopyFromReg(Chain, IA64::r1, MVT::i64);
- Chain = GPBeforeCall.getValue(1);
- SDOperand SPBeforeCall = CurDAG->getCopyFromReg(Chain, IA64::r12, MVT::i64);
- Chain = SPBeforeCall.getValue(1);
- SDOperand RPBeforeCall = CurDAG->getCopyFromReg(Chain, IA64::rp, MVT::i64);
- Chain = RPBeforeCall.getValue(1);
-
- // if we can call directly, do so
- if (GlobalAddressSDNode *GASD =
- dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
- CallOpcode = IA64::BRCALL_IPREL;
- CallOperands.push_back(CurDAG->getTargetGlobalAddress(GASD->getGlobal(),
- MVT::i64));
- } else if (ExternalSymbolSDNode *ESSDN = // FIXME: we currently NEED this
- // case for correctness, to avoid
- // "non-pic code with imm reloc.n
- // against dynamic symbol" errors
- dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) {
- CallOpcode = IA64::BRCALL_IPREL;
- CallOperands.push_back(N->getOperand(1));
- } else {
- // otherwise we need to load the function descriptor,
- // load the branch target (function)'s entry point and GP,
- // branch (call) then restore the
- // GP
-
- SDOperand FnDescriptor = Select(N->getOperand(1));
-
- // load the branch target's entry point [mem] and
- // GP value [mem+8]
- SDOperand targetEntryPoint=CurDAG->getLoad(MVT::i64, Chain, FnDescriptor,
- CurDAG->getSrcValue(0));
- SDOperand targetGPAddr=CurDAG->getNode(ISD::ADD, MVT::i64, FnDescriptor,
- CurDAG->getConstant(8, MVT::i64));
- SDOperand targetGP=CurDAG->getLoad(MVT::i64, Chain, targetGPAddr,
- CurDAG->getSrcValue(0));
-
- // Copy the callee address into the b6 branch register
- SDOperand B6 = CurDAG->getRegister(IA64::B6, MVT::i64);
- Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, B6,
- targetEntryPoint);
+ bool isFP=false;
+
+ if(Tmp1.getValueType().isFloatingPoint())
+ isFP=true;
- CallOperands.push_back(B6);
- CallOpcode = IA64::BRCALL_INDIRECT;
+ bool isModulus=false; // is it a division or a modulus?
+ bool isSigned=false;
+
+ switch(N->getOpcode()) {
+ case ISD::FDIV:
+ case ISD::SDIV: isModulus=false; isSigned=true; break;
+ case ISD::UDIV: isModulus=false; isSigned=false; break;
+ case ISD::FREM:
+ case ISD::SREM: isModulus=true; isSigned=true; break;
+ case ISD::UREM: isModulus=true; isSigned=false; break;
}
-
- // see section 8.5.8 of "Itanium Software Conventions and
- // Runtime Architecture Guide to see some examples of what's going
- // on here. (in short: int args get mapped 1:1 'slot-wise' to out0->out7,
- // while FP args get mapped to F8->F15 as needed)
-
- // TODO: support in-memory arguments
-
- unsigned used_FPArgs=0; // how many FP args have been used so far?
- unsigned intArgs[] = {IA64::out0, IA64::out1, IA64::out2, IA64::out3,
- IA64::out4, IA64::out5, IA64::out6, IA64::out7 };
- unsigned FPArgs[] = {IA64::F8, IA64::F9, IA64::F10, IA64::F11,
- IA64::F12, IA64::F13, IA64::F14, IA64::F15 };
+ // TODO: check for integer divides by powers of 2 (or other simple patterns?)
- SDOperand InFlag; // Null incoming flag value.
-
- for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i) {
- unsigned DestReg = 0;
- MVT::ValueType RegTy = N->getOperand(i).getValueType();
- if (RegTy == MVT::i64) {
- assert((i-2) < 8 && "Too many int args");
- DestReg = intArgs[i-2];
- } else {
- assert(MVT::isFloatingPoint(N->getOperand(i).getValueType()) &&
- "Unpromoted integer arg?");
- assert(used_FPArgs < 8 && "Too many fp args");
- DestReg = FPArgs[used_FPArgs++];
- }
+ SDValue TmpPR, TmpPR2;
+ SDValue TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8;
+ SDValue TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15;
+ SDNode *Result;
+
+ // we'll need copies of F0 and F1
+ SDValue F0 = CurDAG->getRegister(IA64::F0, MVT::f64);
+ SDValue F1 = CurDAG->getRegister(IA64::F1, MVT::f64);
- if (N->getOperand(i).getOpcode() != ISD::UNDEF) {
- SDOperand Val = Select(N->getOperand(i));
- Chain = CurDAG->getCopyToReg(Chain, DestReg, Val, InFlag);
- InFlag = Chain.getValue(1);
- CallOperands.push_back(CurDAG->getRegister(DestReg, RegTy));
- // some functions (e.g. printf) want floating point arguments
- // *also* passed as in-memory representations in integer registers
- // this is FORTRAN legacy junk which we don't _always_ need
- // to do, but to be on the safe side, we do.
- if(MVT::isFloatingPoint(N->getOperand(i).getValueType())) {
- assert((i-2) < 8 && "FP args alone would fit, but no int regs left");
- DestReg = intArgs[i-2]; // this FP arg goes in an int reg
- // GETFD takes an FP reg and writes a GP reg
- Chain = CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Val, InFlag);
- // FIXME: this next line is a bit unfortunate
- Chain = CurDAG->getCopyToReg(Chain, DestReg, Chain, InFlag);
- InFlag = Chain.getValue(1);
- CallOperands.push_back(CurDAG->getRegister(DestReg, MVT::i64));
+ // OK, emit some code:
+
+ if(!isFP) {
+ // first, load the inputs into FP regs.
+ TmpF1 =
+ SDValue(CurDAG->getTargetNode(IA64::SETFSIG, dl, MVT::f64, Tmp1), 0);
+ Chain = TmpF1.getValue(1);
+ TmpF2 =
+ SDValue(CurDAG->getTargetNode(IA64::SETFSIG, dl, MVT::f64, Tmp2), 0);
+ Chain = TmpF2.getValue(1);
+
+ // next, convert the inputs to FP
+ if(isSigned) {
+ TmpF3 =
+ SDValue(CurDAG->getTargetNode(IA64::FCVTXF, dl, MVT::f64, TmpF1), 0);
+ Chain = TmpF3.getValue(1);
+ TmpF4 =
+ SDValue(CurDAG->getTargetNode(IA64::FCVTXF, dl, MVT::f64, TmpF2), 0);
+ Chain = TmpF4.getValue(1);
+ } else { // is unsigned
+ TmpF3 =
+ SDValue(CurDAG->getTargetNode(IA64::FCVTXUFS1, dl, MVT::f64, TmpF1),
+ 0);
+ Chain = TmpF3.getValue(1);
+ TmpF4 =
+ SDValue(CurDAG->getTargetNode(IA64::FCVTXUFS1, dl, MVT::f64, TmpF2),
+ 0);
+ Chain = TmpF4.getValue(1);
}
+
+ } else { // this is an FP divide/remainder, so we 'leak' some temp
+ // regs and assign TmpF3=Tmp1, TmpF4=Tmp2
+ TmpF3=Tmp1;
+ TmpF4=Tmp2;
}
- }
-
- // Finally, once everything is in registers to pass to the call, emit the
- // call itself.
- if (InFlag.Val)
- CallOperands.push_back(InFlag); // Strong dep on register copies.
- else
- CallOperands.push_back(Chain); // Weak dep on whatever occurs before
- Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
- CallOperands);
-
-// return Chain; // HACK: err, this means that functions never return anything. need to intergrate this with the code immediately below FIXME XXX
- std::vector<SDOperand> CallResults;
-
- // If the call has results, copy the values out of the ret val registers.
- switch (N->getValueType(0)) {
- default: assert(0 && "Unexpected ret value!");
- case MVT::Other: break;
- case MVT::i64:
- Chain = CurDAG->getCopyFromReg(Chain, IA64::r8, MVT::i64,
- Chain.getValue(1)).getValue(1);
- CallResults.push_back(Chain.getValue(0));
- break;
- case MVT::f64:
- Chain = CurDAG->getCopyFromReg(Chain, IA64::F8, N->getValueType(0),
- Chain.getValue(1)).getValue(1);
- CallResults.push_back(Chain.getValue(0));
- break;
- }
- // restore GP, SP and RP
- Chain = CurDAG->getCopyToReg(Chain, IA64::r1, GPBeforeCall);
- Chain = CurDAG->getCopyToReg(Chain, IA64::r12, SPBeforeCall);
- Chain = CurDAG->getCopyToReg(Chain, IA64::rp, RPBeforeCall);
+ // we start by computing an approximate reciprocal (good to 9 bits?)
+ // note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate)
+ if(isFP)
+ TmpF5 = SDValue(CurDAG->getTargetNode(IA64::FRCPAS0, dl, MVT::f64,
+ MVT::i1, TmpF3, TmpF4), 0);
+ else
+ TmpF5 = SDValue(CurDAG->getTargetNode(IA64::FRCPAS1, dl, MVT::f64,
+ MVT::i1, TmpF3, TmpF4), 0);
+
+ TmpPR = TmpF5.getValue(1);
+ Chain = TmpF5.getValue(2);
+
+ SDValue minusB;
+ if(isModulus) { // for remainders, it'll be handy to have
+ // copies of -input_b
+ minusB = SDValue(CurDAG->getTargetNode(IA64::SUB, dl, MVT::i64,
+ CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2), 0);
+ Chain = minusB.getValue(1);
+ }
+
+ SDValue TmpE0, TmpY1, TmpE1, TmpY2;
+
+ SDValue OpsE0[] = { TmpF4, TmpF5, F1, TmpPR };
+ TmpE0 = SDValue(CurDAG->getTargetNode(IA64::CFNMAS1, dl, MVT::f64,
+ OpsE0, 4), 0);
+ Chain = TmpE0.getValue(1);
+ SDValue OpsY1[] = { TmpF5, TmpE0, TmpF5, TmpPR };
+ TmpY1 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64,
+ OpsY1, 4), 0);
+ Chain = TmpY1.getValue(1);
+ SDValue OpsE1[] = { TmpE0, TmpE0, F0, TmpPR };
+ TmpE1 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64,
+ OpsE1, 4), 0);
+ Chain = TmpE1.getValue(1);
+ SDValue OpsY2[] = { TmpY1, TmpE1, TmpY1, TmpPR };
+ TmpY2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64,
+ OpsY2, 4), 0);
+ Chain = TmpY2.getValue(1);
+
+ if(isFP) { // if this is an FP divide, we finish up here and exit early
+ if(isModulus)
+ assert(0 && "Sorry, try another FORTRAN compiler.");
- CallResults.push_back(Chain);
+ SDValue TmpE2, TmpY3, TmpQ0, TmpR0;
+
+ SDValue OpsE2[] = { TmpE1, TmpE1, F0, TmpPR };
+ TmpE2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64,
+ OpsE2, 4), 0);
+ Chain = TmpE2.getValue(1);
+ SDValue OpsY3[] = { TmpY2, TmpE2, TmpY2, TmpPR };
+ TmpY3 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64,
+ OpsY3, 4), 0);
+ Chain = TmpY3.getValue(1);
+ SDValue OpsQ0[] = { Tmp1, TmpY3, F0, TmpPR };
+ TmpQ0 =
+ SDValue(CurDAG->getTargetNode(IA64::CFMADS1, dl, // double prec!
+ MVT::f64, OpsQ0, 4), 0);
+ Chain = TmpQ0.getValue(1);
+ SDValue OpsR0[] = { Tmp2, TmpQ0, Tmp1, TmpPR };
+ TmpR0 =
+ SDValue(CurDAG->getTargetNode(IA64::CFNMADS1, dl, // double prec!
+ MVT::f64, OpsR0, 4), 0);
+ Chain = TmpR0.getValue(1);
+
+// we want Result to have the same target register as the frcpa, so
+// we two-address hack it. See the comment "for this to work..." on
+// page 48 of Intel application note #245415
+ SDValue Ops[] = { TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR };
+ Result = CurDAG->getTargetNode(IA64::TCFMADS0, dl, // d.p. s0 rndg!
+ MVT::f64, Ops, 5);
+ Chain = SDValue(Result, 1);
+ return Result; // XXX: early exit!
+ } else { // this is *not* an FP divide, so there's a bit left to do:
+
+ SDValue TmpQ2, TmpR2, TmpQ3, TmpQ;
+
+ SDValue OpsQ2[] = { TmpF3, TmpY2, F0, TmpPR };
+ TmpQ2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64,
+ OpsQ2, 4), 0);
+ Chain = TmpQ2.getValue(1);
+ SDValue OpsR2[] = { TmpF4, TmpQ2, TmpF3, TmpPR };
+ TmpR2 = SDValue(CurDAG->getTargetNode(IA64::CFNMAS1, dl, MVT::f64,
+ OpsR2, 4), 0);
+ Chain = TmpR2.getValue(1);
+
+// we want TmpQ3 to have the same target register as the frcpa? maybe we
+// should two-address hack it. See the comment "for this to work..." on page
+// 48 of Intel application note #245415
+ SDValue OpsQ3[] = { TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR };
+ TmpQ3 = SDValue(CurDAG->getTargetNode(IA64::TCFMAS1, dl, MVT::f64,
+ OpsQ3, 5), 0);
+ Chain = TmpQ3.getValue(1);
+
+ // STORY: without these two-address instructions (TCFMAS1 and TCFMADS0)
+ // the FPSWA won't be able to help out in the case of large/tiny
+ // arguments. Other fun bugs may also appear, e.g. 0/x = x, not 0.
+
+ if(isSigned)
+ TmpQ = SDValue(CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1, dl,
+ MVT::f64, TmpQ3), 0);
+ else
+ TmpQ = SDValue(CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1, dl,
+ MVT::f64, TmpQ3), 0);
+
+ Chain = TmpQ.getValue(1);
+
+ if(isModulus) {
+ SDValue FPminusB =
+ SDValue(CurDAG->getTargetNode(IA64::SETFSIG, dl, MVT::f64, minusB),
+ 0);
+ Chain = FPminusB.getValue(1);
+ SDValue Remainder =
+ SDValue(CurDAG->getTargetNode(IA64::XMAL, dl, MVT::f64,
+ TmpQ, FPminusB, TmpF1), 0);
+ Chain = Remainder.getValue(1);
+ Result = CurDAG->getTargetNode(IA64::GETFSIG, dl, MVT::i64, Remainder);
+ Chain = SDValue(Result, 1);
+ } else { // just an integer divide
+ Result = CurDAG->getTargetNode(IA64::GETFSIG, dl, MVT::i64, TmpQ);
+ Chain = SDValue(Result, 1);
+ }
- for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
- CodeGenMap[Op.getValue(i)] = CallResults[i];
-
- return CallResults[Op.ResNo];
+ return Result;
+ } // wasn't an FP divide
}
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
-SDOperand IA64DAGToDAGISel::Select(SDOperand Op) {
- SDNode *N = Op.Val;
- if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
- N->getOpcode() < IA64ISD::FIRST_NUMBER)
- return Op; // Already selected.
-
- // If this has already been converted, use it.
- std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
- if (CGMI != CodeGenMap.end()) return CGMI->second;
-
+SDNode *IA64DAGToDAGISel::Select(SDValue Op) {
+ SDNode *N = Op.getNode();
+ if (N->isMachineOpcode())
+ return NULL; // Already selected.
+ DebugLoc dl = Op.getDebugLoc();
+
switch (N->getOpcode()) {
default: break;
- case ISD::CALL:
- case ISD::TAILCALL: return SelectCALL(Op);
+ case IA64ISD::BRCALL: { // XXX: this is also a hack!
+ SDValue Chain = N->getOperand(0);
+ SDValue InFlag; // Null incoming flag value.
+
+ if(N->getNumOperands()==3) { // we have an incoming chain, callee and flag
+ InFlag = N->getOperand(2);
+ }
+
+ unsigned CallOpcode;
+ SDValue CallOperand;
+
+ // if we can call directly, do so
+ if (GlobalAddressSDNode *GASD =
+ dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
+ CallOpcode = IA64::BRCALL_IPREL_GA;
+ CallOperand = CurDAG->getTargetGlobalAddress(GASD->getGlobal(), MVT::i64);
+ } else if (isa<ExternalSymbolSDNode>(N->getOperand(1))) {
+ // FIXME: we currently NEED this case for correctness, to avoid
+ // "non-pic code with imm reloc.n against dynamic symbol" errors
+ CallOpcode = IA64::BRCALL_IPREL_ES;
+ CallOperand = N->getOperand(1);
+ } else {
+ // otherwise we need to load the function descriptor,
+ // load the branch target (function)'s entry point and GP,
+ // branch (call) then restore the GP
+ SDValue FnDescriptor = N->getOperand(1);
+
+ // load the branch target's entry point [mem] and
+ // GP value [mem+8]
+ SDValue targetEntryPoint=
+ SDValue(CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64, MVT::Other,
+ FnDescriptor, CurDAG->getEntryNode()), 0);
+ Chain = targetEntryPoint.getValue(1);
+ SDValue targetGPAddr=
+ SDValue(CurDAG->getTargetNode(IA64::ADDS, dl, MVT::i64,
+ FnDescriptor,
+ CurDAG->getConstant(8, MVT::i64)), 0);
+ Chain = targetGPAddr.getValue(1);
+ SDValue targetGP =
+ SDValue(CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64,MVT::Other,
+ targetGPAddr, CurDAG->getEntryNode()), 0);
+ Chain = targetGP.getValue(1);
+
+ Chain = CurDAG->getCopyToReg(Chain, dl, IA64::r1, targetGP, InFlag);
+ InFlag = Chain.getValue(1);
+ Chain = CurDAG->getCopyToReg(Chain, dl, IA64::B6,
+ targetEntryPoint, InFlag); // FLAG these?
+ InFlag = Chain.getValue(1);
+
+ CallOperand = CurDAG->getRegister(IA64::B6, MVT::i64);
+ CallOpcode = IA64::BRCALL_INDIRECT;
+ }
-/* todo:
- * case ISD::DYNAMIC_STACKALLOC:
-*/
+ // Finally, once everything is setup, emit the call itself
+ if (InFlag.getNode())
+ Chain = SDValue(CurDAG->getTargetNode(CallOpcode, dl, MVT::Other,
+ MVT::Flag, CallOperand, InFlag), 0);
+ else // there might be no arguments
+ Chain = SDValue(CurDAG->getTargetNode(CallOpcode, dl, MVT::Other,
+ MVT::Flag, CallOperand, Chain), 0);
+ InFlag = Chain.getValue(1);
+
+ std::vector<SDValue> CallResults;
+
+ CallResults.push_back(Chain);
+ CallResults.push_back(InFlag);
+
+ for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
+ ReplaceUses(Op.getValue(i), CallResults[i]);
+ return NULL;
+ }
+
+ case IA64ISD::GETFD: {
+ SDValue Input = N->getOperand(0);
+ return CurDAG->getTargetNode(IA64::GETFD, dl, MVT::i64, Input);
+ }
+
+ case ISD::FDIV:
+ case ISD::SDIV:
+ case ISD::UDIV:
+ case ISD::SREM:
+ case ISD::UREM:
+ return SelectDIV(Op);
+
+ case ISD::TargetConstantFP: {
+ SDValue Chain = CurDAG->getEntryNode(); // this is a constant, so..
+
+ SDValue V;
+ ConstantFPSDNode* N2 = cast<ConstantFPSDNode>(N);
+ if (N2->getValueAPF().isPosZero()) {
+ V = CurDAG->getCopyFromReg(Chain, dl, IA64::F0, MVT::f64);
+ } else if (N2->isExactlyValue(N2->getValueType(0) == MVT::f32 ?
+ APFloat(+1.0f) : APFloat(+1.0))) {
+ V = CurDAG->getCopyFromReg(Chain, dl, IA64::F1, MVT::f64);
+ } else
+ assert(0 && "Unexpected FP constant!");
+
+ ReplaceUses(SDValue(N, 0), V);
+ return 0;
+ }
case ISD::FrameIndex: { // TODO: reduce creepyness
int FI = cast<FrameIndexSDNode>(N)->getIndex();
- if (N->hasOneUse()) {
- CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
- CurDAG->getTargetFrameIndex(FI, MVT::i64));
- return SDOperand(N, 0);
- }
- return CurDAG->getTargetNode(IA64::MOV, MVT::i64,
- CurDAG->getTargetFrameIndex(FI, MVT::i64));
+ if (N->hasOneUse())
+ return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
+ CurDAG->getTargetFrameIndex(FI, MVT::i64));
+ else
+ return CurDAG->getTargetNode(IA64::MOV, dl, MVT::i64,
+ CurDAG->getTargetFrameIndex(FI, MVT::i64));
}
- case ISD::ConstantPool: {
- Constant *C = cast<ConstantPoolSDNode>(N)->get();
- SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
- return CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
- CurDAG->getRegister(IA64::r1, MVT::i64), CPI);
+ case ISD::ConstantPool: { // TODO: nuke the constant pool
+ // (ia64 doesn't need one)
+ ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N);
+ Constant *C = CP->getConstVal();
+ SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64,
+ CP->getAlignment());
+ return CurDAG->getTargetNode(IA64::ADDL_GA, dl, MVT::i64, // ?
+ CurDAG->getRegister(IA64::r1, MVT::i64), CPI);
}
case ISD::GlobalAddress: {
GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
- SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
- SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
- CurDAG->getRegister(IA64::r1, MVT::i64), GA);
- return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
+ SDValue GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
+ SDValue Tmp =
+ SDValue(CurDAG->getTargetNode(IA64::ADDL_GA, dl, MVT::i64,
+ CurDAG->getRegister(IA64::r1,
+ MVT::i64), GA), 0);
+ return CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64, MVT::Other, Tmp,
+ CurDAG->getEntryNode());
}
-
- case ISD::LOAD:
- case ISD::EXTLOAD:
- case ISD::ZEXTLOAD: {
- SDOperand Chain = Select(N->getOperand(0));
- SDOperand Address = Select(N->getOperand(1));
-
- MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ?
- N->getValueType(0) : cast<VTSDNode>(N->getOperand(3))->getVT();
+
+/* XXX
+ case ISD::ExternalSymbol: {
+ SDValue EA = CurDAG->getTargetExternalSymbol(
+ cast<ExternalSymbolSDNode>(N)->getSymbol(),
+ MVT::i64);
+ SDValue Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, dl, MVT::i64,
+ CurDAG->getRegister(IA64::r1,
+ MVT::i64),
+ EA);
+ return CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64, Tmp);
+ }
+*/
+
+ case ISD::LOAD: { // FIXME: load -1, not 1, for bools?
+ LoadSDNode *LD = cast<LoadSDNode>(N);
+ SDValue Chain = LD->getChain();
+ SDValue Address = LD->getBasePtr();
+
+ MVT TypeBeingLoaded = LD->getMemoryVT();
unsigned Opc;
- switch (TypeBeingLoaded) {
- default: N->dump(); assert(0 && "Cannot load this type!");
- // FIXME: bools? case MVT::i1:
+ switch (TypeBeingLoaded.getSimpleVT()) {
+ default:
+#ifndef NDEBUG
+ N->dump(CurDAG);
+#endif
+ assert(0 && "Cannot load this type!");
+ case MVT::i1: { // this is a bool
+ Opc = IA64::LD1; // first we load a byte, then compare for != 0
+ if(N->getValueType(0) == MVT::i1) { // XXX: early exit!
+ return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
+ SDValue(CurDAG->getTargetNode(Opc, dl,
+ MVT::i64,
+ Address), 0),
+ CurDAG->getRegister(IA64::r0, MVT::i64),
+ Chain);
+ }
+ /* otherwise, we want to load a bool into something bigger: LD1
+ will do that for us, so we just fall through */
+ }
case MVT::i8: Opc = IA64::LD1; break;
case MVT::i16: Opc = IA64::LD2; break;
case MVT::i32: Opc = IA64::LD4; break;
case MVT::f64: Opc = IA64::LDF8; break;
}
- CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
- Address, Chain); // TODO: comment this
-
- return SDOperand(N, Op.ResNo);
+ // TODO: comment this
+ return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
+ Address, Chain);
}
- case ISD::TRUNCSTORE:
case ISD::STORE: {
- SDOperand Address = Select(N->getOperand(2));
-
+ StoreSDNode *ST = cast<StoreSDNode>(N);
+ SDValue Address = ST->getBasePtr();
+ SDValue Chain = ST->getChain();
+
unsigned Opc;
- if (N->getOpcode() == ISD::STORE) {
- switch (N->getOperand(1).getValueType()) {
- default: assert(0 && "unknown Type in store");
+ if (ISD::isNON_TRUNCStore(N)) {
+ switch (N->getOperand(1).getValueType().getSimpleVT()) {
+ default: assert(0 && "unknown type in store");
+ case MVT::i1: { // this is a bool
+ Opc = IA64::ST1; // we store either 0 or 1 as a byte
+ // first load zero!
+ SDValue Initial = CurDAG->getCopyFromReg(Chain, dl, IA64::r0, MVT::i64);
+ Chain = Initial.getValue(1);
+ // then load 1 into the same reg iff the predicate to store is 1
+ SDValue Tmp = ST->getValue();
+ Tmp =
+ SDValue(CurDAG->getTargetNode(IA64::TPCADDS, dl, MVT::i64, Initial,
+ CurDAG->getTargetConstant(1,
+ MVT::i64),
+ Tmp), 0);
+ return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
+ }
case MVT::i64: Opc = IA64::ST8; break;
case MVT::f64: Opc = IA64::STF8; break;
- }
- } else { //ISD::TRUNCSTORE
- switch(cast<VTSDNode>(N->getOperand(4))->getVT()) {
- default: assert(0 && "unknown Type in store");
+ }
+ } else { // Truncating store
+ switch(ST->getMemoryVT().getSimpleVT()) {
+ default: assert(0 && "unknown type in truncstore");
case MVT::i8: Opc = IA64::ST1; break;
case MVT::i16: Opc = IA64::ST2; break;
case MVT::i32: Opc = IA64::ST4; break;
}
}
- CurDAG->SelectNodeTo(N, Opc, MVT::Other, Select(N->getOperand(2)),
- Select(N->getOperand(1)), Select(N->getOperand(0)));
- return SDOperand(N, 0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ return CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain);
}
case ISD::BRCOND: {
- SDOperand Chain = Select(N->getOperand(0));
- SDOperand CC = Select(N->getOperand(1));
+ SDValue Chain = N->getOperand(0);
+ SDValue CC = N->getOperand(1);
MachineBasicBlock *Dest =
cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
//FIXME - we do NOT need long branches all the time
- CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC, CurDAG->getBasicBlock(Dest), Chain);
- return SDOperand(N, 0);
+ return CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC,
+ CurDAG->getBasicBlock(Dest), Chain);
}
case ISD::CALLSEQ_START:
case ISD::CALLSEQ_END: {
- int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
+ int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
- IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
- CurDAG->SelectNodeTo(N, Opc, MVT::Other,
- getI64Imm(Amt), Select(N->getOperand(0)));
- return SDOperand(N, 0);
+ IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
+ SDValue N0 = N->getOperand(0);
+ return CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0);
}
- case ISD::RET: {
- SDOperand Chain = Select(N->getOperand(0)); // Token chain.
-
- switch (N->getNumOperands()) {
- default:
- assert(0 && "Unknown return instruction!");
- case 2: {
- SDOperand RetVal = Select(N->getOperand(1));
- switch (RetVal.getValueType()) {
- default: assert(0 && "I don't know how to return this type! (promote?)");
- // FIXME: do I need to add support for bools here?
- // (return '0' or '1' in r8, basically...)
- //
- // FIXME: need to round floats - 80 bits is bad, the tester
- // told me so
- case MVT::i64:
- // we mark r8 as live on exit up above in LowerArguments()
- // BuildMI(BB, IA64::MOV, 1, IA64::r8).addReg(Tmp1);
- Chain = CurDAG->getCopyToReg(Chain, IA64::r8, RetVal);
- break;
- case MVT::f64:
- // we mark F8 as live on exit up above in LowerArguments()
- // BuildMI(BB, IA64::FMOV, 1, IA64::F8).addReg(Tmp1);
- Chain = CurDAG->getCopyToReg(Chain, IA64::F8, RetVal);
- break;
- }
- break;
- }
- case 1:
- break;
- }
-
- // we need to copy VirtGPR (the vreg (to become a real reg)) that holds
- // the output of this function's alloc instruction back into ar.pfs
- // before we return. this copy must not float up above the last
- // outgoing call in this function!!!
- SDOperand AR_PFSVal = CurDAG->getCopyFromReg(Chain, IA64Lowering.VirtGPR,
- MVT::i64);
- Chain = AR_PFSVal.getValue(1);
- Chain = CurDAG->getCopyToReg(Chain, IA64::AR_PFS, AR_PFSVal);
-
- CurDAG->SelectNodeTo(N, IA64::RET, MVT::Other, Chain); // and then just emit a 'ret' instruction
-
- // before returning, restore the ar.pfs register (set by the 'alloc' up top)
- // BuildMI(BB, IA64::MOV, 1).addReg(IA64::AR_PFS).addReg(IA64Lowering.VirtGPR);
- //
- return SDOperand(N, 0);
- }
-
case ISD::BR:
- // FIXME: we don't need long branches all the time!
- CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other, N->getOperand(1),
- Select(N->getOperand(0)));
- return SDOperand(N, 0);
-
+ // FIXME: we don't need long branches all the time!
+ SDValue N0 = N->getOperand(0);
+ return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
+ N->getOperand(1), N0);
}
return SelectCode(Op);
/// createIA64DAGToDAGInstructionSelector - This pass converts a legalized DAG
/// into an IA64-specific DAG, ready for instruction scheduling.
///
-FunctionPass *llvm::createIA64DAGToDAGInstructionSelector(TargetMachine &TM) {
+FunctionPass
+*llvm::createIA64DAGToDAGInstructionSelector(IA64TargetMachine &TM) {
return new IA64DAGToDAGISel(TM);
}
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