#include "llvm/Intrinsics.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
-#include <queue>
-#include <set>
+#include "llvm/Support/raw_ostream.h"
using namespace llvm;
namespace {
/// instructions for SelectionDAG operations.
///
class IA64DAGToDAGISel : public SelectionDAGISel {
- IA64TargetLowering IA64Lowering;
unsigned GlobalBaseReg;
public:
explicit IA64DAGToDAGISel(IA64TargetMachine &TM)
- : SelectionDAGISel(IA64Lowering), IA64Lowering(*TM.getTargetLowering()) {}
+ : SelectionDAGISel(TM) {}
virtual bool runOnFunction(Function &Fn) {
// Make sure we re-emit a set of the global base reg if necessary
DEBUG(BB->dump());
// Select target instructions for the DAG.
- SelectRoot();
+ SelectRoot(*CurDAG);
CurDAG->RemoveDeadNodes();
}
SDValue Chain = N->getOperand(0);
SDValue Tmp1 = N->getOperand(0);
SDValue Tmp2 = N->getOperand(1);
- AddToISelQueue(Chain);
-
- AddToISelQueue(Tmp1);
- AddToISelQueue(Tmp2);
+ DebugLoc dl = N->getDebugLoc();
bool isFP=false;
if(!isFP) {
// first, load the inputs into FP regs.
TmpF1 =
- SDValue(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1), 0);
+ SDValue(CurDAG->getTargetNode(IA64::SETFSIG, dl, MVT::f64, Tmp1), 0);
Chain = TmpF1.getValue(1);
TmpF2 =
- SDValue(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2), 0);
+ SDValue(CurDAG->getTargetNode(IA64::SETFSIG, dl, MVT::f64, Tmp2), 0);
Chain = TmpF2.getValue(1);
// next, convert the inputs to FP
if(isSigned) {
TmpF3 =
- SDValue(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1), 0);
+ SDValue(CurDAG->getTargetNode(IA64::FCVTXF, dl, MVT::f64, TmpF1), 0);
Chain = TmpF3.getValue(1);
TmpF4 =
- SDValue(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2), 0);
+ SDValue(CurDAG->getTargetNode(IA64::FCVTXF, dl, MVT::f64, TmpF2), 0);
Chain = TmpF4.getValue(1);
} else { // is unsigned
TmpF3 =
- SDValue(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1), 0);
+ SDValue(CurDAG->getTargetNode(IA64::FCVTXUFS1, dl, MVT::f64, TmpF1),
+ 0);
Chain = TmpF3.getValue(1);
TmpF4 =
- SDValue(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2), 0);
+ SDValue(CurDAG->getTargetNode(IA64::FCVTXUFS1, dl, MVT::f64, TmpF2),
+ 0);
Chain = TmpF4.getValue(1);
}
// we start by computing an approximate reciprocal (good to 9 bits?)
// note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate)
if(isFP)
- TmpF5 = SDValue(CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1,
- TmpF3, TmpF4), 0);
+ TmpF5 = SDValue(CurDAG->getTargetNode(IA64::FRCPAS0, dl, MVT::f64,
+ MVT::i1, TmpF3, TmpF4), 0);
else
- TmpF5 = SDValue(CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
- TmpF3, TmpF4), 0);
+ TmpF5 = SDValue(CurDAG->getTargetNode(IA64::FRCPAS1, dl, MVT::f64,
+ MVT::i1, TmpF3, TmpF4), 0);
TmpPR = TmpF5.getValue(1);
Chain = TmpF5.getValue(2);
SDValue minusB;
if(isModulus) { // for remainders, it'll be handy to have
// copies of -input_b
- minusB = SDValue(CurDAG->getTargetNode(IA64::SUB, MVT::i64,
+ minusB = SDValue(CurDAG->getTargetNode(IA64::SUB, dl, MVT::i64,
CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2), 0);
Chain = minusB.getValue(1);
}
SDValue TmpE0, TmpY1, TmpE1, TmpY2;
SDValue OpsE0[] = { TmpF4, TmpF5, F1, TmpPR };
- TmpE0 = SDValue(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
+ TmpE0 = SDValue(CurDAG->getTargetNode(IA64::CFNMAS1, dl, MVT::f64,
OpsE0, 4), 0);
Chain = TmpE0.getValue(1);
SDValue OpsY1[] = { TmpF5, TmpE0, TmpF5, TmpPR };
- TmpY1 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+ TmpY1 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64,
OpsY1, 4), 0);
Chain = TmpY1.getValue(1);
SDValue OpsE1[] = { TmpE0, TmpE0, F0, TmpPR };
- TmpE1 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+ TmpE1 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64,
OpsE1, 4), 0);
Chain = TmpE1.getValue(1);
SDValue OpsY2[] = { TmpY1, TmpE1, TmpY1, TmpPR };
- TmpY2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+ TmpY2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64,
OpsY2, 4), 0);
Chain = TmpY2.getValue(1);
SDValue TmpE2, TmpY3, TmpQ0, TmpR0;
SDValue OpsE2[] = { TmpE1, TmpE1, F0, TmpPR };
- TmpE2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+ TmpE2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64,
OpsE2, 4), 0);
Chain = TmpE2.getValue(1);
SDValue OpsY3[] = { TmpY2, TmpE2, TmpY2, TmpPR };
- TmpY3 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+ TmpY3 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64,
OpsY3, 4), 0);
Chain = TmpY3.getValue(1);
SDValue OpsQ0[] = { Tmp1, TmpY3, F0, TmpPR };
TmpQ0 =
- SDValue(CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double prec!
- OpsQ0, 4), 0);
+ SDValue(CurDAG->getTargetNode(IA64::CFMADS1, dl, // double prec!
+ MVT::f64, OpsQ0, 4), 0);
Chain = TmpQ0.getValue(1);
SDValue OpsR0[] = { Tmp2, TmpQ0, Tmp1, TmpPR };
TmpR0 =
- SDValue(CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double prec!
- OpsR0, 4), 0);
+ SDValue(CurDAG->getTargetNode(IA64::CFNMADS1, dl, // double prec!
+ MVT::f64, OpsR0, 4), 0);
Chain = TmpR0.getValue(1);
// we want Result to have the same target register as the frcpa, so
// we two-address hack it. See the comment "for this to work..." on
// page 48 of Intel application note #245415
SDValue Ops[] = { TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR };
- Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg!
- Ops, 5);
+ Result = CurDAG->getTargetNode(IA64::TCFMADS0, dl, // d.p. s0 rndg!
+ MVT::f64, Ops, 5);
Chain = SDValue(Result, 1);
return Result; // XXX: early exit!
} else { // this is *not* an FP divide, so there's a bit left to do:
SDValue TmpQ2, TmpR2, TmpQ3, TmpQ;
SDValue OpsQ2[] = { TmpF3, TmpY2, F0, TmpPR };
- TmpQ2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+ TmpQ2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64,
OpsQ2, 4), 0);
Chain = TmpQ2.getValue(1);
SDValue OpsR2[] = { TmpF4, TmpQ2, TmpF3, TmpPR };
- TmpR2 = SDValue(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
+ TmpR2 = SDValue(CurDAG->getTargetNode(IA64::CFNMAS1, dl, MVT::f64,
OpsR2, 4), 0);
Chain = TmpR2.getValue(1);
// should two-address hack it. See the comment "for this to work..." on page
// 48 of Intel application note #245415
SDValue OpsQ3[] = { TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR };
- TmpQ3 = SDValue(CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64,
+ TmpQ3 = SDValue(CurDAG->getTargetNode(IA64::TCFMAS1, dl, MVT::f64,
OpsQ3, 5), 0);
Chain = TmpQ3.getValue(1);
// arguments. Other fun bugs may also appear, e.g. 0/x = x, not 0.
if(isSigned)
- TmpQ = SDValue(CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1,
+ TmpQ = SDValue(CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1, dl,
MVT::f64, TmpQ3), 0);
else
- TmpQ = SDValue(CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1,
+ TmpQ = SDValue(CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1, dl,
MVT::f64, TmpQ3), 0);
Chain = TmpQ.getValue(1);
if(isModulus) {
SDValue FPminusB =
- SDValue(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, minusB), 0);
+ SDValue(CurDAG->getTargetNode(IA64::SETFSIG, dl, MVT::f64, minusB),
+ 0);
Chain = FPminusB.getValue(1);
SDValue Remainder =
- SDValue(CurDAG->getTargetNode(IA64::XMAL, MVT::f64,
+ SDValue(CurDAG->getTargetNode(IA64::XMAL, dl, MVT::f64,
TmpQ, FPminusB, TmpF1), 0);
Chain = Remainder.getValue(1);
- Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, Remainder);
+ Result = CurDAG->getTargetNode(IA64::GETFSIG, dl, MVT::i64, Remainder);
Chain = SDValue(Result, 1);
} else { // just an integer divide
- Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, TmpQ);
+ Result = CurDAG->getTargetNode(IA64::GETFSIG, dl, MVT::i64, TmpQ);
Chain = SDValue(Result, 1);
}
SDNode *N = Op.getNode();
if (N->isMachineOpcode())
return NULL; // Already selected.
+ DebugLoc dl = Op.getDebugLoc();
switch (N->getOpcode()) {
default: break;
SDValue Chain = N->getOperand(0);
SDValue InFlag; // Null incoming flag value.
- AddToISelQueue(Chain);
if(N->getNumOperands()==3) { // we have an incoming chain, callee and flag
InFlag = N->getOperand(2);
- AddToISelQueue(InFlag);
}
unsigned CallOpcode;
dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
CallOpcode = IA64::BRCALL_IPREL_GA;
CallOperand = CurDAG->getTargetGlobalAddress(GASD->getGlobal(), MVT::i64);
- } else if (isa<SymbolSDNode>(N->getOperand(1))) {
+ } else if (isa<ExternalSymbolSDNode>(N->getOperand(1))) {
// FIXME: we currently NEED this case for correctness, to avoid
// "non-pic code with imm reloc.n against dynamic symbol" errors
CallOpcode = IA64::BRCALL_IPREL_ES;
// load the branch target (function)'s entry point and GP,
// branch (call) then restore the GP
SDValue FnDescriptor = N->getOperand(1);
- AddToISelQueue(FnDescriptor);
// load the branch target's entry point [mem] and
// GP value [mem+8]
SDValue targetEntryPoint=
- SDValue(CurDAG->getTargetNode(IA64::LD8, MVT::i64, MVT::Other,
+ SDValue(CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64, MVT::Other,
FnDescriptor, CurDAG->getEntryNode()), 0);
Chain = targetEntryPoint.getValue(1);
SDValue targetGPAddr=
- SDValue(CurDAG->getTargetNode(IA64::ADDS, MVT::i64,
+ SDValue(CurDAG->getTargetNode(IA64::ADDS, dl, MVT::i64,
FnDescriptor,
CurDAG->getConstant(8, MVT::i64)), 0);
Chain = targetGPAddr.getValue(1);
SDValue targetGP =
- SDValue(CurDAG->getTargetNode(IA64::LD8, MVT::i64,MVT::Other,
+ SDValue(CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64,MVT::Other,
targetGPAddr, CurDAG->getEntryNode()), 0);
Chain = targetGP.getValue(1);
- Chain = CurDAG->getCopyToReg(Chain, IA64::r1, targetGP, InFlag);
+ Chain = CurDAG->getCopyToReg(Chain, dl, IA64::r1, targetGP, InFlag);
InFlag = Chain.getValue(1);
- Chain = CurDAG->getCopyToReg(Chain, IA64::B6,
+ Chain = CurDAG->getCopyToReg(Chain, dl, IA64::B6,
targetEntryPoint, InFlag); // FLAG these?
InFlag = Chain.getValue(1);
// Finally, once everything is setup, emit the call itself
if (InFlag.getNode())
- Chain = SDValue(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
- CallOperand, InFlag), 0);
+ Chain = SDValue(CurDAG->getTargetNode(CallOpcode, dl, MVT::Other,
+ MVT::Flag, CallOperand, InFlag), 0);
else // there might be no arguments
- Chain = SDValue(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
- CallOperand, Chain), 0);
+ Chain = SDValue(CurDAG->getTargetNode(CallOpcode, dl, MVT::Other,
+ MVT::Flag, CallOperand, Chain), 0);
InFlag = Chain.getValue(1);
std::vector<SDValue> CallResults;
case IA64ISD::GETFD: {
SDValue Input = N->getOperand(0);
- AddToISelQueue(Input);
- return CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input);
+ return CurDAG->getTargetNode(IA64::GETFD, dl, MVT::i64, Input);
}
case ISD::FDIV:
SDValue V;
ConstantFPSDNode* N2 = cast<ConstantFPSDNode>(N);
if (N2->getValueAPF().isPosZero()) {
- V = CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64);
+ V = CurDAG->getCopyFromReg(Chain, dl, IA64::F0, MVT::f64);
} else if (N2->isExactlyValue(N2->getValueType(0) == MVT::f32 ?
APFloat(+1.0f) : APFloat(+1.0))) {
- V = CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64);
+ V = CurDAG->getCopyFromReg(Chain, dl, IA64::F1, MVT::f64);
} else
assert(0 && "Unexpected FP constant!");
return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
CurDAG->getTargetFrameIndex(FI, MVT::i64));
else
- return CurDAG->getTargetNode(IA64::MOV, MVT::i64,
+ return CurDAG->getTargetNode(IA64::MOV, dl, MVT::i64,
CurDAG->getTargetFrameIndex(FI, MVT::i64));
}
Constant *C = CP->getConstVal();
SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64,
CP->getAlignment());
- return CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
+ return CurDAG->getTargetNode(IA64::ADDL_GA, dl, MVT::i64, // ?
CurDAG->getRegister(IA64::r1, MVT::i64), CPI);
}
GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
SDValue GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
SDValue Tmp =
- SDValue(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
+ SDValue(CurDAG->getTargetNode(IA64::ADDL_GA, dl, MVT::i64,
CurDAG->getRegister(IA64::r1,
MVT::i64), GA), 0);
- return CurDAG->getTargetNode(IA64::LD8, MVT::i64, MVT::Other, Tmp,
+ return CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64, MVT::Other, Tmp,
CurDAG->getEntryNode());
}
/* XXX
- case ISD::Symbol: {
- SDValue EA = CurDAG->getTargetSymbol(
- cast<SymbolSDNode>(N)->getSymbol(),
+ case ISD::ExternalSymbol: {
+ SDValue EA = CurDAG->getTargetExternalSymbol(
+ cast<ExternalSymbolSDNode>(N)->getSymbol(),
MVT::i64);
- SDValue Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, MVT::i64,
+ SDValue Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, dl, MVT::i64,
CurDAG->getRegister(IA64::r1,
MVT::i64),
EA);
- return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
+ return CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64, Tmp);
}
*/
LoadSDNode *LD = cast<LoadSDNode>(N);
SDValue Chain = LD->getChain();
SDValue Address = LD->getBasePtr();
- AddToISelQueue(Chain);
- AddToISelQueue(Address);
MVT TypeBeingLoaded = LD->getMemoryVT();
unsigned Opc;
case MVT::i1: { // this is a bool
Opc = IA64::LD1; // first we load a byte, then compare for != 0
if(N->getValueType(0) == MVT::i1) { // XXX: early exit!
- return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
- SDValue(CurDAG->getTargetNode(Opc, MVT::i64, Address), 0),
- CurDAG->getRegister(IA64::r0, MVT::i64),
+ return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
+ SDValue(CurDAG->getTargetNode(Opc, dl,
+ MVT::i64,
+ Address), 0),
+ CurDAG->getRegister(IA64::r0, MVT::i64),
Chain);
}
/* otherwise, we want to load a bool into something bigger: LD1
StoreSDNode *ST = cast<StoreSDNode>(N);
SDValue Address = ST->getBasePtr();
SDValue Chain = ST->getChain();
- AddToISelQueue(Address);
- AddToISelQueue(Chain);
unsigned Opc;
if (ISD::isNON_TRUNCStore(N)) {
case MVT::i1: { // this is a bool
Opc = IA64::ST1; // we store either 0 or 1 as a byte
// first load zero!
- SDValue Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64);
+ SDValue Initial = CurDAG->getCopyFromReg(Chain, dl, IA64::r0, MVT::i64);
Chain = Initial.getValue(1);
// then load 1 into the same reg iff the predicate to store is 1
SDValue Tmp = ST->getValue();
- AddToISelQueue(Tmp);
Tmp =
- SDValue(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
+ SDValue(CurDAG->getTargetNode(IA64::TPCADDS, dl, MVT::i64, Initial,
CurDAG->getTargetConstant(1,
MVT::i64),
Tmp), 0);
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
- AddToISelQueue(N1);
- AddToISelQueue(N2);
return CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain);
}
case ISD::BRCOND: {
SDValue Chain = N->getOperand(0);
SDValue CC = N->getOperand(1);
- AddToISelQueue(Chain);
- AddToISelQueue(CC);
MachineBasicBlock *Dest =
cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
//FIXME - we do NOT need long branches all the time
unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
SDValue N0 = N->getOperand(0);
- AddToISelQueue(N0);
return CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0);
}
case ISD::BR:
// FIXME: we don't need long branches all the time!
SDValue N0 = N->getOperand(0);
- AddToISelQueue(N0);
return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
N->getOperand(1), N0);
}
projects / oota-llvm.git / blobdiff