Support for target dependent Hexagon VLIW packetizer.

[oota-llvm.git] / lib / Target / Hexagon / HexagonTargetMachine.cpp

diff --git a/lib/Target/Hexagon/HexagonTargetMachine.cpp b/lib/Target/Hexagon/HexagonTargetMachine.cpp
index 3c858f702cf8a6f405fc302565a95fbb709a1409..0a5b181fff3e7f2852a510497f235ca2c16fd246 100644 (file)
--- a/lib/Target/Hexagon/HexagonTargetMachine.cpp
+++ b/lib/Target/Hexagon/HexagonTargetMachine.cpp
@@ -55,9 +55,7 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
                                            CodeModel::Model CM,
                                            CodeGenOpt::Level OL)
   : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
-    DataLayout("e-p:32:32:32-"
-                "i64:64:64-i32:32:32-i16:16:16-i1:32:32-"
-                "f64:64:64-f32:32:32-a0:0-n32") ,
+    DataLayout("e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-a0:0") ,
     Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this),
     TSInfo(*this),
     FrameLowering(Subtarget),
@@ -102,29 +100,27 @@ TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
 }
 
 bool HexagonPassConfig::addInstSelector() {
-  PM.add(createHexagonRemoveExtendOps(getHexagonTargetMachine()));
-  PM.add(createHexagonISelDag(getHexagonTargetMachine()));
-  PM.add(createHexagonPeephole());
+  PM->add(createHexagonRemoveExtendOps(getHexagonTargetMachine()));
+  PM->add(createHexagonISelDag(getHexagonTargetMachine()));
+  PM->add(createHexagonPeephole());
   return false;
 }
 
 
 bool HexagonPassConfig::addPreRegAlloc() {
   if (!DisableHardwareLoops) {
-    PM.add(createHexagonHardwareLoops());
+    PM->add(createHexagonHardwareLoops());
   }
-
   return false;
 }
 
 bool HexagonPassConfig::addPostRegAlloc() {
-  PM.add(createHexagonCFGOptimizer(getHexagonTargetMachine()));
+  PM->add(createHexagonCFGOptimizer(getHexagonTargetMachine()));
   return true;
 }
 
 
 bool HexagonPassConfig::addPreSched2() {
-  PM.add(createHexagonCopyToCombine());
   addPass(IfConverterID);
   return true;
 }
@@ -132,19 +128,17 @@ bool HexagonPassConfig::addPreSched2() {
 bool HexagonPassConfig::addPreEmitPass() {
 
   if (!DisableHardwareLoops) {
-    PM.add(createHexagonFixupHwLoops());
+    PM->add(createHexagonFixupHwLoops());
   }
 
-  PM.add(createHexagonNewValueJump());
-
   // Expand Spill code for predicate registers.
-  PM.add(createHexagonExpandPredSpillCode(getHexagonTargetMachine()));
+  PM->add(createHexagonExpandPredSpillCode(getHexagonTargetMachine()));
 
   // Split up TFRcondsets into conditional transfers.
-  PM.add(createHexagonSplitTFRCondSets(getHexagonTargetMachine()));
+  PM->add(createHexagonSplitTFRCondSets(getHexagonTargetMachine()));
 
   // Create Packets.
-  PM.add(createHexagonPacketizer());
+  PM->add(createHexagonPacketizer());
 
   return false;
 }