[Hexagon] Replacing cmp* instructions with ones that contain encoding bits.

[oota-llvm.git] / lib / Target / Hexagon / HexagonInstrInfo.cpp

diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp
index a44fd9328002ee980f5c1e9f9ed7169cc47dd25c..8d3916e124884230a1f9701ce7cf8ba1e8d50594 100644 (file)
--- a/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -348,13 +348,13 @@ bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI,
   switch (Opc) {
     case Hexagon::CMPEHexagon4rr:
     case Hexagon::CMPEQri:
   switch (Opc) {
     case Hexagon::CMPEHexagon4rr:
     case Hexagon::CMPEQri:

-    case Hexagon::CMPEQrr:
+    case Hexagon::C2_cmpeq:

     case Hexagon::CMPGT64rr:
     case Hexagon::CMPGTU64rr:
     case Hexagon::CMPGTUri:
     case Hexagon::CMPGT64rr:
     case Hexagon::CMPGTU64rr:
     case Hexagon::CMPGTUri:

-    case Hexagon::CMPGTUrr:
+    case Hexagon::C2_cmpgtu:

     case Hexagon::CMPGTri:
     case Hexagon::CMPGTri:

-    case Hexagon::CMPGTrr:
+    case Hexagon::C2_cmpgt:

       SrcReg = MI->getOperand(1).getReg();
       Mask = ~0;
       break;
       SrcReg = MI->getOperand(1).getReg();
       Mask = ~0;
       break;


@@ -381,11 +381,11 @@ bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI,
   // Set the value/second source register.
   switch (Opc) {
     case Hexagon::CMPEHexagon4rr:
   // Set the value/second source register.
   switch (Opc) {
     case Hexagon::CMPEHexagon4rr:

-    case Hexagon::CMPEQrr:
+    case Hexagon::C2_cmpeq:

     case Hexagon::CMPGT64rr:
     case Hexagon::CMPGTU64rr:
     case Hexagon::CMPGT64rr:
     case Hexagon::CMPGTU64rr:

-    case Hexagon::CMPGTUrr:
-    case Hexagon::CMPGTrr:
+    case Hexagon::C2_cmpgtu:
+    case Hexagon::C2_cmpgt:

     case Hexagon::CMPbEQrr_sbsb_V4:
     case Hexagon::CMPbEQrr_ubub_V4:
     case Hexagon::CMPbGTUrr_V4:
     case Hexagon::CMPbEQrr_sbsb_V4:
     case Hexagon::CMPbEQrr_ubub_V4:
     case Hexagon::CMPbGTUrr_V4:


@@ -1264,11 +1264,11 @@ isSpillPredRegOp(const MachineInstr *MI) const {
 bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const {
   switch (MI->getOpcode()) {
     default: return false;
 bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const {
   switch (MI->getOpcode()) {
     default: return false;

-    case Hexagon::CMPEQrr:
+    case Hexagon::C2_cmpeq:

     case Hexagon::CMPEQri:
     case Hexagon::CMPEQri:

-    case Hexagon::CMPGTrr:
+    case Hexagon::C2_cmpgt:

     case Hexagon::CMPGTri:
     case Hexagon::CMPGTri:

-    case Hexagon::CMPGTUrr:
+    case Hexagon::C2_cmpgtu:

     case Hexagon::CMPGTUri:
       return true;
   }
     case Hexagon::CMPGTUri:
       return true;
   }