Convert assert(0) to llvm_unreachable

[oota-llvm.git] / lib / Target / Hexagon / HexagonInstrInfo.cpp

diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp
index a346cd7c09de5386940339910c0e84d4f1390e26..2cc55785ebc593c8add157b8b8fe8a514b873e28 100644 (file)
--- a/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -1,4 +1,4 @@
-//=- HexagonInstrInfo.cpp - Hexagon Instruction Information -------*- C++ -*-=//
+//===- HexagonInstrInfo.cpp - Hexagon Instruction Information -------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -15,22 +15,19 @@
 #include "HexagonInstrInfo.h"
 #include "HexagonSubtarget.h"
 #include "Hexagon.h"
-#include "llvm/Support/MathExtras.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SmallVector.h"
+#include "llvm/CodeGen/DFAPacketizer.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineMemOperand.h"
 #include "llvm/CodeGen/PseudoSourceValue.h"
+#include "llvm/Support/MathExtras.h"
 #define GET_INSTRINFO_CTOR
-#include "llvm/CodeGen/DFAPacketizer.h"
 #include "HexagonGenInstrInfo.inc"
 #include "HexagonGenDFAPacketizer.inc"
 
-#include <iostream>
-
-
 using namespace llvm;
 
 ///
@@ -386,7 +383,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
           .addFrameIndex(FI).addImm(0)
           .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
   } else {
-    assert(0 && "Unimplemented");
+    llvm_unreachable("Unimplemented");
   }
 }
 
@@ -398,8 +395,7 @@ void HexagonInstrInfo::storeRegToAddr(
                                  const TargetRegisterClass *RC,
                                  SmallVectorImpl<MachineInstr*> &NewMIs) const
 {
-  assert(0 && "Unimplemented");
-  return;
+  llvm_unreachable("Unimplemented");
 }
 
 
@@ -430,7 +426,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
     BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
           .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
   } else {
-    assert(0 && "Can't store this register to stack slot");
+    llvm_unreachable("Can't store this register to stack slot");
   }
 }
 
@@ -439,7 +435,7 @@ void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
                                         SmallVectorImpl<MachineOperand> &Addr,
                                         const TargetRegisterClass *RC,
                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
-  assert(0 && "Unimplemented");
+  llvm_unreachable("Unimplemented");
 }
 
 
@@ -826,7 +822,7 @@ PredicateInstruction(MachineInstr *MI,
     } else if (MO.isImm()) {
       MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
     } else {
-      assert(false && "Unexpected operand type");
+      llvm_unreachable("Unexpected operand type");
     }
   }
 
@@ -1272,10 +1268,8 @@ isValidAutoIncImm(const EVT VT, const int Offset) const {
       return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
               Offset <= Hexagon_MEMB_AUTOINC_MAX);
   }
-  
-  assert(0 && "Not an auto-inc opc!");
 
-  return false;
+  llvm_unreachable("Not an auto-inc opc!");
 }