//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
#include "Alpha.h"
#include "AlphaJITInfo.h"
+#include "AlphaTargetAsmInfo.h"
#include "AlphaTargetMachine.h"
#include "llvm/Module.h"
-#include "llvm/CodeGen/Passes.h"
-#include "llvm/Target/TargetOptions.h"
+#include "llvm/PassManager.h"
#include "llvm/Target/TargetMachineRegistry.h"
-#include "llvm/Transforms/Scalar.h"
-#include "llvm/Support/Debug.h"
-#include <iostream>
+#include "llvm/Support/raw_ostream.h"
using namespace llvm;
-namespace {
- // Register the targets
- RegisterTarget<AlphaTargetMachine> X("alpha", " Alpha (incomplete)");
+// Register the targets
+static RegisterTarget<AlphaTargetMachine> X("alpha", "Alpha [experimental]");
+
+// No assembler printer by default
+AlphaTargetMachine::AsmPrinterCtorFn AlphaTargetMachine::AsmPrinterCtor = 0;
+
+// Force static initialization.
+extern "C" void LLVMInitializeAlphaTarget() { }
+
+const TargetAsmInfo *AlphaTargetMachine::createTargetAsmInfo() const {
+ return new AlphaTargetAsmInfo(*this);
}
unsigned AlphaTargetMachine::getModuleMatchQuality(const Module &M) {
if (TT.size() >= 5 && TT[0] == 'a' && TT[1] == 'l' && TT[2] == 'p' &&
TT[3] == 'h' && TT[4] == 'a')
return 20;
+ // If the target triple is something non-alpha, we don't match.
+ if (!TT.empty()) return 0;
if (M.getEndianness() == Module::LittleEndian &&
M.getPointerSize() == Module::Pointer64)
}
AlphaTargetMachine::AlphaTargetMachine(const Module &M, const std::string &FS)
- : TargetMachine("alpha"),
- DataLayout("alpha", true),
+ : DataLayout("e-f128:128:128"),
FrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0),
JITInfo(*this),
- Subtarget(M, FS)
-{
- DEBUG(std::cerr << "FS is " << FS << "\n");
+ Subtarget(M, FS),
+ TLInfo(*this) {
+ setRelocationModel(Reloc::PIC_);
}
-/// addPassesToEmitFile - Add passes to the specified pass manager to implement
-/// a static compiler for this target.
-///
-bool AlphaTargetMachine::addPassesToEmitFile(PassManager &PM,
- std::ostream &Out,
- CodeGenFileType FileType,
- bool Fast) {
- if (FileType != TargetMachine::AssemblyFile) return true;
-
- PM.add(createLoopStrengthReducePass());
- PM.add(createCFGSimplificationPass());
-
-
- // FIXME: Implement efficient support for garbage collection intrinsics.
- PM.add(createLowerGCPass());
- // FIXME: Implement the invoke/unwind instructions!
- PM.add(createLowerInvokePass());
-
- // Make sure that no unreachable blocks are instruction selected.
- PM.add(createUnreachableBlockEliminationPass());
+//===----------------------------------------------------------------------===//
+// Pass Pipeline Configuration
+//===----------------------------------------------------------------------===//
+bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel) {
PM.add(createAlphaISelDag(*this));
-
- if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(&std::cerr));
-
- PM.add(createRegisterAllocator());
-
- if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(&std::cerr));
-
- PM.add(createPrologEpilogCodeInserter());
-
- // Must run branch selection immediately preceding the asm printer
- //PM.add(createAlphaBranchSelectionPass());
-
- PM.add(createAlphaCodePrinterPass(Out, *this));
-
- PM.add(createMachineCodeDeleter());
return false;
}
-
-void AlphaJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
-
- PM.add(createLoopStrengthReducePass());
- PM.add(createCFGSimplificationPass());
-
- // FIXME: Implement efficient support for garbage collection intrinsics.
- PM.add(createLowerGCPass());
-
- // FIXME: Implement the invoke/unwind instructions!
- PM.add(createLowerInvokePass());
-
- // Make sure that no unreachable blocks are instruction selected.
- PM.add(createUnreachableBlockEliminationPass());
-
- PM.add(createAlphaISelDag(TM));
-
- if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(&std::cerr));
-
- PM.add(createRegisterAllocator());
-
- if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(&std::cerr));
-
- PM.add(createPrologEpilogCodeInserter());
-
+bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel) {
// Must run branch selection immediately preceding the asm printer
- //PM.add(createAlphaBranchSelectionPass());
-
+ PM.add(createAlphaBranchSelectionPass());
+ return false;
}
-
-bool AlphaTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
- MachineCodeEmitter &MCE) {
- PM.add(createAlphaCodeEmitterPass(MCE));
- // Delete machine code for this function
- PM.add(createMachineCodeDeleter());
+bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
+ bool Verbose,
+ raw_ostream &Out) {
+ PM.add(createAlphaLLRPPass(*this));
+ // Output assembly language.
+ assert(AsmPrinterCtor && "AsmPrinter was not linked in");
+ if (AsmPrinterCtor)
+ PM.add(AsmPrinterCtor(Out, *this, Verbose));
return false;
}
+bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
+ bool DumpAsm, MachineCodeEmitter &MCE) {
+ PM.add(createAlphaCodeEmitterPass(*this, MCE));
+ if (DumpAsm) {
+ assert(AsmPrinterCtor && "AsmPrinter was not linked in");
+ if (AsmPrinterCtor)
+ PM.add(AsmPrinterCtor(errs(), *this, true));
+ }
+ return false;
+}
+bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
+ bool DumpAsm, JITCodeEmitter &JCE) {
+ PM.add(createAlphaJITCodeEmitterPass(*this, JCE));
+ if (DumpAsm) {
+ assert(AsmPrinterCtor && "AsmPrinter was not linked in");
+ if (AsmPrinterCtor)
+ PM.add(AsmPrinterCtor(errs(), *this, true));
+ }
+ return false;
+}
+bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
+ bool DumpAsm, ObjectCodeEmitter &OCE) {
+ PM.add(createAlphaObjectCodeEmitterPass(*this, OCE));
+ if (DumpAsm) {
+ assert(AsmPrinterCtor && "AsmPrinter was not linked in");
+ if (AsmPrinterCtor)
+ PM.add(AsmPrinterCtor(errs(), *this, true));
+ }
+ return false;
+}
+bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
+ bool DumpAsm,
+ MachineCodeEmitter &MCE) {
+ return addCodeEmitter(PM, OptLevel, DumpAsm, MCE);
+}
+bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
+ bool DumpAsm,
+ JITCodeEmitter &JCE) {
+ return addCodeEmitter(PM, OptLevel, DumpAsm, JCE);
+}
+bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
+ bool DumpAsm,
+ ObjectCodeEmitter &OCE) {
+ return addCodeEmitter(PM, OptLevel, DumpAsm, OCE);
+}
+
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