//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
#include "Alpha.h"
#include "AlphaJITInfo.h"
+#include "AlphaTargetAsmInfo.h"
#include "AlphaTargetMachine.h"
#include "llvm/Module.h"
-#include "llvm/CodeGen/Passes.h"
-#include "llvm/Target/TargetOptions.h"
+#include "llvm/PassManager.h"
#include "llvm/Target/TargetMachineRegistry.h"
-#include "llvm/Transforms/Scalar.h"
-#include <iostream>
+#include "llvm/Support/FormattedStream.h"
using namespace llvm;
-namespace {
- // Register the targets
- RegisterTarget<AlphaTargetMachine> X("alpha", " Alpha (incomplete)");
-}
-
-namespace llvm {
- cl::opt<bool> EnableAlphaLSR("enable-lsr-for-alpha",
- cl::desc("Enable LSR for Alpha (beta option!)"),
- cl::Hidden);
-}
+// Register the targets
+extern Target TheAlphaTarget;
+static RegisterTarget<AlphaTargetMachine> X(TheAlphaTarget, "alpha",
+ "Alpha [experimental]");
-unsigned AlphaTargetMachine::getModuleMatchQuality(const Module &M) {
- // We strongly match "alpha*".
- std::string TT = M.getTargetTriple();
- if (TT.size() >= 5 && TT[0] == 'a' && TT[1] == 'l' && TT[2] == 'p' &&
- TT[3] == 'h' && TT[4] == 'a')
- return 20;
+// Force static initialization.
+extern "C" void LLVMInitializeAlphaTarget() { }
- if (M.getEndianness() == Module::LittleEndian &&
- M.getPointerSize() == Module::Pointer64)
- return 10; // Weak match
- else if (M.getEndianness() != Module::AnyEndianness ||
- M.getPointerSize() != Module::AnyPointerSize)
- return 0; // Match for some other target
-
- return 0;
+const TargetAsmInfo *AlphaTargetMachine::createTargetAsmInfo() const {
+ return new AlphaTargetAsmInfo(*this);
}
-unsigned AlphaTargetMachine::getJITMatchQuality() {
-#if 0
- return 10;
-#else
- return 0;
-#endif
+AlphaTargetMachine::AlphaTargetMachine(const Target &T, const Module &M,
+ const std::string &FS)
+ : LLVMTargetMachine(T),
+ DataLayout("e-f128:128:128"),
+ FrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0),
+ JITInfo(*this),
+ Subtarget(M, FS),
+ TLInfo(*this) {
+ setRelocationModel(Reloc::PIC_);
}
-AlphaTargetMachine::AlphaTargetMachine( const Module &M, IntrinsicLowering *IL)
- : TargetMachine("alpha", IL, true),
- FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0), //TODO: check these
- JITInfo(*this)
-{}
-
-/// addPassesToEmitFile - Add passes to the specified pass manager to implement
-/// a static compiler for this target.
-///
-bool AlphaTargetMachine::addPassesToEmitFile(PassManager &PM,
- std::ostream &Out,
- CodeGenFileType FileType) {
- if (FileType != TargetMachine::AssemblyFile) return true;
-
- if (EnableAlphaLSR) {
- PM.add(createLoopStrengthReducePass());
- PM.add(createCFGSimplificationPass());
- }
-
- // FIXME: Implement efficient support for garbage collection intrinsics.
- PM.add(createLowerGCPass());
-
- // FIXME: Implement the invoke/unwind instructions!
- PM.add(createLowerInvokePass());
-
- // FIXME: Implement the switch instruction in the instruction selector!
- PM.add(createLowerSwitchPass());
-
- // Make sure that no unreachable blocks are instruction selected.
- PM.add(createUnreachableBlockEliminationPass());
-
- PM.add(createAlphaPatternInstructionSelector(*this));
- if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(&std::cerr));
-
- PM.add(createRegisterAllocator());
-
- if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(&std::cerr));
-
- PM.add(createPrologEpilogCodeInserter());
-
- // Must run branch selection immediately preceding the asm printer
- //PM.add(createAlphaBranchSelectionPass());
-
- PM.add(createAlphaCodePrinterPass(Out, *this));
+//===----------------------------------------------------------------------===//
+// Pass Pipeline Configuration
+//===----------------------------------------------------------------------===//
- PM.add(createMachineCodeDeleter());
+bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel) {
+ PM.add(createAlphaISelDag(*this));
return false;
}
-
-void AlphaJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
-
- if (EnableAlphaLSR) {
- PM.add(createLoopStrengthReducePass());
- PM.add(createCFGSimplificationPass());
- }
-
- // FIXME: Implement efficient support for garbage collection intrinsics.
- PM.add(createLowerGCPass());
-
- // FIXME: Implement the invoke/unwind instructions!
- PM.add(createLowerInvokePass());
-
- // FIXME: Implement the switch instruction in the instruction selector!
- PM.add(createLowerSwitchPass());
-
- // Make sure that no unreachable blocks are instruction selected.
- PM.add(createUnreachableBlockEliminationPass());
-
- PM.add(createAlphaPatternInstructionSelector(TM));
-
- if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(&std::cerr));
-
- PM.add(createRegisterAllocator());
-
- if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(&std::cerr));
-
- PM.add(createPrologEpilogCodeInserter());
-
+bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel) {
// Must run branch selection immediately preceding the asm printer
- //PM.add(createAlphaBranchSelectionPass());
-
+ PM.add(createAlphaBranchSelectionPass());
+ PM.add(createAlphaLLRPPass(*this));
+ return false;
}
-
-bool AlphaTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
- MachineCodeEmitter &MCE) {
- PM.add(createAlphaCodeEmitterPass(MCE));
- // Delete machine code for this function
- PM.add(createMachineCodeDeleter());
+bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
+ bool Verbose,
+ formatted_raw_ostream &Out) {
+ FunctionPass *Printer = getTarget().createAsmPrinter(Out, *this, Verbose);
+ if (!Printer)
+ llvm_report_error("unable to create assembly printer");
+ PM.add(Printer);
+ return false;
+}
+bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
+ MachineCodeEmitter &MCE) {
+ PM.add(createAlphaCodeEmitterPass(*this, MCE));
return false;
}
+bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
+ JITCodeEmitter &JCE) {
+ PM.add(createAlphaJITCodeEmitterPass(*this, JCE));
+ return false;
+}
+bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
+ ObjectCodeEmitter &OCE) {
+ PM.add(createAlphaObjectCodeEmitterPass(*this, OCE));
+ return false;
+}
+bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
+ MachineCodeEmitter &MCE) {
+ return addCodeEmitter(PM, OptLevel, MCE);
+}
+bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
+ JITCodeEmitter &JCE) {
+ return addCodeEmitter(PM, OptLevel, JCE);
+}
+bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
+ ObjectCodeEmitter &OCE) {
+ return addCodeEmitter(PM, OptLevel, OCE);
+}
+
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