Remove attribution from file headers, per discussion on llvmdev.

[oota-llvm.git] / lib / Target / Alpha / AlphaInstrInfo.cpp

diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp
index 71bf5b0e9628b28668dd406593d3dec5fb965c7f..c2eac6c3e0e88128fcc55923c4e9bcb08641fd55 100644 (file)
--- a/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -2,8 +2,8 @@
 //
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
@@ -14,11 +14,12 @@
 #include "Alpha.h"
 #include "AlphaInstrInfo.h"
 #include "AlphaGenInstrInfo.inc"
+#include "llvm/ADT/STLExtras.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 using namespace llvm;
 
 AlphaInstrInfo::AlphaInstrInfo()
-  : TargetInstrInfo(AlphaInsts, sizeof(AlphaInsts)/sizeof(AlphaInsts[0])),
+  : TargetInstrInfo(AlphaInsts, array_lengthof(AlphaInsts)),
     RI(*this) { }
 
 
@@ -33,7 +34,7 @@ bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
       oc == Alpha::CPYSTs) {
     // or r1, r2, r2 
     // cpys(s|t) r1 r2 r2
-    assert(MI.getNumOperands() == 3 &&
+    assert(MI.getNumOperands() >= 3 &&
            MI.getOperand(0).isRegister() &&
            MI.getOperand(1).isRegister() &&
            MI.getOperand(2).isRegister() &&
@@ -99,7 +100,7 @@ static bool isAlphaIntCondCode(unsigned Opcode) {
   }
 }
 
-void AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
+unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
                                   MachineBasicBlock *FBB,
                                   const std::vector<MachineOperand> &Cond)const{
   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
@@ -117,7 +118,7 @@ void AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
       else
         BuildMI(&MBB, get(Alpha::COND_BRANCH_F))
           .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
-    return;
+    return 1;
   }
   
   // Two-way Conditional Branch.
@@ -128,6 +129,7 @@ void AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
     BuildMI(&MBB, get(Alpha::COND_BRANCH_F))
       .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
   BuildMI(&MBB, get(Alpha::BR)).addMBB(FBB);
+  return 2;
 }
 
 static unsigned AlphaRevCondCode(unsigned Opcode) {
@@ -157,14 +159,14 @@ bool AlphaInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TB
                                  std::vector<MachineOperand> &Cond) const {
   // If the block has no terminators, it just falls into the block after it.
   MachineBasicBlock::iterator I = MBB.end();
-  if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode()))
+  if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
     return false;
 
   // Get the last instruction in the block.
   MachineInstr *LastInst = I;
   
   // If there is only one terminator instruction, process it.
-  if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode())) {
+  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
     if (LastInst->getOpcode() == Alpha::BR) {
       TBB = LastInst->getOperand(0).getMachineBasicBlock();
       return false;
@@ -185,7 +187,7 @@ bool AlphaInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TB
 
   // If there are three terminators, we don't know what sort of block this is.
   if (SecondLastInst && I != MBB.begin() &&
-      isTerminatorInstr((--I)->getOpcode()))
+      isUnpredicatedTerminator(--I))
     return true;
   
   // If the block ends with Alpha::BR and Alpha::COND_BRANCH_*, handle it.
@@ -199,32 +201,43 @@ bool AlphaInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TB
     return false;
   }
   
+  // If the block ends with two Alpha::BRs, handle it.  The second one is not
+  // executed, so remove it.
+  if (SecondLastInst->getOpcode() == Alpha::BR && 
+      LastInst->getOpcode() == Alpha::BR) {
+    TBB = SecondLastInst->getOperand(0).getMachineBasicBlock();
+    I = LastInst;
+    I->eraseFromParent();
+    return false;
+  }
+
   // Otherwise, can't handle this.
   return true;
 }
 
-void AlphaInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
+unsigned AlphaInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
   MachineBasicBlock::iterator I = MBB.end();
-  if (I == MBB.begin()) return;
+  if (I == MBB.begin()) return 0;
   --I;
   if (I->getOpcode() != Alpha::BR && 
       I->getOpcode() != Alpha::COND_BRANCH_I &&
       I->getOpcode() != Alpha::COND_BRANCH_F)
-    return;
+    return 0;
   
   // Remove the branch.
   I->eraseFromParent();
   
   I = MBB.end();
 
-  if (I == MBB.begin()) return;
+  if (I == MBB.begin()) return 1;
   --I;
   if (I->getOpcode() != Alpha::COND_BRANCH_I && 
       I->getOpcode() != Alpha::COND_BRANCH_F)
-    return;
+    return 1;
   
   // Remove the branch.
   I->eraseFromParent();
+  return 2;
 }
 
 void AlphaInstrInfo::insertNoop(MachineBasicBlock &MBB, 
@@ -237,6 +250,8 @@ bool AlphaInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
   if (MBB.empty()) return false;
   
   switch (MBB.back().getOpcode()) {
+  case Alpha::RETDAG: // Return.
+  case Alpha::RETDAGp:
   case Alpha::BR:     // Uncond branch.
   case Alpha::JMP:  // Indirect branch.
     return true;