return;
}
- // TBZ/TBNZ should print the register operand as a Wreg if the bit
- // number is < 32.
- if ((Opcode == ARM64::TBNZ || Opcode == ARM64::TBZ) &&
- MI->getOperand(1).getImm() < 32) {
- MCInst newMI = *MI;
- unsigned Reg = MI->getOperand(0).getReg();
- newMI.getOperand(0).setReg(getWRegFromXReg(Reg));
- printInstruction(&newMI, O);
- printAnnotation(O, Annot);
- return;
- }
-
// SBFM/UBFM should print to a nicer aliased form if possible.
if (Opcode == ARM64::SBFMXri || Opcode == ARM64::SBFMWri ||
Opcode == ARM64::UBFMXri || Opcode == ARM64::UBFMWri) {
const MCOperand &Op2 = MI->getOperand(2);
const MCOperand &Op3 = MI->getOperand(3);
+ bool IsSigned = (Opcode == ARM64::SBFMXri || Opcode == ARM64::SBFMWri);
+ bool Is64Bit = (Opcode == ARM64::SBFMXri || Opcode == ARM64::UBFMXri);
if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
- bool IsSigned = (Opcode == ARM64::SBFMXri || Opcode == ARM64::SBFMWri);
- const char *AsmMnemonic = 0;
+ const char *AsmMnemonic = nullptr;
switch (Op3.getImm()) {
default:
break;
case 7:
- AsmMnemonic = IsSigned ? "sxtb" : "uxtb";
+ if (IsSigned)
+ AsmMnemonic = "sxtb";
+ else if (!Is64Bit)
+ AsmMnemonic = "uxtb";
break;
case 15:
- AsmMnemonic = IsSigned ? "sxth" : "uxth";
+ if (IsSigned)
+ AsmMnemonic = "sxth";
+ else if (!Is64Bit)
+ AsmMnemonic = "uxth";
break;
case 31:
- // *xtw is only valid for 64-bit operations.
- if (Opcode == ARM64::SBFMXri || Opcode == ARM64::UBFMXri)
- AsmMnemonic = IsSigned ? "sxtw" : "uxtw";
+ // *xtw is only valid for signed 64-bit operations.
+ if (Is64Bit && IsSigned)
+ AsmMnemonic = "sxtw";
break;
}
// instruction. In all cases the immediate shift amount shift must be in
// the range 0 to (reg.size -1).
if (Op2.isImm() && Op3.isImm()) {
- const char *AsmMnemonic = 0;
+ const char *AsmMnemonic = nullptr;
int shift = 0;
int64_t immr = Op2.getImm();
int64_t imms = Op3.getImm();
return;
}
}
+
+ // SBFIZ/UBFIZ aliases
+ if (Op2.getImm() > Op3.getImm()) {
+ O << '\t' << (IsSigned ? "sbfiz" : "ubfiz") << '\t'
+ << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
+ << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1;
+ printAnnotation(O, Annot);
+ return;
+ }
+
+ // Otherwise SBFX/UBFX is the preferred form
+ O << '\t' << (IsSigned ? "sbfx" : "ubfx") << '\t'
+ << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
+ << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1;
+ printAnnotation(O, Annot);
+ return;
+ }
+
+ if (Opcode == ARM64::BFMXri || Opcode == ARM64::BFMWri) {
+ const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0
+ const MCOperand &Op2 = MI->getOperand(2);
+ int ImmR = MI->getOperand(3).getImm();
+ int ImmS = MI->getOperand(4).getImm();
+
+ // BFI alias
+ if (ImmS < ImmR) {
+ int BitWidth = Opcode == ARM64::BFMXri ? 64 : 32;
+ int LSB = (BitWidth - ImmR) % BitWidth;
+ int Width = ImmS + 1;
+ O << "\tbfi\t" << getRegisterName(Op0.getReg()) << ", "
+ << getRegisterName(Op2.getReg()) << ", #" << LSB << ", #" << Width;
+ printAnnotation(O, Annot);
+ return;
+ }
+
+ int LSB = ImmR;
+ int Width = ImmS - ImmR + 1;
+ // Otherwise BFXIL the preferred form
+ O << "\tbfxil\t"
+ << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op2.getReg())
+ << ", #" << LSB << ", #" << Width;
+ printAnnotation(O, Annot);
+ return;
}
// Symbolic operands for MOVZ, MOVN and MOVK already imply a shift
return;
}
- // ANDS WZR, Wn, #imm ==> TST Wn, #imm
- // ANDS XZR, Xn, #imm ==> TST Xn, #imm
- if (Opcode == ARM64::ANDSWri && MI->getOperand(0).getReg() == ARM64::WZR) {
- O << "\ttst\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
- printLogicalImm32(MI, 2, O);
- return;
- }
- if (Opcode == ARM64::ANDSXri && MI->getOperand(0).getReg() == ARM64::XZR) {
- O << "\ttst\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
- printLogicalImm64(MI, 2, O);
- return;
- }
- // ANDS WZR, Wn, Wm{, lshift #imm} ==> TST Wn{, lshift #imm}
- // ANDS XZR, Xn, Xm{, lshift #imm} ==> TST Xn{, lshift #imm}
- if ((Opcode == ARM64::ANDSWrs && MI->getOperand(0).getReg() == ARM64::WZR) ||
- (Opcode == ARM64::ANDSXrs && MI->getOperand(0).getReg() == ARM64::XZR)) {
- O << "\ttst\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
- printShiftedRegister(MI, 2, O);
- return;
- }
-
- // ORN Wn, WZR, Wm{, lshift #imm} ==> MVN Wn, Wm{, lshift #imm}
- // ORN Xn, XZR, Xm{, lshift #imm} ==> MVN Xn, Xm{, lshift #imm}
- if ((Opcode == ARM64::ORNWrs && MI->getOperand(1).getReg() == ARM64::WZR) ||
- (Opcode == ARM64::ORNXrs && MI->getOperand(1).getReg() == ARM64::XZR)) {
- O << "\tmvn\t" << getRegisterName(MI->getOperand(0).getReg()) << ", ";
- printShiftedRegister(MI, 2, O);
- return;
- }
- // SUBS WZR, Wn, #imm ==> CMP Wn, #imm
- // SUBS XZR, Xn, #imm ==> CMP Xn, #imm
- if ((Opcode == ARM64::SUBSWri && MI->getOperand(0).getReg() == ARM64::WZR) ||
- (Opcode == ARM64::SUBSXri && MI->getOperand(0).getReg() == ARM64::XZR)) {
- O << "\tcmp\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
- printAddSubImm(MI, 2, O);
- return;
- }
- // SUBS WZR, Wn, Wm{, lshift #imm} ==> CMP Wn, Wm{, lshift #imm}
- // SUBS XZR, Xn, Xm{, lshift #imm} ==> CMP Xn, Xm{, lshift #imm}
- if ((Opcode == ARM64::SUBSWrs && MI->getOperand(0).getReg() == ARM64::WZR) ||
- (Opcode == ARM64::SUBSXrs && MI->getOperand(0).getReg() == ARM64::XZR)) {
- O << "\tcmp\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
- printShiftedRegister(MI, 2, O);
- return;
- }
- // SUBS XZR, Xn, Wm, uxtb #imm ==> CMP Xn, uxtb #imm
- // SUBS WZR, Wn, Xm, uxtb #imm ==> CMP Wn, uxtb #imm
- if ((Opcode == ARM64::SUBSXrx && MI->getOperand(0).getReg() == ARM64::XZR) ||
- (Opcode == ARM64::SUBSWrx && MI->getOperand(0).getReg() == ARM64::WZR)) {
- O << "\tcmp\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
- printExtendedRegister(MI, 2, O);
- return;
- }
- // SUBS XZR, Xn, Xm, uxtx #imm ==> CMP Xn, uxtb #imm
- if (Opcode == ARM64::SUBSXrx64 && MI->getOperand(0).getReg() == ARM64::XZR) {
- O << "\tcmp\t" << getRegisterName(MI->getOperand(1).getReg()) << ", "
- << getRegisterName(MI->getOperand(2).getReg());
- printExtend(MI, 3, O);
- return;
- }
-
- // ADDS WZR, Wn, #imm ==> CMN Wn, #imm
- // ADDS XZR, Xn, #imm ==> CMN Xn, #imm
- if ((Opcode == ARM64::ADDSWri && MI->getOperand(0).getReg() == ARM64::WZR) ||
- (Opcode == ARM64::ADDSXri && MI->getOperand(0).getReg() == ARM64::XZR)) {
- O << "\tcmn\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
- printAddSubImm(MI, 2, O);
- return;
- }
- // ADDS WZR, Wn, Wm{, lshift #imm} ==> CMN Wn, Wm{, lshift #imm}
- // ADDS XZR, Xn, Xm{, lshift #imm} ==> CMN Xn, Xm{, lshift #imm}
- if ((Opcode == ARM64::ADDSWrs && MI->getOperand(0).getReg() == ARM64::WZR) ||
- (Opcode == ARM64::ADDSXrs && MI->getOperand(0).getReg() == ARM64::XZR)) {
- O << "\tcmn\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
- printShiftedRegister(MI, 2, O);
- return;
- }
- // ADDS XZR, Xn, Wm, uxtb #imm ==> CMN Xn, uxtb #imm
- if (Opcode == ARM64::ADDSXrx && MI->getOperand(0).getReg() == ARM64::XZR) {
- O << "\tcmn\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
- printExtendedRegister(MI, 2, O);
- return;
- }
- // ADDS XZR, Xn, Xm, uxtx #imm ==> CMN Xn, uxtb #imm
- if (Opcode == ARM64::ADDSXrx64 && MI->getOperand(0).getReg() == ARM64::XZR) {
- O << "\tcmn\t" << getRegisterName(MI->getOperand(1).getReg()) << ", "
- << getRegisterName(MI->getOperand(2).getReg());
- printExtend(MI, 3, O);
- return;
- }
- // ADD WSP, Wn, #0 ==> MOV WSP, Wn
- if (Opcode == ARM64::ADDWri && (MI->getOperand(0).getReg() == ARM64::WSP ||
- MI->getOperand(1).getReg() == ARM64::WSP) &&
- MI->getOperand(2).getImm() == 0 &&
- ARM64_AM::getShiftValue(MI->getOperand(3).getImm()) == 0) {
- O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg())
- << ", " << getRegisterName(MI->getOperand(1).getReg());
- return;
- }
- // ADD XSP, Wn, #0 ==> MOV XSP, Wn
- if (Opcode == ARM64::ADDXri && (MI->getOperand(0).getReg() == ARM64::SP ||
- MI->getOperand(1).getReg() == ARM64::SP) &&
- MI->getOperand(2).getImm() == 0 &&
- ARM64_AM::getShiftValue(MI->getOperand(3).getImm()) == 0) {
- O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg())
- << ", " << getRegisterName(MI->getOperand(1).getReg());
- return;
- }
- // ORR Wn, WZR, Wm ==> MOV Wn, Wm
- if (Opcode == ARM64::ORRWrs && MI->getOperand(1).getReg() == ARM64::WZR &&
- MI->getOperand(3).getImm() == 0) {
- O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg())
- << ", " << getRegisterName(MI->getOperand(2).getReg());
- return;
- }
- // ORR Xn, XZR, Xm ==> MOV Xn, Xm
- if (Opcode == ARM64::ORRXrs && MI->getOperand(1).getReg() == ARM64::XZR &&
- MI->getOperand(3).getImm() == 0) {
- O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg())
- << ", " << getRegisterName(MI->getOperand(2).getReg());
- return;
- }
-
if (!printAliasInstr(MI, O))
printInstruction(MI, O);
unsigned Opcode;
const char *Mnemonic;
const char *Layout;
- int LaneOperand;
+ int ListOperand;
+ bool HasLane;
int NaturalOffset;
};
static LdStNInstrDesc LdStNInstInfo[] = {
- { ARM64::LD1i8, "ld1", ".b", 2, 0 },
- { ARM64::LD1i16, "ld1", ".h", 2, 0 },
- { ARM64::LD1i32, "ld1", ".s", 2, 0 },
- { ARM64::LD1i64, "ld1", ".d", 2, 0 },
- { ARM64::LD1i8_POST, "ld1", ".b", 2, 1 },
- { ARM64::LD1i16_POST, "ld1", ".h", 2, 2 },
- { ARM64::LD1i32_POST, "ld1", ".s", 2, 4 },
- { ARM64::LD1i64_POST, "ld1", ".d", 2, 8 },
- { ARM64::LD1Rv16b, "ld1r", ".16b", 0, 0 },
- { ARM64::LD1Rv8h, "ld1r", ".8h", 0, 0 },
- { ARM64::LD1Rv4s, "ld1r", ".4s", 0, 0 },
- { ARM64::LD1Rv2d, "ld1r", ".2d", 0, 0 },
- { ARM64::LD1Rv8b, "ld1r", ".8b", 0, 0 },
- { ARM64::LD1Rv4h, "ld1r", ".4h", 0, 0 },
- { ARM64::LD1Rv2s, "ld1r", ".2s", 0, 0 },
- { ARM64::LD1Rv1d, "ld1r", ".1d", 0, 0 },
- { ARM64::LD1Rv16b_POST, "ld1r", ".16b", 0, 1 },
- { ARM64::LD1Rv8h_POST, "ld1r", ".8h", 0, 2 },
- { ARM64::LD1Rv4s_POST, "ld1r", ".4s", 0, 4 },
- { ARM64::LD1Rv2d_POST, "ld1r", ".2d", 0, 8 },
- { ARM64::LD1Rv8b_POST, "ld1r", ".8b", 0, 1 },
- { ARM64::LD1Rv4h_POST, "ld1r", ".4h", 0, 2 },
- { ARM64::LD1Rv2s_POST, "ld1r", ".2s", 0, 4 },
- { ARM64::LD1Rv1d_POST, "ld1r", ".1d", 0, 8 },
- { ARM64::LD1Onev16b, "ld1", ".16b", 0, 0 },
- { ARM64::LD1Onev8h, "ld1", ".8h", 0, 0 },
- { ARM64::LD1Onev4s, "ld1", ".4s", 0, 0 },
- { ARM64::LD1Onev2d, "ld1", ".2d", 0, 0 },
- { ARM64::LD1Onev8b, "ld1", ".8b", 0, 0 },
- { ARM64::LD1Onev4h, "ld1", ".4h", 0, 0 },
- { ARM64::LD1Onev2s, "ld1", ".2s", 0, 0 },
- { ARM64::LD1Onev1d, "ld1", ".1d", 0, 0 },
- { ARM64::LD1Onev16b_POST, "ld1", ".16b", 0, 16 },
- { ARM64::LD1Onev8h_POST, "ld1", ".8h", 0, 16 },
- { ARM64::LD1Onev4s_POST, "ld1", ".4s", 0, 16 },
- { ARM64::LD1Onev2d_POST, "ld1", ".2d", 0, 16 },
- { ARM64::LD1Onev8b_POST, "ld1", ".8b", 0, 8 },
- { ARM64::LD1Onev4h_POST, "ld1", ".4h", 0, 8 },
- { ARM64::LD1Onev2s_POST, "ld1", ".2s", 0, 8 },
- { ARM64::LD1Onev1d_POST, "ld1", ".1d", 0, 8 },
- { ARM64::LD1Twov16b, "ld1", ".16b", 0, 0 },
- { ARM64::LD1Twov8h, "ld1", ".8h", 0, 0 },
- { ARM64::LD1Twov4s, "ld1", ".4s", 0, 0 },
- { ARM64::LD1Twov2d, "ld1", ".2d", 0, 0 },
- { ARM64::LD1Twov8b, "ld1", ".8b", 0, 0 },
- { ARM64::LD1Twov4h, "ld1", ".4h", 0, 0 },
- { ARM64::LD1Twov2s, "ld1", ".2s", 0, 0 },
- { ARM64::LD1Twov1d, "ld1", ".1d", 0, 0 },
- { ARM64::LD1Twov16b_POST, "ld1", ".16b", 0, 32 },
- { ARM64::LD1Twov8h_POST, "ld1", ".8h", 0, 32 },
- { ARM64::LD1Twov4s_POST, "ld1", ".4s", 0, 32 },
- { ARM64::LD1Twov2d_POST, "ld1", ".2d", 0, 32 },
- { ARM64::LD1Twov8b_POST, "ld1", ".8b", 0, 16 },
- { ARM64::LD1Twov4h_POST, "ld1", ".4h", 0, 16 },
- { ARM64::LD1Twov2s_POST, "ld1", ".2s", 0, 16 },
- { ARM64::LD1Twov1d_POST, "ld1", ".1d", 0, 16 },
- { ARM64::LD1Threev16b, "ld1", ".16b", 0, 0 },
- { ARM64::LD1Threev8h, "ld1", ".8h", 0, 0 },
- { ARM64::LD1Threev4s, "ld1", ".4s", 0, 0 },
- { ARM64::LD1Threev2d, "ld1", ".2d", 0, 0 },
- { ARM64::LD1Threev8b, "ld1", ".8b", 0, 0 },
- { ARM64::LD1Threev4h, "ld1", ".4h", 0, 0 },
- { ARM64::LD1Threev2s, "ld1", ".2s", 0, 0 },
- { ARM64::LD1Threev1d, "ld1", ".1d", 0, 0 },
- { ARM64::LD1Threev16b_POST, "ld1", ".16b", 0, 48 },
- { ARM64::LD1Threev8h_POST, "ld1", ".8h", 0, 48 },
- { ARM64::LD1Threev4s_POST, "ld1", ".4s", 0, 48 },
- { ARM64::LD1Threev2d_POST, "ld1", ".2d", 0, 48 },
- { ARM64::LD1Threev8b_POST, "ld1", ".8b", 0, 24 },
- { ARM64::LD1Threev4h_POST, "ld1", ".4h", 0, 24 },
- { ARM64::LD1Threev2s_POST, "ld1", ".2s", 0, 24 },
- { ARM64::LD1Threev1d_POST, "ld1", ".1d", 0, 24 },
- { ARM64::LD1Fourv16b, "ld1", ".16b", 0, 0 },
- { ARM64::LD1Fourv8h, "ld1", ".8h", 0, 0 },
- { ARM64::LD1Fourv4s, "ld1", ".4s", 0, 0 },
- { ARM64::LD1Fourv2d, "ld1", ".2d", 0, 0 },
- { ARM64::LD1Fourv8b, "ld1", ".8b", 0, 0 },
- { ARM64::LD1Fourv4h, "ld1", ".4h", 0, 0 },
- { ARM64::LD1Fourv2s, "ld1", ".2s", 0, 0 },
- { ARM64::LD1Fourv1d, "ld1", ".1d", 0, 0 },
- { ARM64::LD1Fourv16b_POST, "ld1", ".16b", 0, 64 },
- { ARM64::LD1Fourv8h_POST, "ld1", ".8h", 0, 64 },
- { ARM64::LD1Fourv4s_POST, "ld1", ".4s", 0, 64 },
- { ARM64::LD1Fourv2d_POST, "ld1", ".2d", 0, 64 },
- { ARM64::LD1Fourv8b_POST, "ld1", ".8b", 0, 32 },
- { ARM64::LD1Fourv4h_POST, "ld1", ".4h", 0, 32 },
- { ARM64::LD1Fourv2s_POST, "ld1", ".2s", 0, 32 },
- { ARM64::LD1Fourv1d_POST, "ld1", ".1d", 0, 32 },
- { ARM64::LD2i8, "ld2", ".b", 2, 0 },
- { ARM64::LD2i16, "ld2", ".h", 2, 0 },
- { ARM64::LD2i32, "ld2", ".s", 2, 0 },
- { ARM64::LD2i64, "ld2", ".d", 2, 0 },
- { ARM64::LD2i8_POST, "ld2", ".b", 2, 2 },
- { ARM64::LD2i16_POST, "ld2", ".h", 2, 4 },
- { ARM64::LD2i32_POST, "ld2", ".s", 2, 8 },
- { ARM64::LD2i64_POST, "ld2", ".d", 2, 16 },
- { ARM64::LD2Rv16b, "ld2r", ".16b", 0, 0 },
- { ARM64::LD2Rv8h, "ld2r", ".8h", 0, 0 },
- { ARM64::LD2Rv4s, "ld2r", ".4s", 0, 0 },
- { ARM64::LD2Rv2d, "ld2r", ".2d", 0, 0 },
- { ARM64::LD2Rv8b, "ld2r", ".8b", 0, 0 },
- { ARM64::LD2Rv4h, "ld2r", ".4h", 0, 0 },
- { ARM64::LD2Rv2s, "ld2r", ".2s", 0, 0 },
- { ARM64::LD2Rv1d, "ld2r", ".1d", 0, 0 },
- { ARM64::LD2Rv16b_POST, "ld2r", ".16b", 0, 2 },
- { ARM64::LD2Rv8h_POST, "ld2r", ".8h", 0, 4 },
- { ARM64::LD2Rv4s_POST, "ld2r", ".4s", 0, 8 },
- { ARM64::LD2Rv2d_POST, "ld2r", ".2d", 0, 16 },
- { ARM64::LD2Rv8b_POST, "ld2r", ".8b", 0, 2 },
- { ARM64::LD2Rv4h_POST, "ld2r", ".4h", 0, 4 },
- { ARM64::LD2Rv2s_POST, "ld2r", ".2s", 0, 8 },
- { ARM64::LD2Rv1d_POST, "ld2r", ".1d", 0, 16 },
- { ARM64::LD2Twov16b, "ld2", ".16b", 0, 0 },
- { ARM64::LD2Twov8h, "ld2", ".8h", 0, 0 },
- { ARM64::LD2Twov4s, "ld2", ".4s", 0, 0 },
- { ARM64::LD2Twov2d, "ld2", ".2d", 0, 0 },
- { ARM64::LD2Twov8b, "ld2", ".8b", 0, 0 },
- { ARM64::LD2Twov4h, "ld2", ".4h", 0, 0 },
- { ARM64::LD2Twov2s, "ld2", ".2s", 0, 0 },
- { ARM64::LD2Twov16b_POST, "ld2", ".16b", 0, 32 },
- { ARM64::LD2Twov8h_POST, "ld2", ".8h", 0, 32 },
- { ARM64::LD2Twov4s_POST, "ld2", ".4s", 0, 32 },
- { ARM64::LD2Twov2d_POST, "ld2", ".2d", 0, 32 },
- { ARM64::LD2Twov8b_POST, "ld2", ".8b", 0, 16 },
- { ARM64::LD2Twov4h_POST, "ld2", ".4h", 0, 16 },
- { ARM64::LD2Twov2s_POST, "ld2", ".2s", 0, 16 },
- { ARM64::LD3i8, "ld3", ".b", 2, 0 },
- { ARM64::LD3i16, "ld3", ".h", 2, 0 },
- { ARM64::LD3i32, "ld3", ".s", 2, 0 },
- { ARM64::LD3i64, "ld3", ".d", 2, 0 },
- { ARM64::LD3i8_POST, "ld3", ".b", 2, 3 },
- { ARM64::LD3i16_POST, "ld3", ".h", 2, 6 },
- { ARM64::LD3i32_POST, "ld3", ".s", 2, 12 },
- { ARM64::LD3i64_POST, "ld3", ".d", 2, 24 },
- { ARM64::LD3Rv16b, "ld3r", ".16b", 0, 0 },
- { ARM64::LD3Rv8h, "ld3r", ".8h", 0, 0 },
- { ARM64::LD3Rv4s, "ld3r", ".4s", 0, 0 },
- { ARM64::LD3Rv2d, "ld3r", ".2d", 0, 0 },
- { ARM64::LD3Rv8b, "ld3r", ".8b", 0, 0 },
- { ARM64::LD3Rv4h, "ld3r", ".4h", 0, 0 },
- { ARM64::LD3Rv2s, "ld3r", ".2s", 0, 0 },
- { ARM64::LD3Rv1d, "ld3r", ".1d", 0, 0 },
- { ARM64::LD3Rv16b_POST, "ld3r", ".16b", 0, 3 },
- { ARM64::LD3Rv8h_POST, "ld3r", ".8h", 0, 6 },
- { ARM64::LD3Rv4s_POST, "ld3r", ".4s", 0, 12 },
- { ARM64::LD3Rv2d_POST, "ld3r", ".2d", 0, 24 },
- { ARM64::LD3Rv8b_POST, "ld3r", ".8b", 0, 3 },
- { ARM64::LD3Rv4h_POST, "ld3r", ".4h", 0, 6 },
- { ARM64::LD3Rv2s_POST, "ld3r", ".2s", 0, 12 },
- { ARM64::LD3Rv1d_POST, "ld3r", ".1d", 0, 24 },
- { ARM64::LD3Threev16b, "ld3", ".16b", 0, 0 },
- { ARM64::LD3Threev8h, "ld3", ".8h", 0, 0 },
- { ARM64::LD3Threev4s, "ld3", ".4s", 0, 0 },
- { ARM64::LD3Threev2d, "ld3", ".2d", 0, 0 },
- { ARM64::LD3Threev8b, "ld3", ".8b", 0, 0 },
- { ARM64::LD3Threev4h, "ld3", ".4h", 0, 0 },
- { ARM64::LD3Threev2s, "ld3", ".2s", 0, 0 },
- { ARM64::LD3Threev16b_POST, "ld3", ".16b", 0, 48 },
- { ARM64::LD3Threev8h_POST, "ld3", ".8h", 0, 48 },
- { ARM64::LD3Threev4s_POST, "ld3", ".4s", 0, 48 },
- { ARM64::LD3Threev2d_POST, "ld3", ".2d", 0, 48 },
- { ARM64::LD3Threev8b_POST, "ld3", ".8b", 0, 24 },
- { ARM64::LD3Threev4h_POST, "ld3", ".4h", 0, 24 },
- { ARM64::LD3Threev2s_POST, "ld3", ".2s", 0, 24 },
- { ARM64::LD4i8, "ld4", ".b", 2, 0 },
- { ARM64::LD4i16, "ld4", ".h", 2, 0 },
- { ARM64::LD4i32, "ld4", ".s", 2, 0 },
- { ARM64::LD4i64, "ld4", ".d", 2, 0 },
- { ARM64::LD4i8_POST, "ld4", ".b", 2, 4 },
- { ARM64::LD4i16_POST, "ld4", ".h", 2, 8 },
- { ARM64::LD4i32_POST, "ld4", ".s", 2, 16 },
- { ARM64::LD4i64_POST, "ld4", ".d", 2, 32 },
- { ARM64::LD4Rv16b, "ld4r", ".16b", 0, 0 },
- { ARM64::LD4Rv8h, "ld4r", ".8h", 0, 0 },
- { ARM64::LD4Rv4s, "ld4r", ".4s", 0, 0 },
- { ARM64::LD4Rv2d, "ld4r", ".2d", 0, 0 },
- { ARM64::LD4Rv8b, "ld4r", ".8b", 0, 0 },
- { ARM64::LD4Rv4h, "ld4r", ".4h", 0, 0 },
- { ARM64::LD4Rv2s, "ld4r", ".2s", 0, 0 },
- { ARM64::LD4Rv1d, "ld4r", ".1d", 0, 0 },
- { ARM64::LD4Rv16b_POST, "ld4r", ".16b", 0, 4 },
- { ARM64::LD4Rv8h_POST, "ld4r", ".8h", 0, 8 },
- { ARM64::LD4Rv4s_POST, "ld4r", ".4s", 0, 16 },
- { ARM64::LD4Rv2d_POST, "ld4r", ".2d", 0, 32 },
- { ARM64::LD4Rv8b_POST, "ld4r", ".8b", 0, 4 },
- { ARM64::LD4Rv4h_POST, "ld4r", ".4h", 0, 8 },
- { ARM64::LD4Rv2s_POST, "ld4r", ".2s", 0, 16 },
- { ARM64::LD4Rv1d_POST, "ld4r", ".1d", 0, 32 },
- { ARM64::LD4Fourv16b, "ld4", ".16b", 0, 0 },
- { ARM64::LD4Fourv8h, "ld4", ".8h", 0, 0 },
- { ARM64::LD4Fourv4s, "ld4", ".4s", 0, 0 },
- { ARM64::LD4Fourv2d, "ld4", ".2d", 0, 0 },
- { ARM64::LD4Fourv8b, "ld4", ".8b", 0, 0 },
- { ARM64::LD4Fourv4h, "ld4", ".4h", 0, 0 },
- { ARM64::LD4Fourv2s, "ld4", ".2s", 0, 0 },
- { ARM64::LD4Fourv16b_POST, "ld4", ".16b", 0, 64 },
- { ARM64::LD4Fourv8h_POST, "ld4", ".8h", 0, 64 },
- { ARM64::LD4Fourv4s_POST, "ld4", ".4s", 0, 64 },
- { ARM64::LD4Fourv2d_POST, "ld4", ".2d", 0, 64 },
- { ARM64::LD4Fourv8b_POST, "ld4", ".8b", 0, 32 },
- { ARM64::LD4Fourv4h_POST, "ld4", ".4h", 0, 32 },
- { ARM64::LD4Fourv2s_POST, "ld4", ".2s", 0, 32 },
- { ARM64::ST1i8, "st1", ".b", 1, 0 },
- { ARM64::ST1i16, "st1", ".h", 1, 0 },
- { ARM64::ST1i32, "st1", ".s", 1, 0 },
- { ARM64::ST1i64, "st1", ".d", 1, 0 },
- { ARM64::ST1i8_POST, "st1", ".b", 1, 1 },
- { ARM64::ST1i16_POST, "st1", ".h", 1, 2 },
- { ARM64::ST1i32_POST, "st1", ".s", 1, 4 },
- { ARM64::ST1i64_POST, "st1", ".d", 1, 8 },
- { ARM64::ST1Onev16b, "st1", ".16b", 0, 0 },
- { ARM64::ST1Onev8h, "st1", ".8h", 0, 0 },
- { ARM64::ST1Onev4s, "st1", ".4s", 0, 0 },
- { ARM64::ST1Onev2d, "st1", ".2d", 0, 0 },
- { ARM64::ST1Onev8b, "st1", ".8b", 0, 0 },
- { ARM64::ST1Onev4h, "st1", ".4h", 0, 0 },
- { ARM64::ST1Onev2s, "st1", ".2s", 0, 0 },
- { ARM64::ST1Onev1d, "st1", ".1d", 0, 0 },
- { ARM64::ST1Onev16b_POST, "st1", ".16b", 0, 16 },
- { ARM64::ST1Onev8h_POST, "st1", ".8h", 0, 16 },
- { ARM64::ST1Onev4s_POST, "st1", ".4s", 0, 16 },
- { ARM64::ST1Onev2d_POST, "st1", ".2d", 0, 16 },
- { ARM64::ST1Onev8b_POST, "st1", ".8b", 0, 8 },
- { ARM64::ST1Onev4h_POST, "st1", ".4h", 0, 8 },
- { ARM64::ST1Onev2s_POST, "st1", ".2s", 0, 8 },
- { ARM64::ST1Onev1d_POST, "st1", ".1d", 0, 8 },
- { ARM64::ST1Twov16b, "st1", ".16b", 0, 0 },
- { ARM64::ST1Twov8h, "st1", ".8h", 0, 0 },
- { ARM64::ST1Twov4s, "st1", ".4s", 0, 0 },
- { ARM64::ST1Twov2d, "st1", ".2d", 0, 0 },
- { ARM64::ST1Twov8b, "st1", ".8b", 0, 0 },
- { ARM64::ST1Twov4h, "st1", ".4h", 0, 0 },
- { ARM64::ST1Twov2s, "st1", ".2s", 0, 0 },
- { ARM64::ST1Twov1d, "st1", ".1d", 0, 0 },
- { ARM64::ST1Twov16b_POST, "st1", ".16b", 0, 32 },
- { ARM64::ST1Twov8h_POST, "st1", ".8h", 0, 32 },
- { ARM64::ST1Twov4s_POST, "st1", ".4s", 0, 32 },
- { ARM64::ST1Twov2d_POST, "st1", ".2d", 0, 32 },
- { ARM64::ST1Twov8b_POST, "st1", ".8b", 0, 16 },
- { ARM64::ST1Twov4h_POST, "st1", ".4h", 0, 16 },
- { ARM64::ST1Twov2s_POST, "st1", ".2s", 0, 16 },
- { ARM64::ST1Twov1d_POST, "st1", ".1d", 0, 16 },
- { ARM64::ST1Threev16b, "st1", ".16b", 0, 0 },
- { ARM64::ST1Threev8h, "st1", ".8h", 0, 0 },
- { ARM64::ST1Threev4s, "st1", ".4s", 0, 0 },
- { ARM64::ST1Threev2d, "st1", ".2d", 0, 0 },
- { ARM64::ST1Threev8b, "st1", ".8b", 0, 0 },
- { ARM64::ST1Threev4h, "st1", ".4h", 0, 0 },
- { ARM64::ST1Threev2s, "st1", ".2s", 0, 0 },
- { ARM64::ST1Threev1d, "st1", ".1d", 0, 0 },
- { ARM64::ST1Threev16b_POST, "st1", ".16b", 0, 48 },
- { ARM64::ST1Threev8h_POST, "st1", ".8h", 0, 48 },
- { ARM64::ST1Threev4s_POST, "st1", ".4s", 0, 48 },
- { ARM64::ST1Threev2d_POST, "st1", ".2d", 0, 48 },
- { ARM64::ST1Threev8b_POST, "st1", ".8b", 0, 24 },
- { ARM64::ST1Threev4h_POST, "st1", ".4h", 0, 24 },
- { ARM64::ST1Threev2s_POST, "st1", ".2s", 0, 24 },
- { ARM64::ST1Threev1d_POST, "st1", ".1d", 0, 24 },
- { ARM64::ST1Fourv16b, "st1", ".16b", 0, 0 },
- { ARM64::ST1Fourv8h, "st1", ".8h", 0, 0 },
- { ARM64::ST1Fourv4s, "st1", ".4s", 0, 0 },
- { ARM64::ST1Fourv2d, "st1", ".2d", 0, 0 },
- { ARM64::ST1Fourv8b, "st1", ".8b", 0, 0 },
- { ARM64::ST1Fourv4h, "st1", ".4h", 0, 0 },
- { ARM64::ST1Fourv2s, "st1", ".2s", 0, 0 },
- { ARM64::ST1Fourv1d, "st1", ".1d", 0, 0 },
- { ARM64::ST1Fourv16b_POST, "st1", ".16b", 0, 64 },
- { ARM64::ST1Fourv8h_POST, "st1", ".8h", 0, 64 },
- { ARM64::ST1Fourv4s_POST, "st1", ".4s", 0, 64 },
- { ARM64::ST1Fourv2d_POST, "st1", ".2d", 0, 64 },
- { ARM64::ST1Fourv8b_POST, "st1", ".8b", 0, 32 },
- { ARM64::ST1Fourv4h_POST, "st1", ".4h", 0, 32 },
- { ARM64::ST1Fourv2s_POST, "st1", ".2s", 0, 32 },
- { ARM64::ST1Fourv1d_POST, "st1", ".1d", 0, 32 },
- { ARM64::ST2i8, "st2", ".b", 1, 0 },
- { ARM64::ST2i16, "st2", ".h", 1, 0 },
- { ARM64::ST2i32, "st2", ".s", 1, 0 },
- { ARM64::ST2i64, "st2", ".d", 1, 0 },
- { ARM64::ST2i8_POST, "st2", ".b", 1, 2 },
- { ARM64::ST2i16_POST, "st2", ".h", 1, 4 },
- { ARM64::ST2i32_POST, "st2", ".s", 1, 8 },
- { ARM64::ST2i64_POST, "st2", ".d", 1, 16 },
- { ARM64::ST2Twov16b, "st2", ".16b", 0, 0 },
- { ARM64::ST2Twov8h, "st2", ".8h", 0, 0 },
- { ARM64::ST2Twov4s, "st2", ".4s", 0, 0 },
- { ARM64::ST2Twov2d, "st2", ".2d", 0, 0 },
- { ARM64::ST2Twov8b, "st2", ".8b", 0, 0 },
- { ARM64::ST2Twov4h, "st2", ".4h", 0, 0 },
- { ARM64::ST2Twov2s, "st2", ".2s", 0, 0 },
- { ARM64::ST2Twov16b_POST, "st2", ".16b", 0, 32 },
- { ARM64::ST2Twov8h_POST, "st2", ".8h", 0, 32 },
- { ARM64::ST2Twov4s_POST, "st2", ".4s", 0, 32 },
- { ARM64::ST2Twov2d_POST, "st2", ".2d", 0, 32 },
- { ARM64::ST2Twov8b_POST, "st2", ".8b", 0, 16 },
- { ARM64::ST2Twov4h_POST, "st2", ".4h", 0, 16 },
- { ARM64::ST2Twov2s_POST, "st2", ".2s", 0, 16 },
- { ARM64::ST3i8, "st3", ".b", 1, 0 },
- { ARM64::ST3i16, "st3", ".h", 1, 0 },
- { ARM64::ST3i32, "st3", ".s", 1, 0 },
- { ARM64::ST3i64, "st3", ".d", 1, 0 },
- { ARM64::ST3i8_POST, "st3", ".b", 1, 3 },
- { ARM64::ST3i16_POST, "st3", ".h", 1, 6 },
- { ARM64::ST3i32_POST, "st3", ".s", 1, 12 },
- { ARM64::ST3i64_POST, "st3", ".d", 1, 24 },
- { ARM64::ST3Threev16b, "st3", ".16b", 0, 0 },
- { ARM64::ST3Threev8h, "st3", ".8h", 0, 0 },
- { ARM64::ST3Threev4s, "st3", ".4s", 0, 0 },
- { ARM64::ST3Threev2d, "st3", ".2d", 0, 0 },
- { ARM64::ST3Threev8b, "st3", ".8b", 0, 0 },
- { ARM64::ST3Threev4h, "st3", ".4h", 0, 0 },
- { ARM64::ST3Threev2s, "st3", ".2s", 0, 0 },
- { ARM64::ST3Threev16b_POST, "st3", ".16b", 0, 48 },
- { ARM64::ST3Threev8h_POST, "st3", ".8h", 0, 48 },
- { ARM64::ST3Threev4s_POST, "st3", ".4s", 0, 48 },
- { ARM64::ST3Threev2d_POST, "st3", ".2d", 0, 48 },
- { ARM64::ST3Threev8b_POST, "st3", ".8b", 0, 24 },
- { ARM64::ST3Threev4h_POST, "st3", ".4h", 0, 24 },
- { ARM64::ST3Threev2s_POST, "st3", ".2s", 0, 24 },
- { ARM64::ST4i8, "st4", ".b", 1, 0 },
- { ARM64::ST4i16, "st4", ".h", 1, 0 },
- { ARM64::ST4i32, "st4", ".s", 1, 0 },
- { ARM64::ST4i64, "st4", ".d", 1, 0 },
- { ARM64::ST4i8_POST, "st4", ".b", 1, 4 },
- { ARM64::ST4i16_POST, "st4", ".h", 1, 8 },
- { ARM64::ST4i32_POST, "st4", ".s", 1, 16 },
- { ARM64::ST4i64_POST, "st4", ".d", 1, 32 },
- { ARM64::ST4Fourv16b, "st4", ".16b", 0, 0 },
- { ARM64::ST4Fourv8h, "st4", ".8h", 0, 0 },
- { ARM64::ST4Fourv4s, "st4", ".4s", 0, 0 },
- { ARM64::ST4Fourv2d, "st4", ".2d", 0, 0 },
- { ARM64::ST4Fourv8b, "st4", ".8b", 0, 0 },
- { ARM64::ST4Fourv4h, "st4", ".4h", 0, 0 },
- { ARM64::ST4Fourv2s, "st4", ".2s", 0, 0 },
- { ARM64::ST4Fourv16b_POST, "st4", ".16b", 0, 64 },
- { ARM64::ST4Fourv8h_POST, "st4", ".8h", 0, 64 },
- { ARM64::ST4Fourv4s_POST, "st4", ".4s", 0, 64 },
- { ARM64::ST4Fourv2d_POST, "st4", ".2d", 0, 64 },
- { ARM64::ST4Fourv8b_POST, "st4", ".8b", 0, 32 },
- { ARM64::ST4Fourv4h_POST, "st4", ".4h", 0, 32 },
- { ARM64::ST4Fourv2s_POST, "st4", ".2s", 0, 32 },
+ { ARM64::LD1i8, "ld1", ".b", 1, true, 0 },
+ { ARM64::LD1i16, "ld1", ".h", 1, true, 0 },
+ { ARM64::LD1i32, "ld1", ".s", 1, true, 0 },
+ { ARM64::LD1i64, "ld1", ".d", 1, true, 0 },
+ { ARM64::LD1i8_POST, "ld1", ".b", 2, true, 1 },
+ { ARM64::LD1i16_POST, "ld1", ".h", 2, true, 2 },
+ { ARM64::LD1i32_POST, "ld1", ".s", 2, true, 4 },
+ { ARM64::LD1i64_POST, "ld1", ".d", 2, true, 8 },
+ { ARM64::LD1Rv16b, "ld1r", ".16b", 0, false, 0 },
+ { ARM64::LD1Rv8h, "ld1r", ".8h", 0, false, 0 },
+ { ARM64::LD1Rv4s, "ld1r", ".4s", 0, false, 0 },
+ { ARM64::LD1Rv2d, "ld1r", ".2d", 0, false, 0 },
+ { ARM64::LD1Rv8b, "ld1r", ".8b", 0, false, 0 },
+ { ARM64::LD1Rv4h, "ld1r", ".4h", 0, false, 0 },
+ { ARM64::LD1Rv2s, "ld1r", ".2s", 0, false, 0 },
+ { ARM64::LD1Rv1d, "ld1r", ".1d", 0, false, 0 },
+ { ARM64::LD1Rv16b_POST, "ld1r", ".16b", 1, false, 1 },
+ { ARM64::LD1Rv8h_POST, "ld1r", ".8h", 1, false, 2 },
+ { ARM64::LD1Rv4s_POST, "ld1r", ".4s", 1, false, 4 },
+ { ARM64::LD1Rv2d_POST, "ld1r", ".2d", 1, false, 8 },
+ { ARM64::LD1Rv8b_POST, "ld1r", ".8b", 1, false, 1 },
+ { ARM64::LD1Rv4h_POST, "ld1r", ".4h", 1, false, 2 },
+ { ARM64::LD1Rv2s_POST, "ld1r", ".2s", 1, false, 4 },
+ { ARM64::LD1Rv1d_POST, "ld1r", ".1d", 1, false, 8 },
+ { ARM64::LD1Onev16b, "ld1", ".16b", 0, false, 0 },
+ { ARM64::LD1Onev8h, "ld1", ".8h", 0, false, 0 },
+ { ARM64::LD1Onev4s, "ld1", ".4s", 0, false, 0 },
+ { ARM64::LD1Onev2d, "ld1", ".2d", 0, false, 0 },
+ { ARM64::LD1Onev8b, "ld1", ".8b", 0, false, 0 },
+ { ARM64::LD1Onev4h, "ld1", ".4h", 0, false, 0 },
+ { ARM64::LD1Onev2s, "ld1", ".2s", 0, false, 0 },
+ { ARM64::LD1Onev1d, "ld1", ".1d", 0, false, 0 },
+ { ARM64::LD1Onev16b_POST, "ld1", ".16b", 1, false, 16 },
+ { ARM64::LD1Onev8h_POST, "ld1", ".8h", 1, false, 16 },
+ { ARM64::LD1Onev4s_POST, "ld1", ".4s", 1, false, 16 },
+ { ARM64::LD1Onev2d_POST, "ld1", ".2d", 1, false, 16 },
+ { ARM64::LD1Onev8b_POST, "ld1", ".8b", 1, false, 8 },
+ { ARM64::LD1Onev4h_POST, "ld1", ".4h", 1, false, 8 },
+ { ARM64::LD1Onev2s_POST, "ld1", ".2s", 1, false, 8 },
+ { ARM64::LD1Onev1d_POST, "ld1", ".1d", 1, false, 8 },
+ { ARM64::LD1Twov16b, "ld1", ".16b", 0, false, 0 },
+ { ARM64::LD1Twov8h, "ld1", ".8h", 0, false, 0 },
+ { ARM64::LD1Twov4s, "ld1", ".4s", 0, false, 0 },
+ { ARM64::LD1Twov2d, "ld1", ".2d", 0, false, 0 },
+ { ARM64::LD1Twov8b, "ld1", ".8b", 0, false, 0 },
+ { ARM64::LD1Twov4h, "ld1", ".4h", 0, false, 0 },
+ { ARM64::LD1Twov2s, "ld1", ".2s", 0, false, 0 },
+ { ARM64::LD1Twov1d, "ld1", ".1d", 0, false, 0 },
+ { ARM64::LD1Twov16b_POST, "ld1", ".16b", 1, false, 32 },
+ { ARM64::LD1Twov8h_POST, "ld1", ".8h", 1, false, 32 },
+ { ARM64::LD1Twov4s_POST, "ld1", ".4s", 1, false, 32 },
+ { ARM64::LD1Twov2d_POST, "ld1", ".2d", 1, false, 32 },
+ { ARM64::LD1Twov8b_POST, "ld1", ".8b", 1, false, 16 },
+ { ARM64::LD1Twov4h_POST, "ld1", ".4h", 1, false, 16 },
+ { ARM64::LD1Twov2s_POST, "ld1", ".2s", 1, false, 16 },
+ { ARM64::LD1Twov1d_POST, "ld1", ".1d", 1, false, 16 },
+ { ARM64::LD1Threev16b, "ld1", ".16b", 0, false, 0 },
+ { ARM64::LD1Threev8h, "ld1", ".8h", 0, false, 0 },
+ { ARM64::LD1Threev4s, "ld1", ".4s", 0, false, 0 },
+ { ARM64::LD1Threev2d, "ld1", ".2d", 0, false, 0 },
+ { ARM64::LD1Threev8b, "ld1", ".8b", 0, false, 0 },
+ { ARM64::LD1Threev4h, "ld1", ".4h", 0, false, 0 },
+ { ARM64::LD1Threev2s, "ld1", ".2s", 0, false, 0 },
+ { ARM64::LD1Threev1d, "ld1", ".1d", 0, false, 0 },
+ { ARM64::LD1Threev16b_POST, "ld1", ".16b", 1, false, 48 },
+ { ARM64::LD1Threev8h_POST, "ld1", ".8h", 1, false, 48 },
+ { ARM64::LD1Threev4s_POST, "ld1", ".4s", 1, false, 48 },
+ { ARM64::LD1Threev2d_POST, "ld1", ".2d", 1, false, 48 },
+ { ARM64::LD1Threev8b_POST, "ld1", ".8b", 1, false, 24 },
+ { ARM64::LD1Threev4h_POST, "ld1", ".4h", 1, false, 24 },
+ { ARM64::LD1Threev2s_POST, "ld1", ".2s", 1, false, 24 },
+ { ARM64::LD1Threev1d_POST, "ld1", ".1d", 1, false, 24 },
+ { ARM64::LD1Fourv16b, "ld1", ".16b", 0, false, 0 },
+ { ARM64::LD1Fourv8h, "ld1", ".8h", 0, false, 0 },
+ { ARM64::LD1Fourv4s, "ld1", ".4s", 0, false, 0 },
+ { ARM64::LD1Fourv2d, "ld1", ".2d", 0, false, 0 },
+ { ARM64::LD1Fourv8b, "ld1", ".8b", 0, false, 0 },
+ { ARM64::LD1Fourv4h, "ld1", ".4h", 0, false, 0 },
+ { ARM64::LD1Fourv2s, "ld1", ".2s", 0, false, 0 },
+ { ARM64::LD1Fourv1d, "ld1", ".1d", 0, false, 0 },
+ { ARM64::LD1Fourv16b_POST, "ld1", ".16b", 1, false, 64 },
+ { ARM64::LD1Fourv8h_POST, "ld1", ".8h", 1, false, 64 },
+ { ARM64::LD1Fourv4s_POST, "ld1", ".4s", 1, false, 64 },
+ { ARM64::LD1Fourv2d_POST, "ld1", ".2d", 1, false, 64 },
+ { ARM64::LD1Fourv8b_POST, "ld1", ".8b", 1, false, 32 },
+ { ARM64::LD1Fourv4h_POST, "ld1", ".4h", 1, false, 32 },
+ { ARM64::LD1Fourv2s_POST, "ld1", ".2s", 1, false, 32 },
+ { ARM64::LD1Fourv1d_POST, "ld1", ".1d", 1, false, 32 },
+ { ARM64::LD2i8, "ld2", ".b", 1, true, 0 },
+ { ARM64::LD2i16, "ld2", ".h", 1, true, 0 },
+ { ARM64::LD2i32, "ld2", ".s", 1, true, 0 },
+ { ARM64::LD2i64, "ld2", ".d", 1, true, 0 },
+ { ARM64::LD2i8_POST, "ld2", ".b", 2, true, 2 },
+ { ARM64::LD2i16_POST, "ld2", ".h", 2, true, 4 },
+ { ARM64::LD2i32_POST, "ld2", ".s", 2, true, 8 },
+ { ARM64::LD2i64_POST, "ld2", ".d", 2, true, 16 },
+ { ARM64::LD2Rv16b, "ld2r", ".16b", 0, false, 0 },
+ { ARM64::LD2Rv8h, "ld2r", ".8h", 0, false, 0 },
+ { ARM64::LD2Rv4s, "ld2r", ".4s", 0, false, 0 },
+ { ARM64::LD2Rv2d, "ld2r", ".2d", 0, false, 0 },
+ { ARM64::LD2Rv8b, "ld2r", ".8b", 0, false, 0 },
+ { ARM64::LD2Rv4h, "ld2r", ".4h", 0, false, 0 },
+ { ARM64::LD2Rv2s, "ld2r", ".2s", 0, false, 0 },
+ { ARM64::LD2Rv1d, "ld2r", ".1d", 0, false, 0 },
+ { ARM64::LD2Rv16b_POST, "ld2r", ".16b", 1, false, 2 },
+ { ARM64::LD2Rv8h_POST, "ld2r", ".8h", 1, false, 4 },
+ { ARM64::LD2Rv4s_POST, "ld2r", ".4s", 1, false, 8 },
+ { ARM64::LD2Rv2d_POST, "ld2r", ".2d", 1, false, 16 },
+ { ARM64::LD2Rv8b_POST, "ld2r", ".8b", 1, false, 2 },
+ { ARM64::LD2Rv4h_POST, "ld2r", ".4h", 1, false, 4 },
+ { ARM64::LD2Rv2s_POST, "ld2r", ".2s", 1, false, 8 },
+ { ARM64::LD2Rv1d_POST, "ld2r", ".1d", 1, false, 16 },
+ { ARM64::LD2Twov16b, "ld2", ".16b", 0, false, 0 },
+ { ARM64::LD2Twov8h, "ld2", ".8h", 0, false, 0 },
+ { ARM64::LD2Twov4s, "ld2", ".4s", 0, false, 0 },
+ { ARM64::LD2Twov2d, "ld2", ".2d", 0, false, 0 },
+ { ARM64::LD2Twov8b, "ld2", ".8b", 0, false, 0 },
+ { ARM64::LD2Twov4h, "ld2", ".4h", 0, false, 0 },
+ { ARM64::LD2Twov2s, "ld2", ".2s", 0, false, 0 },
+ { ARM64::LD2Twov16b_POST, "ld2", ".16b", 1, false, 32 },
+ { ARM64::LD2Twov8h_POST, "ld2", ".8h", 1, false, 32 },
+ { ARM64::LD2Twov4s_POST, "ld2", ".4s", 1, false, 32 },
+ { ARM64::LD2Twov2d_POST, "ld2", ".2d", 1, false, 32 },
+ { ARM64::LD2Twov8b_POST, "ld2", ".8b", 1, false, 16 },
+ { ARM64::LD2Twov4h_POST, "ld2", ".4h", 1, false, 16 },
+ { ARM64::LD2Twov2s_POST, "ld2", ".2s", 1, false, 16 },
+ { ARM64::LD3i8, "ld3", ".b", 1, true, 0 },
+ { ARM64::LD3i16, "ld3", ".h", 1, true, 0 },
+ { ARM64::LD3i32, "ld3", ".s", 1, true, 0 },
+ { ARM64::LD3i64, "ld3", ".d", 1, true, 0 },
+ { ARM64::LD3i8_POST, "ld3", ".b", 2, true, 3 },
+ { ARM64::LD3i16_POST, "ld3", ".h", 2, true, 6 },
+ { ARM64::LD3i32_POST, "ld3", ".s", 2, true, 12 },
+ { ARM64::LD3i64_POST, "ld3", ".d", 2, true, 24 },
+ { ARM64::LD3Rv16b, "ld3r", ".16b", 0, false, 0 },
+ { ARM64::LD3Rv8h, "ld3r", ".8h", 0, false, 0 },
+ { ARM64::LD3Rv4s, "ld3r", ".4s", 0, false, 0 },
+ { ARM64::LD3Rv2d, "ld3r", ".2d", 0, false, 0 },
+ { ARM64::LD3Rv8b, "ld3r", ".8b", 0, false, 0 },
+ { ARM64::LD3Rv4h, "ld3r", ".4h", 0, false, 0 },
+ { ARM64::LD3Rv2s, "ld3r", ".2s", 0, false, 0 },
+ { ARM64::LD3Rv1d, "ld3r", ".1d", 0, false, 0 },
+ { ARM64::LD3Rv16b_POST, "ld3r", ".16b", 1, false, 3 },
+ { ARM64::LD3Rv8h_POST, "ld3r", ".8h", 1, false, 6 },
+ { ARM64::LD3Rv4s_POST, "ld3r", ".4s", 1, false, 12 },
+ { ARM64::LD3Rv2d_POST, "ld3r", ".2d", 1, false, 24 },
+ { ARM64::LD3Rv8b_POST, "ld3r", ".8b", 1, false, 3 },
+ { ARM64::LD3Rv4h_POST, "ld3r", ".4h", 1, false, 6 },
+ { ARM64::LD3Rv2s_POST, "ld3r", ".2s", 1, false, 12 },
+ { ARM64::LD3Rv1d_POST, "ld3r", ".1d", 1, false, 24 },
+ { ARM64::LD3Threev16b, "ld3", ".16b", 0, false, 0 },
+ { ARM64::LD3Threev8h, "ld3", ".8h", 0, false, 0 },
+ { ARM64::LD3Threev4s, "ld3", ".4s", 0, false, 0 },
+ { ARM64::LD3Threev2d, "ld3", ".2d", 0, false, 0 },
+ { ARM64::LD3Threev8b, "ld3", ".8b", 0, false, 0 },
+ { ARM64::LD3Threev4h, "ld3", ".4h", 0, false, 0 },
+ { ARM64::LD3Threev2s, "ld3", ".2s", 0, false, 0 },
+ { ARM64::LD3Threev16b_POST, "ld3", ".16b", 1, false, 48 },
+ { ARM64::LD3Threev8h_POST, "ld3", ".8h", 1, false, 48 },
+ { ARM64::LD3Threev4s_POST, "ld3", ".4s", 1, false, 48 },
+ { ARM64::LD3Threev2d_POST, "ld3", ".2d", 1, false, 48 },
+ { ARM64::LD3Threev8b_POST, "ld3", ".8b", 1, false, 24 },
+ { ARM64::LD3Threev4h_POST, "ld3", ".4h", 1, false, 24 },
+ { ARM64::LD3Threev2s_POST, "ld3", ".2s", 1, false, 24 },
+ { ARM64::LD4i8, "ld4", ".b", 1, true, 0 },
+ { ARM64::LD4i16, "ld4", ".h", 1, true, 0 },
+ { ARM64::LD4i32, "ld4", ".s", 1, true, 0 },
+ { ARM64::LD4i64, "ld4", ".d", 1, true, 0 },
+ { ARM64::LD4i8_POST, "ld4", ".b", 2, true, 4 },
+ { ARM64::LD4i16_POST, "ld4", ".h", 2, true, 8 },
+ { ARM64::LD4i32_POST, "ld4", ".s", 2, true, 16 },
+ { ARM64::LD4i64_POST, "ld4", ".d", 2, true, 32 },
+ { ARM64::LD4Rv16b, "ld4r", ".16b", 0, false, 0 },
+ { ARM64::LD4Rv8h, "ld4r", ".8h", 0, false, 0 },
+ { ARM64::LD4Rv4s, "ld4r", ".4s", 0, false, 0 },
+ { ARM64::LD4Rv2d, "ld4r", ".2d", 0, false, 0 },
+ { ARM64::LD4Rv8b, "ld4r", ".8b", 0, false, 0 },
+ { ARM64::LD4Rv4h, "ld4r", ".4h", 0, false, 0 },
+ { ARM64::LD4Rv2s, "ld4r", ".2s", 0, false, 0 },
+ { ARM64::LD4Rv1d, "ld4r", ".1d", 0, false, 0 },
+ { ARM64::LD4Rv16b_POST, "ld4r", ".16b", 1, false, 4 },
+ { ARM64::LD4Rv8h_POST, "ld4r", ".8h", 1, false, 8 },
+ { ARM64::LD4Rv4s_POST, "ld4r", ".4s", 1, false, 16 },
+ { ARM64::LD4Rv2d_POST, "ld4r", ".2d", 1, false, 32 },
+ { ARM64::LD4Rv8b_POST, "ld4r", ".8b", 1, false, 4 },
+ { ARM64::LD4Rv4h_POST, "ld4r", ".4h", 1, false, 8 },
+ { ARM64::LD4Rv2s_POST, "ld4r", ".2s", 1, false, 16 },
+ { ARM64::LD4Rv1d_POST, "ld4r", ".1d", 1, false, 32 },
+ { ARM64::LD4Fourv16b, "ld4", ".16b", 0, false, 0 },
+ { ARM64::LD4Fourv8h, "ld4", ".8h", 0, false, 0 },
+ { ARM64::LD4Fourv4s, "ld4", ".4s", 0, false, 0 },
+ { ARM64::LD4Fourv2d, "ld4", ".2d", 0, false, 0 },
+ { ARM64::LD4Fourv8b, "ld4", ".8b", 0, false, 0 },
+ { ARM64::LD4Fourv4h, "ld4", ".4h", 0, false, 0 },
+ { ARM64::LD4Fourv2s, "ld4", ".2s", 0, false, 0 },
+ { ARM64::LD4Fourv16b_POST, "ld4", ".16b", 1, false, 64 },
+ { ARM64::LD4Fourv8h_POST, "ld4", ".8h", 1, false, 64 },
+ { ARM64::LD4Fourv4s_POST, "ld4", ".4s", 1, false, 64 },
+ { ARM64::LD4Fourv2d_POST, "ld4", ".2d", 1, false, 64 },
+ { ARM64::LD4Fourv8b_POST, "ld4", ".8b", 1, false, 32 },
+ { ARM64::LD4Fourv4h_POST, "ld4", ".4h", 1, false, 32 },
+ { ARM64::LD4Fourv2s_POST, "ld4", ".2s", 1, false, 32 },
+ { ARM64::ST1i8, "st1", ".b", 0, true, 0 },
+ { ARM64::ST1i16, "st1", ".h", 0, true, 0 },
+ { ARM64::ST1i32, "st1", ".s", 0, true, 0 },
+ { ARM64::ST1i64, "st1", ".d", 0, true, 0 },
+ { ARM64::ST1i8_POST, "st1", ".b", 1, true, 1 },
+ { ARM64::ST1i16_POST, "st1", ".h", 1, true, 2 },
+ { ARM64::ST1i32_POST, "st1", ".s", 1, true, 4 },
+ { ARM64::ST1i64_POST, "st1", ".d", 1, true, 8 },
+ { ARM64::ST1Onev16b, "st1", ".16b", 0, false, 0 },
+ { ARM64::ST1Onev8h, "st1", ".8h", 0, false, 0 },
+ { ARM64::ST1Onev4s, "st1", ".4s", 0, false, 0 },
+ { ARM64::ST1Onev2d, "st1", ".2d", 0, false, 0 },
+ { ARM64::ST1Onev8b, "st1", ".8b", 0, false, 0 },
+ { ARM64::ST1Onev4h, "st1", ".4h", 0, false, 0 },
+ { ARM64::ST1Onev2s, "st1", ".2s", 0, false, 0 },
+ { ARM64::ST1Onev1d, "st1", ".1d", 0, false, 0 },
+ { ARM64::ST1Onev16b_POST, "st1", ".16b", 1, false, 16 },
+ { ARM64::ST1Onev8h_POST, "st1", ".8h", 1, false, 16 },
+ { ARM64::ST1Onev4s_POST, "st1", ".4s", 1, false, 16 },
+ { ARM64::ST1Onev2d_POST, "st1", ".2d", 1, false, 16 },
+ { ARM64::ST1Onev8b_POST, "st1", ".8b", 1, false, 8 },
+ { ARM64::ST1Onev4h_POST, "st1", ".4h", 1, false, 8 },
+ { ARM64::ST1Onev2s_POST, "st1", ".2s", 1, false, 8 },
+ { ARM64::ST1Onev1d_POST, "st1", ".1d", 1, false, 8 },
+ { ARM64::ST1Twov16b, "st1", ".16b", 0, false, 0 },
+ { ARM64::ST1Twov8h, "st1", ".8h", 0, false, 0 },
+ { ARM64::ST1Twov4s, "st1", ".4s", 0, false, 0 },
+ { ARM64::ST1Twov2d, "st1", ".2d", 0, false, 0 },
+ { ARM64::ST1Twov8b, "st1", ".8b", 0, false, 0 },
+ { ARM64::ST1Twov4h, "st1", ".4h", 0, false, 0 },
+ { ARM64::ST1Twov2s, "st1", ".2s", 0, false, 0 },
+ { ARM64::ST1Twov1d, "st1", ".1d", 0, false, 0 },
+ { ARM64::ST1Twov16b_POST, "st1", ".16b", 1, false, 32 },
+ { ARM64::ST1Twov8h_POST, "st1", ".8h", 1, false, 32 },
+ { ARM64::ST1Twov4s_POST, "st1", ".4s", 1, false, 32 },
+ { ARM64::ST1Twov2d_POST, "st1", ".2d", 1, false, 32 },
+ { ARM64::ST1Twov8b_POST, "st1", ".8b", 1, false, 16 },
+ { ARM64::ST1Twov4h_POST, "st1", ".4h", 1, false, 16 },
+ { ARM64::ST1Twov2s_POST, "st1", ".2s", 1, false, 16 },
+ { ARM64::ST1Twov1d_POST, "st1", ".1d", 1, false, 16 },
+ { ARM64::ST1Threev16b, "st1", ".16b", 0, false, 0 },
+ { ARM64::ST1Threev8h, "st1", ".8h", 0, false, 0 },
+ { ARM64::ST1Threev4s, "st1", ".4s", 0, false, 0 },
+ { ARM64::ST1Threev2d, "st1", ".2d", 0, false, 0 },
+ { ARM64::ST1Threev8b, "st1", ".8b", 0, false, 0 },
+ { ARM64::ST1Threev4h, "st1", ".4h", 0, false, 0 },
+ { ARM64::ST1Threev2s, "st1", ".2s", 0, false, 0 },
+ { ARM64::ST1Threev1d, "st1", ".1d", 0, false, 0 },
+ { ARM64::ST1Threev16b_POST, "st1", ".16b", 1, false, 48 },
+ { ARM64::ST1Threev8h_POST, "st1", ".8h", 1, false, 48 },
+ { ARM64::ST1Threev4s_POST, "st1", ".4s", 1, false, 48 },
+ { ARM64::ST1Threev2d_POST, "st1", ".2d", 1, false, 48 },
+ { ARM64::ST1Threev8b_POST, "st1", ".8b", 1, false, 24 },
+ { ARM64::ST1Threev4h_POST, "st1", ".4h", 1, false, 24 },
+ { ARM64::ST1Threev2s_POST, "st1", ".2s", 1, false, 24 },
+ { ARM64::ST1Threev1d_POST, "st1", ".1d", 1, false, 24 },
+ { ARM64::ST1Fourv16b, "st1", ".16b", 0, false, 0 },
+ { ARM64::ST1Fourv8h, "st1", ".8h", 0, false, 0 },
+ { ARM64::ST1Fourv4s, "st1", ".4s", 0, false, 0 },
+ { ARM64::ST1Fourv2d, "st1", ".2d", 0, false, 0 },
+ { ARM64::ST1Fourv8b, "st1", ".8b", 0, false, 0 },
+ { ARM64::ST1Fourv4h, "st1", ".4h", 0, false, 0 },
+ { ARM64::ST1Fourv2s, "st1", ".2s", 0, false, 0 },
+ { ARM64::ST1Fourv1d, "st1", ".1d", 0, false, 0 },
+ { ARM64::ST1Fourv16b_POST, "st1", ".16b", 1, false, 64 },
+ { ARM64::ST1Fourv8h_POST, "st1", ".8h", 1, false, 64 },
+ { ARM64::ST1Fourv4s_POST, "st1", ".4s", 1, false, 64 },
+ { ARM64::ST1Fourv2d_POST, "st1", ".2d", 1, false, 64 },
+ { ARM64::ST1Fourv8b_POST, "st1", ".8b", 1, false, 32 },
+ { ARM64::ST1Fourv4h_POST, "st1", ".4h", 1, false, 32 },
+ { ARM64::ST1Fourv2s_POST, "st1", ".2s", 1, false, 32 },
+ { ARM64::ST1Fourv1d_POST, "st1", ".1d", 1, false, 32 },
+ { ARM64::ST2i8, "st2", ".b", 0, true, 0 },
+ { ARM64::ST2i16, "st2", ".h", 0, true, 0 },
+ { ARM64::ST2i32, "st2", ".s", 0, true, 0 },
+ { ARM64::ST2i64, "st2", ".d", 0, true, 0 },
+ { ARM64::ST2i8_POST, "st2", ".b", 1, true, 2 },
+ { ARM64::ST2i16_POST, "st2", ".h", 1, true, 4 },
+ { ARM64::ST2i32_POST, "st2", ".s", 1, true, 8 },
+ { ARM64::ST2i64_POST, "st2", ".d", 1, true, 16 },
+ { ARM64::ST2Twov16b, "st2", ".16b", 0, false, 0 },
+ { ARM64::ST2Twov8h, "st2", ".8h", 0, false, 0 },
+ { ARM64::ST2Twov4s, "st2", ".4s", 0, false, 0 },
+ { ARM64::ST2Twov2d, "st2", ".2d", 0, false, 0 },
+ { ARM64::ST2Twov8b, "st2", ".8b", 0, false, 0 },
+ { ARM64::ST2Twov4h, "st2", ".4h", 0, false, 0 },
+ { ARM64::ST2Twov2s, "st2", ".2s", 0, false, 0 },
+ { ARM64::ST2Twov16b_POST, "st2", ".16b", 1, false, 32 },
+ { ARM64::ST2Twov8h_POST, "st2", ".8h", 1, false, 32 },
+ { ARM64::ST2Twov4s_POST, "st2", ".4s", 1, false, 32 },
+ { ARM64::ST2Twov2d_POST, "st2", ".2d", 1, false, 32 },
+ { ARM64::ST2Twov8b_POST, "st2", ".8b", 1, false, 16 },
+ { ARM64::ST2Twov4h_POST, "st2", ".4h", 1, false, 16 },
+ { ARM64::ST2Twov2s_POST, "st2", ".2s", 1, false, 16 },
+ { ARM64::ST3i8, "st3", ".b", 0, true, 0 },
+ { ARM64::ST3i16, "st3", ".h", 0, true, 0 },
+ { ARM64::ST3i32, "st3", ".s", 0, true, 0 },
+ { ARM64::ST3i64, "st3", ".d", 0, true, 0 },
+ { ARM64::ST3i8_POST, "st3", ".b", 1, true, 3 },
+ { ARM64::ST3i16_POST, "st3", ".h", 1, true, 6 },
+ { ARM64::ST3i32_POST, "st3", ".s", 1, true, 12 },
+ { ARM64::ST3i64_POST, "st3", ".d", 1, true, 24 },
+ { ARM64::ST3Threev16b, "st3", ".16b", 0, false, 0 },
+ { ARM64::ST3Threev8h, "st3", ".8h", 0, false, 0 },
+ { ARM64::ST3Threev4s, "st3", ".4s", 0, false, 0 },
+ { ARM64::ST3Threev2d, "st3", ".2d", 0, false, 0 },
+ { ARM64::ST3Threev8b, "st3", ".8b", 0, false, 0 },
+ { ARM64::ST3Threev4h, "st3", ".4h", 0, false, 0 },
+ { ARM64::ST3Threev2s, "st3", ".2s", 0, false, 0 },
+ { ARM64::ST3Threev16b_POST, "st3", ".16b", 1, false, 48 },
+ { ARM64::ST3Threev8h_POST, "st3", ".8h", 1, false, 48 },
+ { ARM64::ST3Threev4s_POST, "st3", ".4s", 1, false, 48 },
+ { ARM64::ST3Threev2d_POST, "st3", ".2d", 1, false, 48 },
+ { ARM64::ST3Threev8b_POST, "st3", ".8b", 1, false, 24 },
+ { ARM64::ST3Threev4h_POST, "st3", ".4h", 1, false, 24 },
+ { ARM64::ST3Threev2s_POST, "st3", ".2s", 1, false, 24 },
+ { ARM64::ST4i8, "st4", ".b", 0, true, 0 },
+ { ARM64::ST4i16, "st4", ".h", 0, true, 0 },
+ { ARM64::ST4i32, "st4", ".s", 0, true, 0 },
+ { ARM64::ST4i64, "st4", ".d", 0, true, 0 },
+ { ARM64::ST4i8_POST, "st4", ".b", 1, true, 4 },
+ { ARM64::ST4i16_POST, "st4", ".h", 1, true, 8 },
+ { ARM64::ST4i32_POST, "st4", ".s", 1, true, 16 },
+ { ARM64::ST4i64_POST, "st4", ".d", 1, true, 32 },
+ { ARM64::ST4Fourv16b, "st4", ".16b", 0, false, 0 },
+ { ARM64::ST4Fourv8h, "st4", ".8h", 0, false, 0 },
+ { ARM64::ST4Fourv4s, "st4", ".4s", 0, false, 0 },
+ { ARM64::ST4Fourv2d, "st4", ".2d", 0, false, 0 },
+ { ARM64::ST4Fourv8b, "st4", ".8b", 0, false, 0 },
+ { ARM64::ST4Fourv4h, "st4", ".4h", 0, false, 0 },
+ { ARM64::ST4Fourv2s, "st4", ".2s", 0, false, 0 },
+ { ARM64::ST4Fourv16b_POST, "st4", ".16b", 1, false, 64 },
+ { ARM64::ST4Fourv8h_POST, "st4", ".8h", 1, false, 64 },
+ { ARM64::ST4Fourv4s_POST, "st4", ".4s", 1, false, 64 },
+ { ARM64::ST4Fourv2d_POST, "st4", ".2d", 1, false, 64 },
+ { ARM64::ST4Fourv8b_POST, "st4", ".8b", 1, false, 32 },
+ { ARM64::ST4Fourv4h_POST, "st4", ".4h", 1, false, 32 },
+ { ARM64::ST4Fourv2s_POST, "st4", ".2s", 1, false, 32 },
};
static LdStNInstrDesc *getLdStNInstrDesc(unsigned Opcode) {
if (LdStNInstInfo[Idx].Opcode == Opcode)
return &LdStNInstInfo[Idx];
- return 0;
+ return nullptr;
}
void ARM64AppleInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
// Now onto the operands: first a vector list with possible lane
// specifier. E.g. { v0 }[2]
- printVectorList(MI, 0, O, "");
+ int OpNum = LdStDesc->ListOperand;
+ printVectorList(MI, OpNum++, O, "");
- if (LdStDesc->LaneOperand != 0)
- O << '[' << MI->getOperand(LdStDesc->LaneOperand).getImm() << ']';
+ if (LdStDesc->HasLane)
+ O << '[' << MI->getOperand(OpNum++).getImm() << ']';
// Next the address: [xN]
- unsigned AddrOpNum = LdStDesc->LaneOperand + 1;
- unsigned AddrReg = MI->getOperand(AddrOpNum).getReg();
+ unsigned AddrReg = MI->getOperand(OpNum++).getReg();
O << ", [" << getRegisterName(AddrReg) << ']';
// Finally, there might be a post-indexed offset.
if (LdStDesc->NaturalOffset != 0) {
- unsigned Reg = MI->getOperand(AddrOpNum + 1).getReg();
+ unsigned Reg = MI->getOperand(OpNum++).getReg();
if (Reg != ARM64::XZR)
O << ", " << getRegisterName(Reg);
else {
assert(Opcode == ARM64::SYSxt && "Invalid opcode for SYS alias!");
#endif
- const char *Asm = 0;
+ const char *Asm = nullptr;
const MCOperand &Op1 = MI->getOperand(0);
const MCOperand &Cn = MI->getOperand(1);
const MCOperand &Cm = MI->getOperand(2);
O << ", " << getRegisterName(Reg);
}
- return Asm != 0;
+ return Asm != nullptr;
}
void ARM64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
}
}
+void ARM64InstPrinter::printHexImm(const MCInst *MI, unsigned OpNo,
+ raw_ostream &O) {
+ const MCOperand &Op = MI->getOperand(OpNo);
+ O << format("#%#llx", Op.getImm());
+}
+
void ARM64InstPrinter::printPostIncOperand(const MCInst *MI, unsigned OpNo,
unsigned Imm, raw_ostream &O) {
const MCOperand &Op = MI->getOperand(OpNo);
assert(0 && "unknown operand kind in printPostIncOperand64");
}
-void ARM64InstPrinter::printPostIncOperand1(const MCInst *MI, unsigned OpNo,
- raw_ostream &O) {
- printPostIncOperand(MI, OpNo, 1, O);
-}
-
-void ARM64InstPrinter::printPostIncOperand2(const MCInst *MI, unsigned OpNo,
- raw_ostream &O) {
- printPostIncOperand(MI, OpNo, 2, O);
-}
-
-void ARM64InstPrinter::printPostIncOperand3(const MCInst *MI, unsigned OpNo,
- raw_ostream &O) {
- printPostIncOperand(MI, OpNo, 3, O);
-}
-
-void ARM64InstPrinter::printPostIncOperand4(const MCInst *MI, unsigned OpNo,
- raw_ostream &O) {
- printPostIncOperand(MI, OpNo, 4, O);
-}
-
-void ARM64InstPrinter::printPostIncOperand6(const MCInst *MI, unsigned OpNo,
- raw_ostream &O) {
- printPostIncOperand(MI, OpNo, 6, O);
-}
-
-void ARM64InstPrinter::printPostIncOperand8(const MCInst *MI, unsigned OpNo,
- raw_ostream &O) {
- printPostIncOperand(MI, OpNo, 8, O);
-}
-
-void ARM64InstPrinter::printPostIncOperand12(const MCInst *MI, unsigned OpNo,
- raw_ostream &O) {
- printPostIncOperand(MI, OpNo, 12, O);
-}
-
-void ARM64InstPrinter::printPostIncOperand16(const MCInst *MI, unsigned OpNo,
- raw_ostream &O) {
- printPostIncOperand(MI, OpNo, 16, O);
-}
-
-void ARM64InstPrinter::printPostIncOperand24(const MCInst *MI, unsigned OpNo,
- raw_ostream &O) {
- printPostIncOperand(MI, OpNo, 24, O);
-}
-
-void ARM64InstPrinter::printPostIncOperand32(const MCInst *MI, unsigned OpNo,
- raw_ostream &O) {
- printPostIncOperand(MI, OpNo, 32, O);
-}
-
-void ARM64InstPrinter::printPostIncOperand48(const MCInst *MI, unsigned OpNo,
- raw_ostream &O) {
- printPostIncOperand(MI, OpNo, 48, O);
-}
-
-void ARM64InstPrinter::printPostIncOperand64(const MCInst *MI, unsigned OpNo,
- raw_ostream &O) {
- printPostIncOperand(MI, OpNo, 64, O);
-}
-
void ARM64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
const MCOperand &Op = MI->getOperand(OpNo);
assert(Val == MO.getImm() && "Add/sub immediate out of range!");
unsigned Shift =
ARM64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm());
- O << '#' << (Val << Shift);
- // Distinguish "0, lsl #12" from "0, lsl #0".
- if (Val == 0 && Shift != 0)
+ O << '#' << Val;
+ if (Shift != 0)
printShifter(MI, OpNum + 1, O);
+
+ if (CommentStream)
+ *CommentStream << '=' << (Val << Shift) << '\n';
} else {
assert(MO.isExpr() && "Unexpected operand type!");
O << *MO.getExpr();
if (ARM64_AM::getShiftType(Val) == ARM64_AM::LSL &&
ARM64_AM::getShiftValue(Val) == 0)
return;
- O << ", " << ARM64_AM::getShiftName(ARM64_AM::getShiftType(Val)) << " #"
+ O << ", " << ARM64_AM::getShiftExtendName(ARM64_AM::getShiftType(Val)) << " #"
<< ARM64_AM::getShiftValue(Val);
}
void ARM64InstPrinter::printExtendedRegister(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
O << getRegisterName(MI->getOperand(OpNum).getReg());
- printExtend(MI, OpNum + 1, O);
+ printArithExtend(MI, OpNum + 1, O);
}
-void ARM64InstPrinter::printExtend(const MCInst *MI, unsigned OpNum,
- raw_ostream &O) {
+void ARM64InstPrinter::printArithExtend(const MCInst *MI, unsigned OpNum,
+ raw_ostream &O) {
unsigned Val = MI->getOperand(OpNum).getImm();
- ARM64_AM::ExtendType ExtType = ARM64_AM::getArithExtendType(Val);
+ ARM64_AM::ShiftExtendType ExtType = ARM64_AM::getArithExtendType(Val);
unsigned ShiftVal = ARM64_AM::getArithShiftValue(Val);
// If the destination or first source register operand is [W]SP, print
return;
}
}
- O << ", " << ARM64_AM::getExtendName(ExtType);
+ O << ", " << ARM64_AM::getShiftExtendName(ExtType);
if (ShiftVal != 0)
O << " #" << ShiftVal;
}
-void ARM64InstPrinter::printDotCondCode(const MCInst *MI, unsigned OpNum,
- raw_ostream &O) {
- ARM64CC::CondCode CC = (ARM64CC::CondCode)MI->getOperand(OpNum).getImm();
- O << '.' << ARM64CC::getCondCodeName(CC);
+void ARM64InstPrinter::printMemExtend(const MCInst *MI, unsigned OpNum,
+ raw_ostream &O, char SrcRegKind,
+ unsigned Width) {
+ unsigned SignExtend = MI->getOperand(OpNum).getImm();
+ unsigned DoShift = MI->getOperand(OpNum + 1).getImm();
+
+ // sxtw, sxtx, uxtw or lsl (== uxtx)
+ bool IsLSL = !SignExtend && SrcRegKind == 'x';
+ if (IsLSL)
+ O << "lsl";
+ else
+ O << (SignExtend ? 's' : 'u') << "xt" << SrcRegKind;
+
+ if (DoShift || IsLSL)
+ O << " #" << Log2_32(Width / 8);
}
void ARM64InstPrinter::printCondCode(const MCInst *MI, unsigned OpNum,
O << ARM64CC::getCondCodeName(CC);
}
-void ARM64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum,
- raw_ostream &O) {
- O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']';
-}
-
-void ARM64InstPrinter::printImmScale4(const MCInst *MI, unsigned OpNum,
- raw_ostream &O) {
- O << '#' << 4 * MI->getOperand(OpNum).getImm();
+void ARM64InstPrinter::printInverseCondCode(const MCInst *MI, unsigned OpNum,
+ raw_ostream &O) {
+ ARM64CC::CondCode CC = (ARM64CC::CondCode)MI->getOperand(OpNum).getImm();
+ O << ARM64CC::getCondCodeName(ARM64CC::getInvertedCondCode(CC));
}
-void ARM64InstPrinter::printImmScale8(const MCInst *MI, unsigned OpNum,
+void ARM64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
- O << '#' << 8 * MI->getOperand(OpNum).getImm();
+ O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']';
}
-void ARM64InstPrinter::printImmScale16(const MCInst *MI, unsigned OpNum,
- raw_ostream &O) {
- O << '#' << 16 * MI->getOperand(OpNum).getImm();
+template<int Scale>
+void ARM64InstPrinter::printImmScale(const MCInst *MI, unsigned OpNum,
+ raw_ostream &O) {
+ O << '#' << Scale * MI->getOperand(OpNum).getImm();
}
-void ARM64InstPrinter::printAMIndexed(const MCInst *MI, unsigned OpNum,
- unsigned Scale, raw_ostream &O) {
- const MCOperand MO1 = MI->getOperand(OpNum + 1);
- O << '[' << getRegisterName(MI->getOperand(OpNum).getReg());
- if (MO1.isImm()) {
- if (MO1.getImm() != 0)
- O << ", #" << (MO1.getImm() * Scale);
+void ARM64InstPrinter::printUImm12Offset(const MCInst *MI, unsigned OpNum,
+ unsigned Scale, raw_ostream &O) {
+ const MCOperand MO = MI->getOperand(OpNum);
+ if (MO.isImm()) {
+ O << "#" << (MO.getImm() * Scale);
} else {
- assert(MO1.isExpr() && "Unexpected operand type!");
- O << ", " << *MO1.getExpr();
+ assert(MO.isExpr() && "Unexpected operand type!");
+ O << *MO.getExpr();
}
- O << ']';
}
void ARM64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum,
O << '#' << prfop;
}
-void ARM64InstPrinter::printMemoryPostIndexed32(const MCInst *MI,
- unsigned OpNum,
- raw_ostream &O) {
- O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']' << ", #"
- << 4 * MI->getOperand(OpNum + 1).getImm();
-}
-
-void ARM64InstPrinter::printMemoryPostIndexed64(const MCInst *MI,
- unsigned OpNum,
- raw_ostream &O) {
- O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']' << ", #"
- << 8 * MI->getOperand(OpNum + 1).getImm();
-}
-
-void ARM64InstPrinter::printMemoryPostIndexed128(const MCInst *MI,
- unsigned OpNum,
- raw_ostream &O) {
- O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']' << ", #"
- << 16 * MI->getOperand(OpNum + 1).getImm();
-}
-
-void ARM64InstPrinter::printMemoryPostIndexed(const MCInst *MI, unsigned OpNum,
- raw_ostream &O) {
- O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']' << ", #"
- << MI->getOperand(OpNum + 1).getImm();
-}
-
-void ARM64InstPrinter::printMemoryRegOffset(const MCInst *MI, unsigned OpNum,
- raw_ostream &O, int LegalShiftAmt) {
- unsigned Val = MI->getOperand(OpNum + 2).getImm();
- ARM64_AM::ExtendType ExtType = ARM64_AM::getMemExtendType(Val);
-
- O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ", ";
- if (ExtType == ARM64_AM::UXTW || ExtType == ARM64_AM::SXTW)
- O << getRegisterName(getWRegFromXReg(MI->getOperand(OpNum + 1).getReg()));
- else
- O << getRegisterName(MI->getOperand(OpNum + 1).getReg());
-
- bool DoShift = ARM64_AM::getMemDoShift(Val);
-
- if (ExtType == ARM64_AM::UXTX) {
- if (DoShift)
- O << ", lsl";
- } else
- O << ", " << ARM64_AM::getExtendName(ExtType);
-
- if (DoShift)
- O << " #" << LegalShiftAmt;
-
- O << "]";
-}
-
-void ARM64InstPrinter::printMemoryRegOffset8(const MCInst *MI, unsigned OpNum,
- raw_ostream &O) {
- printMemoryRegOffset(MI, OpNum, O, 0);
-}
-
-void ARM64InstPrinter::printMemoryRegOffset16(const MCInst *MI, unsigned OpNum,
- raw_ostream &O) {
- printMemoryRegOffset(MI, OpNum, O, 1);
-}
-
-void ARM64InstPrinter::printMemoryRegOffset32(const MCInst *MI, unsigned OpNum,
- raw_ostream &O) {
- printMemoryRegOffset(MI, OpNum, O, 2);
-}
-
-void ARM64InstPrinter::printMemoryRegOffset64(const MCInst *MI, unsigned OpNum,
- raw_ostream &O) {
- printMemoryRegOffset(MI, OpNum, O, 3);
-}
-
-void ARM64InstPrinter::printMemoryRegOffset128(const MCInst *MI, unsigned OpNum,
- raw_ostream &O) {
- printMemoryRegOffset(MI, OpNum, O, 4);
-}
-
void ARM64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
const MCOperand &MO = MI->getOperand(OpNum);
- O << '#';
- if (MO.isFPImm())
- // FIXME: Should this ever happen?
- O << MO.getFPImm();
- else
- O << ARM64_AM::getFPImmFloat(MO.getImm());
+ float FPImm = MO.isFPImm() ? MO.getFPImm() : ARM64_AM::getFPImmFloat(MO.getImm());
+
+ // 8 decimal places are enough to perfectly represent permitted floats.
+ O << format("#%.8f", FPImm);
}
static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) {
unsigned Val = MI->getOperand(OpNo).getImm();
bool Valid;
- auto Mapper = ARM64SysReg::MRSMapper();
+ auto Mapper = ARM64SysReg::MRSMapper(getAvailableFeatures());
std::string Name = Mapper.toString(Val, Valid);
if (Valid)
unsigned Val = MI->getOperand(OpNo).getImm();
bool Valid;
- auto Mapper = ARM64SysReg::MSRMapper();
+ auto Mapper = ARM64SysReg::MSRMapper(getAvailableFeatures());
std::string Name = Mapper.toString(Val, Valid);
if (Valid)
O << StringRef(Name).upper();
}
-void ARM64InstPrinter::printSystemCPSRField(const MCInst *MI, unsigned OpNo,
- raw_ostream &O) {
+void ARM64InstPrinter::printSystemPStateField(const MCInst *MI, unsigned OpNo,
+ raw_ostream &O) {
unsigned Val = MI->getOperand(OpNo).getImm();
bool Valid;
projects / oota-llvm.git / blobdiff