AArch64/ARM64: Port NEON post-increment load/store with 2/3/4 vectors to ARM64 backend.

[oota-llvm.git] / lib / Target / ARM64 / ARM64ISelLowering.h

diff --git a/lib/Target/ARM64/ARM64ISelLowering.h b/lib/Target/ARM64/ARM64ISelLowering.h
index 96a32ea85c00e393913484839fbf3aa8f198c1a4..8b321ee9d03d17351b93d35cae2d08feb32dd338 100644 (file)
--- a/lib/Target/ARM64/ARM64ISelLowering.h
+++ b/lib/Target/ARM64/ARM64ISelLowering.h
@@ -160,7 +160,30 @@ enum {
 
   // {s|u}int to FP within a FP register.
   SITOF,
-  UITOF
+  UITOF,
+
+  // NEON Load/Store with post-increment base updates
+  LD2post = ISD::FIRST_TARGET_MEMORY_OPCODE,
+  LD3post,
+  LD4post,
+  ST2post,
+  ST3post,
+  ST4post,
+  LD1x2post,
+  LD1x3post,
+  LD1x4post,
+  ST1x2post,
+  ST1x3post,
+  ST1x4post,
+  LD2DUPpost,
+  LD3DUPpost,
+  LD4DUPpost,
+  LD2LANEpost,
+  LD3LANEpost,
+  LD4LANEpost,
+  ST2LANEpost,
+  ST3LANEpost,
+  ST4LANEpost
 };
 
 } // end namespace ARM64ISD
@@ -388,6 +411,7 @@ private:
 
   ConstraintType
   getConstraintType(const std::string &Constraint) const override;
+  unsigned getRegisterByName(const char* RegName) const;
 
   /// Examine constraint string and operand type and determine a weight value.
   /// The operand object must already have been set up with the operand type.