Update Cortex-A8 instruction itineraries for integer instructions.

[oota-llvm.git] / lib / Target / ARM / ARMScheduleV6.td

diff --git a/lib/Target/ARM/ARMScheduleV6.td b/lib/Target/ARM/ARMScheduleV6.td
index e594f5278687861c81b0cf0e22de19323b4ce9d3..1cac9180df1a6d21ae6445c46f8c17f5546a1034 100644 (file)
--- a/lib/Target/ARM/ARMScheduleV6.td
+++ b/lib/Target/ARM/ARMScheduleV6.td
@@ -14,13 +14,53 @@
 // TODO: this should model an ARM11
 // Single issue pipeline so every itinerary starts with FU_pipe0
 def V6Itineraries : ProcessorItineraries<[
-  InstrItinData<IIC_iALU    , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iMPYh   , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iMPYw   , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iMPYl   , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iLoad   , [InstrStage<1, [FU_Pipe0]>,
+  InstrItinData<IIC_iALUx   , [InstrStage<1, [FU_Pipe0]>]>,
+  InstrItinData<IIC_iALUi   , [InstrStage<1, [FU_Pipe0]>]>,
+  InstrItinData<IIC_iALUr   , [InstrStage<1, [FU_Pipe0]>]>,
+  InstrItinData<IIC_iALUsi  , [InstrStage<1, [FU_Pipe0]>]>,
+  InstrItinData<IIC_iALUsr  , [InstrStage<1, [FU_Pipe0]>]>,
+  InstrItinData<IIC_iUNAr   , [InstrStage<1, [FU_Pipe0]>]>,
+  InstrItinData<IIC_iUNAsi  , [InstrStage<1, [FU_Pipe0]>]>,
+  InstrItinData<IIC_iUNAsr  , [InstrStage<1, [FU_Pipe0]>]>,
+  InstrItinData<IIC_iCMPi   , [InstrStage<1, [FU_Pipe0]>]>,
+  InstrItinData<IIC_iCMPr   , [InstrStage<1, [FU_Pipe0]>]>,
+  InstrItinData<IIC_iCMPsi  , [InstrStage<1, [FU_Pipe0]>]>,
+  InstrItinData<IIC_iCMPsr  , [InstrStage<1, [FU_Pipe0]>]>,
+  InstrItinData<IIC_iMOVi   , [InstrStage<1, [FU_Pipe0]>]>,
+  InstrItinData<IIC_iMOVr   , [InstrStage<1, [FU_Pipe0]>]>,
+  InstrItinData<IIC_iMOVsi  , [InstrStage<1, [FU_Pipe0]>]>,
+  InstrItinData<IIC_iMOVsr  , [InstrStage<1, [FU_Pipe0]>]>,
+  InstrItinData<IIC_iCMOVi  , [InstrStage<1, [FU_Pipe0]>]>,
+  InstrItinData<IIC_iCMOVr  , [InstrStage<1, [FU_Pipe0]>]>,
+  InstrItinData<IIC_iCMOVsi , [InstrStage<1, [FU_Pipe0]>]>,
+  InstrItinData<IIC_iCMOVsr , [InstrStage<1, [FU_Pipe0]>]>,
+  InstrItinData<IIC_iMUL16  , [InstrStage<1, [FU_Pipe0]>]>,
+  InstrItinData<IIC_iMAC16  , [InstrStage<1, [FU_Pipe0]>]>,
+  InstrItinData<IIC_iMUL32  , [InstrStage<1, [FU_Pipe0]>]>,
+  InstrItinData<IIC_iMAC32  , [InstrStage<1, [FU_Pipe0]>]>,
+  InstrItinData<IIC_iMUL64  , [InstrStage<1, [FU_Pipe0]>]>,
+  InstrItinData<IIC_iMAC64  , [InstrStage<1, [FU_Pipe0]>]>,
+  InstrItinData<IIC_iLoadi  , [InstrStage<1, [FU_Pipe0]>,
                                InstrStage<1, [FU_LdSt0]>]>,
-  InstrItinData<IIC_iStore  , [InstrStage<1, [FU_Pipe0]>]>,
+  InstrItinData<IIC_iLoadr  , [InstrStage<1, [FU_Pipe0]>,
+                               InstrStage<1, [FU_LdSt0]>]>,
+  InstrItinData<IIC_iLoadsi , [InstrStage<1, [FU_Pipe0]>,
+                               InstrStage<1, [FU_LdSt0]>]>,
+  InstrItinData<IIC_iLoadiu , [InstrStage<1, [FU_Pipe0]>,
+                               InstrStage<1, [FU_LdSt0]>]>,
+  InstrItinData<IIC_iLoadru , [InstrStage<1, [FU_Pipe0]>,
+                               InstrStage<1, [FU_LdSt0]>]>,
+  InstrItinData<IIC_iLoadsiu, [InstrStage<1, [FU_Pipe0]>,
+                               InstrStage<1, [FU_LdSt0]>]>,
+  InstrItinData<IIC_iLoadm  , [InstrStage<2, [FU_Pipe0]>,
+                               InstrStage<2, [FU_LdSt0]>]>,
+  InstrItinData<IIC_iStorei  , [InstrStage<1, [FU_Pipe0]>]>,
+  InstrItinData<IIC_iStorer  , [InstrStage<1, [FU_Pipe0]>]>,
+  InstrItinData<IIC_iStoresi , [InstrStage<1, [FU_Pipe0]>]>,
+  InstrItinData<IIC_iStoreiu , [InstrStage<1, [FU_Pipe0]>]>,
+  InstrItinData<IIC_iStoreru , [InstrStage<1, [FU_Pipe0]>]>,
+  InstrItinData<IIC_iStoresiu, [InstrStage<1, [FU_Pipe0]>]>,
+  InstrItinData<IIC_iStorem  , [InstrStage<2, [FU_Pipe0]>]>,
   InstrItinData<IIC_Br      , [InstrStage<1, [FU_Pipe0]>]>,
   InstrItinData<IIC_fpALU   , [InstrStage<1, [FU_Pipe0]>]>,
   InstrItinData<IIC_fpMPY   , [InstrStage<1, [FU_Pipe0]>]>,