Remove refs to non-DebugLoc versions of BuildMI from ARM.

[oota-llvm.git] / lib / Target / ARM / ARMLoadStoreOptimizer.cpp

diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index 8126f0f7725b2418fd7f5dd32eb4067fc1d595fe..710bc3e90ef6275b73d63ef0ab604ffbf903b425 100644 (file)
--- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -2,8 +2,8 @@
 //
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by Evan Cheng and is distributed under the
-// University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
@@ -26,7 +26,7 @@
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/RegisterScavenging.h"
 #include "llvm/Support/Compiler.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
 using namespace llvm;
@@ -39,10 +39,10 @@ STATISTIC(NumFSTMGened, "Number of fstm instructions generated");
 namespace {
   struct VISIBILITY_HIDDEN ARMLoadStoreOpt : public MachineFunctionPass {
     static char ID;
-    ARMLoadStoreOpt() : MachineFunctionPass((intptr_t)&ID) {}
+    ARMLoadStoreOpt() : MachineFunctionPass(&ID) {}
 
     const TargetInstrInfo *TII;
-    const MRegisterInfo *MRI;
+    const TargetRegisterInfo *TRI;
     ARMFunctionInfo *AFI;
     RegScavenger *RS;
 
@@ -116,6 +116,8 @@ static bool mergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
                      ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
                      SmallVector<std::pair<unsigned, bool>, 8> &Regs,
                      const TargetInstrInfo *TII) {
+  // FIXME would it be better to take a DL from one of the loads arbitrarily?
+  DebugLoc dl = DebugLoc::getUnknownLoc();
   // Only a single register to load / store. Don't bother.
   unsigned NumRegs = Regs.size();
   if (NumRegs <= 1)
@@ -156,7 +158,7 @@ static bool mergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
     if (ImmedOffset == -1)
       return false;  // Probably not worth it then.
 
-    BuildMI(MBB, MBBI, TII->get(BaseOpc), NewBase)
+    BuildMI(MBB, MBBI, dl, TII->get(BaseOpc), NewBase)
       .addReg(Base, false, false, BaseKill).addImm(ImmedOffset)
       .addImm(Pred).addReg(PredReg).addReg(0);
     Base = NewBase;
@@ -167,9 +169,11 @@ static bool mergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
   bool isDef = Opcode == ARM::LDR || Opcode == ARM::FLDS || Opcode == ARM::FLDD;
   Opcode = getLoadStoreMultipleOpcode(Opcode);
   MachineInstrBuilder MIB = (isAM4)
-    ? BuildMI(MBB, MBBI, TII->get(Opcode)).addReg(Base, false, false, BaseKill)
+    ? BuildMI(MBB, MBBI, dl, TII->get(Opcode))
+        .addReg(Base, false, false, BaseKill)
         .addImm(ARM_AM::getAM4ModeImm(Mode)).addImm(Pred).addReg(PredReg)
-    : BuildMI(MBB, MBBI, TII->get(Opcode)).addReg(Base, false, false, BaseKill)
+    : BuildMI(MBB, MBBI, dl, TII->get(Opcode))
+        .addReg(Base, false, false, BaseKill)
         .addImm(ARM_AM::getAM5Opc(Mode, false, isDPR ? NumRegs<<1 : NumRegs))
         .addImm(Pred).addReg(PredReg);
   for (unsigned i = 0; i != NumRegs; ++i)
@@ -255,7 +259,7 @@ static ARMCC::CondCodes getInstrPredicate(MachineInstr *MI, unsigned &PredReg) {
   }
 
   PredReg = MI->getOperand(PIdx+1).getReg();
-  return (ARMCC::CondCodes)MI->getOperand(PIdx).getImmedValue();
+  return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
 }
 
 static inline bool isMatchingDecrement(MachineInstr *MI, unsigned Base,
@@ -450,6 +454,7 @@ static bool mergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
   bool BaseKill = MI->getOperand(1).isKill();
   unsigned Bytes = getLSMultipleTransferSize(MI);
   int Opcode = MI->getOpcode();
+  DebugLoc dl = MI->getDebugLoc();
   bool isAM2 = Opcode == ARM::LDR || Opcode == ARM::STR;
   if ((isAM2 && ARM_AM::getAM2Offset(MI->getOperand(3).getImm()) != 0) ||
       (!isAM2 && ARM_AM::getAM5Offset(MI->getOperand(2).getImm()) != 0))
@@ -510,24 +515,25 @@ static bool mergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
   if (isLd) {
     if (isAM2)
       // LDR_PRE, LDR_POST;
-      BuildMI(MBB, MBBI, TII->get(NewOpc), MI->getOperand(0).getReg())
+      BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg())
         .addReg(Base, true)
         .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
     else
       // FLDMS, FLDMD
-      BuildMI(MBB, MBBI, TII->get(NewOpc)).addReg(Base, false, false, BaseKill)
+      BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
+        .addReg(Base, false, false, BaseKill)
         .addImm(Offset).addImm(Pred).addReg(PredReg)
         .addReg(MI->getOperand(0).getReg(), true);
   } else {
     MachineOperand &MO = MI->getOperand(0);
     if (isAM2)
       // STR_PRE, STR_POST;
-      BuildMI(MBB, MBBI, TII->get(NewOpc), Base)
+      BuildMI(MBB, MBBI, dl, TII->get(NewOpc), Base)
         .addReg(MO.getReg(), false, false, MO.isKill())
         .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
     else
       // FSTMS, FSTMD
-      BuildMI(MBB, MBBI, TII->get(NewOpc)).addReg(Base).addImm(Offset)
+      BuildMI(MBB, MBBI, dl, TII->get(NewOpc)).addReg(Base).addImm(Offset)
         .addImm(Pred).addReg(PredReg)
         .addReg(MO.getReg(), false, false, MO.isKill());
   }
@@ -544,13 +550,13 @@ static bool isMemoryOp(MachineInstr *MI) {
   default: break;
   case ARM::LDR:
   case ARM::STR:
-    return MI->getOperand(1).isRegister() && MI->getOperand(2).getReg() == 0;
+    return MI->getOperand(1).isReg() && MI->getOperand(2).getReg() == 0;
   case ARM::FLDS:
   case ARM::FSTS:
-    return MI->getOperand(1).isRegister();
+    return MI->getOperand(1).isReg();
   case ARM::FLDD:
   case ARM::FSTD:
-    return MI->getOperand(1).isRegister();
+    return MI->getOperand(1).isReg();
   }
   return false;
 }
@@ -599,8 +605,8 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
       unsigned Base = MBBI->getOperand(1).getReg();
       unsigned PredReg = 0;
       ARMCC::CondCodes Pred = getInstrPredicate(MBBI, PredReg);
-      const TargetInstrDescriptor *TID = MBBI->getInstrDescriptor();
-      unsigned OffField = MBBI->getOperand(TID->numOperands-3).getImm();
+      unsigned NumOperands = MBBI->getDesc().getNumOperands();
+      unsigned OffField = MBBI->getOperand(NumOperands-3).getImm();
       int Offset = isAM2
         ? ARM_AM::getAM2Offset(OffField) : ARM_AM::getAM5Offset(OffField) * 4;
       if (isAM2) {
@@ -741,7 +747,7 @@ bool ARMLoadStoreOpt::MergeReturnIntoLDM(MachineBasicBlock &MBB) {
     if (PrevMI->getOpcode() == ARM::LDM) {
       MachineOperand &MO = PrevMI->getOperand(PrevMI->getNumOperands()-1);
       if (MO.getReg() == ARM::LR) {
-        PrevMI->setInstrDescriptor(TII->get(ARM::LDM_RET));
+        PrevMI->setDesc(TII->get(ARM::LDM_RET));
         MO.setReg(ARM::PC);
         MBB.erase(MBBI);
         return true;
@@ -755,7 +761,7 @@ bool ARMLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
   const TargetMachine &TM = Fn.getTarget();
   AFI = Fn.getInfo<ARMFunctionInfo>();
   TII = TM.getInstrInfo();
-  MRI = TM.getRegisterInfo();
+  TRI = TM.getRegisterInfo();
   RS = new RegScavenger();
 
   bool Modified = false;