return true;
case ARM::MOVr:
case ARM::tMOVr:
- assert(MI.getInstrDescriptor()->numOperands >= 2 &&
+ assert(MI.getDesc()->numOperands >= 2 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
"Invalid ARM MOV instruction");
return NULL;
MachineInstr *MI = MBBI;
- unsigned TSFlags = MI->getInstrDescriptor()->TSFlags;
+ unsigned TSFlags = MI->getDesc()->TSFlags;
bool isPre = false;
switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
default: return NULL;
MachineInstr *UpdateMI = NULL;
MachineInstr *MemMI = NULL;
unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
- const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
+ const TargetInstrDescriptor *TID = MI->getDesc();
unsigned NumOps = TID->numOperands;
bool isLoad = TID->isSimpleLoad();
const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
bool ARMInstrInfo::DefinesPredicate(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const {
- const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
+ const TargetInstrDescriptor *TID = MI->getDesc();
if (!TID->ImplicitDefs && (TID->Flags & M_HAS_OPTIONAL_DEF) == 0)
return false;
const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo();
// Basic size info comes from the TSFlags field.
- const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
+ const TargetInstrDescriptor *TID = MI->getDesc();
unsigned TSFlags = TID->TSFlags;
switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
// jumptable. The size is 4 + 4 * number of entries.
unsigned NumOps = TID->numOperands;
MachineOperand JTOP =
- MI->getOperand(NumOps - ((TID->Flags & M_PREDICABLE) ? 3 : 2));
+ MI->getOperand(NumOps - (TID->isPredicable() ? 3 : 2));
unsigned JTI = JTOP.getIndex();
MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();