Move get[S|U]LEB128Size() to LEB128.h.

[oota-llvm.git] / lib / Target / ARM / ARMFeatures.h

diff --git a/lib/Target/ARM/ARMFeatures.h b/lib/Target/ARM/ARMFeatures.h
index eaec0507410c991e34fb75cd7ad03600594ea3da..2580f7bf7f4c4930c880a0442b26a082487eb89c 100644 (file)
--- a/lib/Target/ARM/ARMFeatures.h
+++ b/lib/Target/ARM/ARMFeatures.h
@@ -16,10 +16,10 @@
 
 #include "ARM.h"
 
-using namespace llvm;
+namespace llvm {
 
 template<typename InstrType> // could be MachineInstr or MCInst
-bool isV8EligibleForIT(InstrType *Instr, int BLXOperandIndex=0) {
+inline bool isV8EligibleForIT(InstrType *Instr) {
   switch (Instr->getOpcode()) {
   default:
     return false;
@@ -70,14 +70,13 @@ bool isV8EligibleForIT(InstrType *Instr, int BLXOperandIndex=0) {
     return true;
 // there are some "conditionally deprecated" opcodes
   case ARM::tADDspr:
+  case ARM::tBLXr:
     return Instr->getOperand(2).getReg() != ARM::PC;
   // ADD PC, SP and BLX PC were always unpredictable,
   // now on top of it they're deprecated
   case ARM::tADDrSP:
   case ARM::tBX:
     return Instr->getOperand(0).getReg() != ARM::PC;
-  case ARM::tBLXr:
-    return Instr->getOperand(BLXOperandIndex).getReg() != ARM::PC;
   case ARM::tADDhirr:
     return Instr->getOperand(0).getReg() != ARM::PC &&
            Instr->getOperand(2).getReg() != ARM::PC;
@@ -88,4 +87,6 @@ bool isV8EligibleForIT(InstrType *Instr, int BLXOperandIndex=0) {
   }
 }
 
+}
+
 #endif