//
//===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "arm-emitter"
+#define DEBUG_TYPE "jit"
+#include "ARM.h"
+#include "ARMAddressingModes.h"
+#include "ARMConstantPoolValue.h"
#include "ARMInstrInfo.h"
+#include "ARMRelocations.h"
#include "ARMSubtarget.h"
#include "ARMTargetMachine.h"
-#include "ARMRelocations.h"
-#include "ARMAddressingModes.h"
-#include "ARM.h"
+#include "llvm/Constants.h"
+#include "llvm/DerivedTypes.h"
+#include "llvm/Function.h"
#include "llvm/PassManager.h"
#include "llvm/CodeGen/MachineCodeEmitter.h"
+#include "llvm/CodeGen/JITCodeEmitter.h"
+#include "llvm/CodeGen/ObjectCodeEmitter.h"
+#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/Passes.h"
-#include "llvm/Function.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Support/Compiler.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
+#ifndef NDEBUG
+#include <iomanip>
+#endif
using namespace llvm;
STATISTIC(NumEmitted, "Number of machine instructions emitted");
namespace {
- class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass {
- const ARMInstrInfo *II;
- const TargetData *TD;
- TargetMachine &TM;
- MachineCodeEmitter &MCE;
+
+ class ARMCodeEmitter {
+ public:
+ /// getBinaryCodeForInstr - This function, generated by the
+ /// CodeEmitterGenerator using TableGen, produces the binary encoding for
+ /// machine instructions.
+ unsigned getBinaryCodeForInstr(const MachineInstr &MI);
+ };
+
+ template<class CodeEmitter>
+ class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass,
+ public ARMCodeEmitter {
+ ARMJITInfo *JTI;
+ const ARMInstrInfo *II;
+ const TargetData *TD;
+ TargetMachine &TM;
+ CodeEmitter &MCE;
+ const std::vector<MachineConstantPoolEntry> *MCPEs;
+ const std::vector<MachineJumpTableEntry> *MJTEs;
+ bool IsPIC;
+
public:
static char ID;
- explicit Emitter(TargetMachine &tm, MachineCodeEmitter &mce)
- : MachineFunctionPass((intptr_t)&ID), II(0), TD(0), TM(tm),
- MCE(mce) {}
- Emitter(TargetMachine &tm, MachineCodeEmitter &mce,
+ explicit Emitter(TargetMachine &tm, CodeEmitter &mce)
+ : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
+ MCE(mce), MCPEs(0), MJTEs(0),
+ IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
+ Emitter(TargetMachine &tm, CodeEmitter &mce,
const ARMInstrInfo &ii, const TargetData &td)
- : MachineFunctionPass((intptr_t)&ID), II(&ii), TD(&td), TM(tm),
- MCE(mce) {}
+ : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
+ MCE(mce), MCPEs(0), MJTEs(0),
+ IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
bool runOnMachineFunction(MachineFunction &MF);
}
void emitInstruction(const MachineInstr &MI);
- int getMachineOpValue(const MachineInstr &MI, unsigned OpIndex);
- unsigned getBaseOpcodeFor(const TargetInstrDescriptor *TID);
- unsigned getBinaryCodeForInstr(const MachineInstr &MI);
-
- void emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub);
- void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
- void emitConstPoolAddress(unsigned CPI, unsigned Reloc,
- int Disp = 0, unsigned PCAdj = 0 );
- void emitJumpTableAddress(unsigned JTI, unsigned Reloc,
- unsigned PCAdj = 0);
- void emitGlobalConstant(const Constant *CV);
- void emitMachineBasicBlock(MachineBasicBlock *BB);
private:
- int getShiftOp(const MachineOperand &MO);
+ void emitWordLE(unsigned Binary);
+
+ void emitDWordLE(uint64_t Binary);
+
+ void emitConstPoolInstruction(const MachineInstr &MI);
+
+ void emitMOVi2piecesInstruction(const MachineInstr &MI);
+
+ void emitLEApcrelJTInstruction(const MachineInstr &MI);
+
+ void emitPseudoMoveInstruction(const MachineInstr &MI);
+
+ void addPCLabel(unsigned LabelID);
+
+ void emitPseudoInstruction(const MachineInstr &MI);
+
+ unsigned getMachineSoRegOpValue(const MachineInstr &MI,
+ const TargetInstrDesc &TID,
+ const MachineOperand &MO,
+ unsigned OpIdx);
+
+ unsigned getMachineSoImmOpValue(unsigned SoImm);
+
+ unsigned getAddrModeSBit(const MachineInstr &MI,
+ const TargetInstrDesc &TID) const;
+
+ void emitDataProcessingInstruction(const MachineInstr &MI,
+ unsigned ImplicitRd = 0,
+ unsigned ImplicitRn = 0);
+
+ void emitLoadStoreInstruction(const MachineInstr &MI,
+ unsigned ImplicitRd = 0,
+ unsigned ImplicitRn = 0);
+
+ void emitMiscLoadStoreInstruction(const MachineInstr &MI,
+ unsigned ImplicitRn = 0);
+
+ void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
+
+ void emitMulFrmInstruction(const MachineInstr &MI);
+
+ void emitExtendInstruction(const MachineInstr &MI);
+
+ void emitMiscArithInstruction(const MachineInstr &MI);
+
+ void emitBranchInstruction(const MachineInstr &MI);
+
+ void emitInlineJumpTable(unsigned JTIndex);
+
+ void emitMiscBranchInstruction(const MachineInstr &MI);
+
+ void emitVFPArithInstruction(const MachineInstr &MI);
+
+ void emitVFPConversionInstruction(const MachineInstr &MI);
+
+ void emitVFPLoadStoreInstruction(const MachineInstr &MI);
+
+ void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
+
+ void emitMiscInstruction(const MachineInstr &MI);
+
+ /// getMachineOpValue - Return binary encoding of operand. If the machine
+ /// operand requires relocation, record the relocation and return zero.
+ unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
+ unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
+ return getMachineOpValue(MI, MI.getOperand(OpIdx));
+ }
+
+ /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
+ ///
+ unsigned getShiftOp(unsigned Imm) const ;
+
+ /// Routines that handle operands which add machine relocations which are
+ /// fixed up by the relocation stage.
+ void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
+ bool NeedStub, intptr_t ACPV = 0);
+ void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
+ void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
+ void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
+ void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
+ intptr_t JTBase = 0);
};
- char Emitter::ID = 0;
+ template <class CodeEmitter>
+ char Emitter<CodeEmitter>::ID = 0;
}
/// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
/// to the specified MCE object.
-FunctionPass *llvm::createARMCodeEmitterPass(ARMTargetMachine &TM,
+
+FunctionPass *llvm::createARMCodeEmitterPass(ARMBaseTargetMachine &TM,
MachineCodeEmitter &MCE) {
- return new Emitter(TM, MCE);
+ return new Emitter<MachineCodeEmitter>(TM, MCE);
+}
+FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
+ JITCodeEmitter &JCE) {
+ return new Emitter<JITCodeEmitter>(TM, JCE);
+}
+FunctionPass *llvm::createARMObjectCodeEmitterPass(ARMBaseTargetMachine &TM,
+ ObjectCodeEmitter &OCE) {
+ return new Emitter<ObjectCodeEmitter>(TM, OCE);
}
-bool Emitter::runOnMachineFunction(MachineFunction &MF) {
+template<class CodeEmitter>
+bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
MF.getTarget().getRelocationModel() != Reloc::Static) &&
"JIT relocation model must be set to static or default!");
II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
+ JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
+ MCPEs = &MF.getConstantPool()->getConstants();
+ MJTEs = &MF.getJumpTableInfo()->getJumpTables();
+ IsPIC = TM.getRelocationModel() == Reloc::PIC_;
+ JTI->Initialize(MF, IsPIC);
do {
+ DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
MCE.startFunction(MF);
for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
MBB != E; ++MBB) {
return false;
}
-/// getBaseOpcodeFor - Return the opcode value
-unsigned Emitter::getBaseOpcodeFor(const TargetInstrDescriptor *TID) {
- return (TID->TSFlags & ARMII::OpcodeMask) >> ARMII::OpcodeShift;
+/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
+///
+template<class CodeEmitter>
+unsigned Emitter<CodeEmitter>::getShiftOp(unsigned Imm) const {
+ switch (ARM_AM::getAM2ShiftOpc(Imm)) {
+ default: LLVM_UNREACHABLE("Unknown shift opc!");
+ case ARM_AM::asr: return 2;
+ case ARM_AM::lsl: return 0;
+ case ARM_AM::lsr: return 1;
+ case ARM_AM::ror:
+ case ARM_AM::rrx: return 3;
+ }
+ return 0;
}
-/// getShiftOp - Verify which is the shift opcode (bit[6:5]) of the
-/// machine operand.
-int Emitter::getShiftOp(const MachineOperand &MO) {
- unsigned ShiftOp = 0x0;
- switch(ARM_AM::getAM2ShiftOpc(MO.getImm())) {
- default: assert(0 && "Unknown shift opc!");
- case ARM_AM::asr:
- ShiftOp = 0X2;
- break;
- case ARM_AM::lsl:
- ShiftOp = 0X0;
- break;
- case ARM_AM::lsr:
- ShiftOp = 0X1;
- break;
- case ARM_AM::ror:
- case ARM_AM::rrx:
- ShiftOp = 0X3;
- break;
- }
- return ShiftOp;
-}
-
-int Emitter::getMachineOpValue(const MachineInstr &MI, unsigned OpIndex) {
- intptr_t rv = 0;
- const MachineOperand &MO = MI.getOperand(OpIndex);
- if (MO.isRegister()) {
- assert(MRegisterInfo::isPhysicalRegister(MO.getReg()));
- rv = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
- } else if (MO.isImmediate()) {
- rv = MO.getImm();
- } else if (MO.isGlobalAddress()) {
- emitGlobalAddressForCall(MO.getGlobal(), false);
- } else if (MO.isExternalSymbol()) {
- emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_relative);
- } else if (MO.isConstantPoolIndex()) {
- emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_relative);
- } else if (MO.isJumpTableIndex()) {
+/// getMachineOpValue - Return binary encoding of operand. If the machine
+/// operand requires relocation, record the relocation and return zero.
+template<class CodeEmitter>
+unsigned Emitter<CodeEmitter>::getMachineOpValue(const MachineInstr &MI,
+ const MachineOperand &MO) {
+ if (MO.isReg())
+ return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
+ else if (MO.isImm())
+ return static_cast<unsigned>(MO.getImm());
+ else if (MO.isGlobal())
+ emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true);
+ else if (MO.isSymbol())
+ emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
+ else if (MO.isCPI()) {
+ const TargetInstrDesc &TID = MI.getDesc();
+ // For VFP load, the immediate offset is multiplied by 4.
+ unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
+ ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
+ emitConstPoolAddress(MO.getIndex(), Reloc);
+ } else if (MO.isJTI())
emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
- } else if (MO.isMachineBasicBlock()) {
- emitMachineBasicBlock(MO.getMBB());
+ else if (MO.isMBB())
+ emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
+ else {
+#ifndef NDEBUG
+ cerr << MO;
+#endif
+ llvm_unreachable();
}
-
- return rv;
+ return 0;
}
-/// emitGlobalAddressForCall - Emit the specified address to the code stream
-/// assuming this is part of a function call, which is PC relative.
+/// emitGlobalAddress - Emit the specified address to the code stream.
///
-void Emitter::emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub) {
- MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
- ARM::reloc_arm_branch, GV, 0,
- DoesntNeedStub));
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
+ bool NeedStub, intptr_t ACPV) {
+ MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
+ GV, ACPV, NeedStub));
}
/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
/// be emitted to the current location in the function, and allow it to be PC
/// relative.
-void Emitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES,
+ unsigned Reloc) {
MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
Reloc, ES));
}
/// emitConstPoolAddress - Arrange for the address of an constant pool
/// to be emitted to the current location in the function, and allow it to be PC
/// relative.
-void Emitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
- int Disp /* = 0 */,
- unsigned PCAdj /* = 0 */) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI,
+ unsigned Reloc) {
+ // Tell JIT emitter we'll resolve the address.
MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
- Reloc, CPI, PCAdj));
+ Reloc, CPI, 0, true));
}
/// emitJumpTableAddress - Arrange for the address of a jump table to
/// be emitted to the current location in the function, and allow it to be PC
/// relative.
-void Emitter::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
- unsigned PCAdj /* = 0 */) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTIndex,
+ unsigned Reloc) {
MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
- Reloc, JTI, PCAdj));
+ Reloc, JTIndex, 0, true));
}
/// emitMachineBasicBlock - Emit the specified address basic block.
-void Emitter::emitMachineBasicBlock(MachineBasicBlock *BB) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitMachineBasicBlock(MachineBasicBlock *BB,
+ unsigned Reloc, intptr_t JTBase) {
MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
- ARM::reloc_arm_branch, BB));
+ Reloc, BB, JTBase));
+}
+
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitWordLE(unsigned Binary) {
+#ifndef NDEBUG
+ DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
+ << Binary << std::dec << "\n";
+#endif
+ MCE.emitWordLE(Binary);
+}
+
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitDWordLE(uint64_t Binary) {
+#ifndef NDEBUG
+ DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
+ << (unsigned)Binary << std::dec << "\n";
+ DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
+ << (unsigned)(Binary >> 32) << std::dec << "\n";
+#endif
+ MCE.emitDWordLE(Binary);
}
-void Emitter::emitInstruction(const MachineInstr &MI) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI) {
+ DOUT << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI;
+
NumEmitted++; // Keep track of the # of mi's emitted
- MCE.emitWordLE(getBinaryCodeForInstr(MI));
-}
-
-unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
- const TargetInstrDescriptor *Desc = MI.getInstrDescriptor();
- const unsigned opcode = MI.getOpcode();
- // initial instruction mask
- unsigned Value = 0xE0000000;
- unsigned op;
-
- switch (Desc->TSFlags & ARMII::AddrModeMask) {
- case ARMII::AddrModeNone: {
- switch(Desc->TSFlags & ARMII::FormMask) {
- default: {
- assert(0 && "Unknown instruction subtype!");
- // treat special instruction CLZ
- if(opcode == ARM::CLZ) {
- // set first operand
- op = getMachineOpValue(MI,0);
- Value |= op << ARMII::RegRdShift;
-
- // set second operand
- op = getMachineOpValue(MI,1);
- Value |= op;
- }
- break;
- }
- case ARMII::MulSMLAW:
- case ARMII::MulSMULW:
- // set bit W(21)
- Value |= 1 << 21;
- case ARMII::MulSMLA:
- case ARMII::MulSMUL: {
- // set bit W(21)
- Value |= 1 << 24;
-
- // set opcode (bit[7:4]). For more information, see ARM-ARM page A3-31
- // SMLA<x><y> - 1yx0
- // SMLAW<y> - 1y00
- // SMULW<y> - 1y10
- // SMUL<x><y> - 1yx0
- unsigned char BaseOpcode = getBaseOpcodeFor(Desc);
- Value |= BaseOpcode << 4;
-
- unsigned Format = (Desc->TSFlags & ARMII::FormMask);
- if (Format == ARMII::MulSMUL)
- Value |= 1 << 22;
-
- // set first operand
- op = getMachineOpValue(MI,0);
- Value |= op << ARMII::RegRnShift;
-
- // set second operand
- op = getMachineOpValue(MI,1);
- Value |= op;
-
- // set third operand
- op = getMachineOpValue(MI,2);
- Value |= op << ARMII::RegRsShift;
-
- // instructions SMLA and SMLAW have a fourth operand
- if (Format != ARMII::MulSMULW && Format != ARMII::MulSMUL) {
- op = getMachineOpValue(MI,3);
- Value |= op << ARMII::RegRdShift;
- }
+ switch (MI.getDesc().TSFlags & ARMII::FormMask) {
+ default: {
+ LLVM_UNREACHABLE("Unhandled instruction encoding format!");
+ break;
+ }
+ case ARMII::Pseudo:
+ emitPseudoInstruction(MI);
+ break;
+ case ARMII::DPFrm:
+ case ARMII::DPSoRegFrm:
+ emitDataProcessingInstruction(MI);
+ break;
+ case ARMII::LdFrm:
+ case ARMII::StFrm:
+ emitLoadStoreInstruction(MI);
+ break;
+ case ARMII::LdMiscFrm:
+ case ARMII::StMiscFrm:
+ emitMiscLoadStoreInstruction(MI);
+ break;
+ case ARMII::LdStMulFrm:
+ emitLoadStoreMultipleInstruction(MI);
+ break;
+ case ARMII::MulFrm:
+ emitMulFrmInstruction(MI);
+ break;
+ case ARMII::ExtFrm:
+ emitExtendInstruction(MI);
+ break;
+ case ARMII::ArithMiscFrm:
+ emitMiscArithInstruction(MI);
+ break;
+ case ARMII::BrFrm:
+ emitBranchInstruction(MI);
+ break;
+ case ARMII::BrMiscFrm:
+ emitMiscBranchInstruction(MI);
+ break;
+ // VFP instructions.
+ case ARMII::VFPUnaryFrm:
+ case ARMII::VFPBinaryFrm:
+ emitVFPArithInstruction(MI);
+ break;
+ case ARMII::VFPConv1Frm:
+ case ARMII::VFPConv2Frm:
+ case ARMII::VFPConv3Frm:
+ case ARMII::VFPConv4Frm:
+ case ARMII::VFPConv5Frm:
+ emitVFPConversionInstruction(MI);
+ break;
+ case ARMII::VFPLdStFrm:
+ emitVFPLoadStoreInstruction(MI);
+ break;
+ case ARMII::VFPLdStMulFrm:
+ emitVFPLoadStoreMultipleInstruction(MI);
+ break;
+ case ARMII::VFPMiscFrm:
+ emitMiscInstruction(MI);
+ break;
+ }
+}
- break;
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitConstPoolInstruction(const MachineInstr &MI) {
+ unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
+ unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
+ const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
+
+ // Remember the CONSTPOOL_ENTRY address for later relocation.
+ JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
+
+ // Emit constpool island entry. In most cases, the actual values will be
+ // resolved and relocated after code emission.
+ if (MCPE.isMachineConstantPoolEntry()) {
+ ARMConstantPoolValue *ACPV =
+ static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
+
+ DOUT << " ** ARM constant pool #" << CPI << " @ "
+ << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n';
+
+ GlobalValue *GV = ACPV->getGV();
+ if (GV) {
+ assert(!ACPV->isStub() && "Don't know how to deal this yet!");
+ if (ACPV->isNonLazyPointer())
+ MCE.addRelocation(MachineRelocation::getIndirectSymbol(
+ MCE.getCurrentPCOffset(), ARM::reloc_arm_machine_cp_entry, GV,
+ (intptr_t)ACPV, false));
+ else
+ emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
+ ACPV->isStub() || isa<Function>(GV), (intptr_t)ACPV);
+ } else {
+ assert(!ACPV->isNonLazyPointer() && "Don't know how to deal this yet!");
+ emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
}
- case ARMII::MulFrm: {
- // bit[7:4] is always 9
- Value |= 9 << 4;
- // set opcode (bit[23:20])
- unsigned char BaseOpcode = getBaseOpcodeFor(Desc);
- Value |= BaseOpcode << 20;
-
- bool isMUL = opcode == ARM::MUL;
- bool isMLA = opcode == ARM::MLA;
-
- // set first operand
- op = getMachineOpValue(MI,0);
- Value |= op << (isMUL || isMLA ? ARMII::RegRnShift : ARMII::RegRdShift);
-
- // set second operand
- op = getMachineOpValue(MI,1);
- Value |= op << (isMUL || isMLA ? 0 : ARMII::RegRnShift);
-
- // set third operand
- op = getMachineOpValue(MI,2);
- Value |= op << (isMUL || isMLA ? ARMII::RegRsShift : 0);
-
- // multiply instructions (except MUL), have a fourth operand
- if (!isMUL) {
- op = getMachineOpValue(MI,3);
- Value |= op << (isMLA ? ARMII::RegRdShift : ARMII::RegRsShift);
+ emitWordLE(0);
+ } else {
+ Constant *CV = MCPE.Val.ConstVal;
+
+#ifndef NDEBUG
+ DOUT << " ** Constant pool #" << CPI << " @ "
+ << (void*)MCE.getCurrentPCValue() << " ";
+ if (const Function *F = dyn_cast<Function>(CV))
+ DOUT << F->getName();
+ else
+ DOUT << *CV;
+ DOUT << '\n';
+#endif
+
+ if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
+ emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV));
+ emitWordLE(0);
+ } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
+ uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
+ emitWordLE(Val);
+ } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
+ if (CFP->getType() == Type::FloatTy)
+ emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
+ else if (CFP->getType() == Type::DoubleTy)
+ emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
+ else {
+ LLVM_UNREACHABLE("Unable to handle this constantpool entry!");
}
-
- break;
+ } else {
+ LLVM_UNREACHABLE("Unable to handle this constantpool entry!");
}
- case ARMII::Branch: {
- // set opcode (bit[27:24])
- unsigned BaseOpcode = getBaseOpcodeFor(Desc);
- Value |= BaseOpcode << 24;
-
- // set signed_immed_24 field
- op = getMachineOpValue(MI,0);
- Value |= op;
-
- // if it is a conditional branch, set cond field
- if (opcode == ARM::Bcc) {
- op = getMachineOpValue(MI,1);
- Value &= 0x0FFFFFFF; // clear conditional field
- Value |= op << 28; // set conditional field
- }
+ }
+}
- break;
- }
- case ARMII::BranchMisc: {
- // set opcode (bit[7:4])
- unsigned char BaseOpcode = getBaseOpcodeFor(Desc);
- Value |= BaseOpcode << 4;
- // set bit[27:24] to 1, set bit[23:20] to 2 and set bit[19:8] to 0xFFF
- Value |= 0x12fff << 8;
-
- if (opcode == ARM::BX_RET)
- op = 0xe; // the return register is LR
- else
- // otherwise, set the return register
- op = getMachineOpValue(MI,0);
- Value |= op;
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitMOVi2piecesInstruction(const MachineInstr &MI) {
+ const MachineOperand &MO0 = MI.getOperand(0);
+ const MachineOperand &MO1 = MI.getOperand(1);
+ assert(MO1.isImm() && ARM_AM::getSOImmVal(MO1.isImm()) != -1 &&
+ "Not a valid so_imm value!");
+ unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
+ unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
- break;
- }
- case ARMII::Pseudo:
- break;
- }
+ // Emit the 'mov' instruction.
+ unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
+
+ // Set the conditional execution predicate.
+ Binary |= II->getPredicate(&MI) << ARMII::CondShift;
+
+ // Encode Rd.
+ Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
+
+ // Encode so_imm.
+ // Set bit I(25) to identify this is the immediate form of <shifter_op>
+ Binary |= 1 << ARMII::I_BitShift;
+ Binary |= getMachineSoImmOpValue(V1);
+ emitWordLE(Binary);
+
+ // Now the 'orr' instruction.
+ Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
+
+ // Set the conditional execution predicate.
+ Binary |= II->getPredicate(&MI) << ARMII::CondShift;
+
+ // Encode Rd.
+ Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
+
+ // Encode Rn.
+ Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
+
+ // Encode so_imm.
+ // Set bit I(25) to identify this is the immediate form of <shifter_op>
+ Binary |= 1 << ARMII::I_BitShift;
+ Binary |= getMachineSoImmOpValue(V2);
+ emitWordLE(Binary);
+}
+
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitLEApcrelJTInstruction(const MachineInstr &MI) {
+ // It's basically add r, pc, (LJTI - $+8)
+
+ const TargetInstrDesc &TID = MI.getDesc();
+
+ // Emit the 'add' instruction.
+ unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100
+
+ // Set the conditional execution predicate
+ Binary |= II->getPredicate(&MI) << ARMII::CondShift;
+
+ // Encode S bit if MI modifies CPSR.
+ Binary |= getAddrModeSBit(MI, TID);
+ // Encode Rd.
+ Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
+
+ // Encode Rn which is PC.
+ Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
+
+ // Encode the displacement.
+ Binary |= 1 << ARMII::I_BitShift;
+ emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
+
+ emitWordLE(Binary);
+}
+
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitPseudoMoveInstruction(const MachineInstr &MI) {
+ unsigned Opcode = MI.getDesc().Opcode;
+
+ // Part of binary is determined by TableGn.
+ unsigned Binary = getBinaryCodeForInstr(MI);
+
+ // Set the conditional execution predicate
+ Binary |= II->getPredicate(&MI) << ARMII::CondShift;
+
+ // Encode S bit if MI modifies CPSR.
+ if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
+ Binary |= 1 << ARMII::S_BitShift;
+
+ // Encode register def if there is one.
+ Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
+
+ // Encode the shift operation.
+ switch (Opcode) {
+ default: break;
+ case ARM::MOVrx:
+ // rrx
+ Binary |= 0x6 << 4;
+ break;
+ case ARM::MOVsrl_flag:
+ // lsr #1
+ Binary |= (0x2 << 4) | (1 << 7);
+ break;
+ case ARM::MOVsra_flag:
+ // asr #1
+ Binary |= (0x4 << 4) | (1 << 7);
break;
}
- case ARMII::AddrMode1: {
- // set opcode (bit[24:21]) of data-processing instructions
- unsigned char BaseOpcode = getBaseOpcodeFor(Desc);
- Value |= BaseOpcode << 21;
- // treat 3 special instructions: MOVsra_flag, MOVsrl_flag and
- // MOVrx.
- unsigned Format = (Desc->TSFlags & ARMII::FormMask);
- if (Format == ARMII::DPRdMisc) {
- Value |= getMachineOpValue(MI,0) << ARMII::RegRdShift;
- Value |= getMachineOpValue(MI,1);
- switch(opcode) {
- case ARM::MOVsra_flag: {
- Value |= 0x1 << 6;
- Value |= 0x1 << 7;
- break;
- }
- case ARM::MOVsrl_flag: {
- Value |= 0x1 << 5;
- Value |= 0x1 << 7;
- break;
- }
- case ARM::MOVrx: {
- Value |= 0x3 << 5;
- break;
- }
- }
- break;
- }
+ // Encode register Rm.
+ Binary |= getMachineOpValue(MI, 1);
- // Data processing operand instructions has 3 possible encodings (for more
- // information, see ARM-ARM page A3-10):
- // 1. <instr> <Rd>,<shifter_operand>
- // 2. <instr> <Rn>,<shifter_operand>
- // 3. <instr> <Rd>,<Rn>,<shifter_operand>
- bool IsDataProcessing1 = Format == ARMII::DPRdIm ||
- Format == ARMII::DPRdReg ||
- Format == ARMII::DPRdSoReg;
- bool IsDataProcessing2 = Format == ARMII::DPRnIm ||
- Format == ARMII::DPRnReg ||
- Format == ARMII::DPRnSoReg;
- bool IsDataProcessing3 = false;
-
- // set bit S(20)
- if (Format == ARMII::DPRImS || Format == ARMII::DPRRegS ||
- Format == ARMII::DPRSoRegS || IsDataProcessing2) {
- Value |= 1 << ARMII::S_BitShift;
- IsDataProcessing3 = !IsDataProcessing2;
- }
+ emitWordLE(Binary);
+}
+
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::addPCLabel(unsigned LabelID) {
+ DOUT << " ** LPC" << LabelID << " @ "
+ << (void*)MCE.getCurrentPCValue() << '\n';
+ JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
+}
- IsDataProcessing3 = Format == ARMII::DPRIm ||
- Format == ARMII::DPRReg ||
- Format == ARMII::DPRSoReg ||
- IsDataProcessing3;
-
- // set first operand
- op = getMachineOpValue(MI,0);
- if (IsDataProcessing1 || IsDataProcessing3) {
- Value |= op << ARMII::RegRdShift;
- } else if (IsDataProcessing2) {
- Value |= op << ARMII::RegRnShift;
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) {
+ unsigned Opcode = MI.getDesc().Opcode;
+ switch (Opcode) {
+ default:
+ LLVM_UNREACHABLE("ARMCodeEmitter::emitPseudoInstruction");//FIXME:
+ case TargetInstrInfo::INLINEASM: {
+ // We allow inline assembler nodes with empty bodies - they can
+ // implicitly define registers, which is ok for JIT.
+ if (MI.getOperand(0).getSymbolName()[0]) {
+ llvm_report_error("JIT does not support inline asm!");
}
+ break;
+ }
+ case TargetInstrInfo::DBG_LABEL:
+ case TargetInstrInfo::EH_LABEL:
+ MCE.emitLabel(MI.getOperand(0).getImm());
+ break;
+ case TargetInstrInfo::IMPLICIT_DEF:
+ case TargetInstrInfo::DECLARE:
+ case ARM::DWARF_LOC:
+ // Do nothing.
+ break;
+ case ARM::CONSTPOOL_ENTRY:
+ emitConstPoolInstruction(MI);
+ break;
+ case ARM::PICADD: {
+ // Remember of the address of the PC label for relocation later.
+ addPCLabel(MI.getOperand(2).getImm());
+ // PICADD is just an add instruction that implicitly read pc.
+ emitDataProcessingInstruction(MI, 0, ARM::PC);
+ break;
+ }
+ case ARM::PICLDR:
+ case ARM::PICLDRB:
+ case ARM::PICSTR:
+ case ARM::PICSTRB: {
+ // Remember of the address of the PC label for relocation later.
+ addPCLabel(MI.getOperand(2).getImm());
+ // These are just load / store instructions that implicitly read pc.
+ emitLoadStoreInstruction(MI, 0, ARM::PC);
+ break;
+ }
+ case ARM::PICLDRH:
+ case ARM::PICLDRSH:
+ case ARM::PICLDRSB:
+ case ARM::PICSTRH: {
+ // Remember of the address of the PC label for relocation later.
+ addPCLabel(MI.getOperand(2).getImm());
+ // These are just load / store instructions that implicitly read pc.
+ emitMiscLoadStoreInstruction(MI, ARM::PC);
+ break;
+ }
+ case ARM::MOVi2pieces:
+ // Two instructions to materialize a constant.
+ emitMOVi2piecesInstruction(MI);
+ break;
+ case ARM::LEApcrelJT:
+ // Materialize jumptable address.
+ emitLEApcrelJTInstruction(MI);
+ break;
+ case ARM::MOVrx:
+ case ARM::MOVsrl_flag:
+ case ARM::MOVsra_flag:
+ emitPseudoMoveInstruction(MI);
+ break;
+ }
+}
- // set second operand of data processing #3 instructions
- if (IsDataProcessing3) {
- op = getMachineOpValue(MI,1);
- Value |= op << ARMII::RegRnShift;
+template<class CodeEmitter>
+unsigned Emitter<CodeEmitter>::getMachineSoRegOpValue(
+ const MachineInstr &MI,
+ const TargetInstrDesc &TID,
+ const MachineOperand &MO,
+ unsigned OpIdx) {
+ unsigned Binary = getMachineOpValue(MI, MO);
+
+ const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
+ const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
+ ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
+
+ // Encode the shift opcode.
+ unsigned SBits = 0;
+ unsigned Rs = MO1.getReg();
+ if (Rs) {
+ // Set shift operand (bit[7:4]).
+ // LSL - 0001
+ // LSR - 0011
+ // ASR - 0101
+ // ROR - 0111
+ // RRX - 0110 and bit[11:8] clear.
+ switch (SOpc) {
+ default: LLVM_UNREACHABLE("Unknown shift opc!");
+ case ARM_AM::lsl: SBits = 0x1; break;
+ case ARM_AM::lsr: SBits = 0x3; break;
+ case ARM_AM::asr: SBits = 0x5; break;
+ case ARM_AM::ror: SBits = 0x7; break;
+ case ARM_AM::rrx: SBits = 0x6; break;
+ }
+ } else {
+ // Set shift operand (bit[6:4]).
+ // LSL - 000
+ // LSR - 010
+ // ASR - 100
+ // ROR - 110
+ switch (SOpc) {
+ default: LLVM_UNREACHABLE("Unknown shift opc!");
+ case ARM_AM::lsl: SBits = 0x0; break;
+ case ARM_AM::lsr: SBits = 0x2; break;
+ case ARM_AM::asr: SBits = 0x4; break;
+ case ARM_AM::ror: SBits = 0x6; break;
}
+ }
+ Binary |= SBits << 4;
+ if (SOpc == ARM_AM::rrx)
+ return Binary;
+
+ // Encode the shift operation Rs or shift_imm (except rrx).
+ if (Rs) {
+ // Encode Rs bit[11:8].
+ assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
+ return Binary |
+ (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
+ }
- unsigned OperandIndex = IsDataProcessing3 ? 2 : 1;
- switch (Format) {
- case ARMII::DPRdIm: case ARMII::DPRnIm:
- case ARMII::DPRIm: case ARMII::DPRImS: {
- // set bit I(25) to identify this is the immediate form of <shifter_op>
- Value |= 1 << ARMII::I_BitShift;
- // set immed_8 field
- const MachineOperand &MO = MI.getOperand(OperandIndex);
- op = ARM_AM::getSOImmVal(MO.getImm());
- Value |= op;
+ // Encode shift_imm bit[11:7].
+ return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
+}
- break;
- }
- case ARMII::DPRdReg: case ARMII::DPRnReg:
- case ARMII::DPRReg: case ARMII::DPRRegS: {
- // set last operand (register Rm)
- op = getMachineOpValue(MI,OperandIndex);
- Value |= op;
+template<class CodeEmitter>
+unsigned Emitter<CodeEmitter>::getMachineSoImmOpValue(unsigned SoImm) {
+ int SoImmVal = ARM_AM::getSOImmVal(SoImm);
+ assert(SoImmVal != -1 && "Not a valid so_imm value!");
- break;
- }
- case ARMII::DPRdSoReg: case ARMII::DPRnSoReg:
- case ARMII::DPRSoReg: case ARMII::DPRSoRegS: {
- // set last operand (register Rm)
- op = getMachineOpValue(MI,OperandIndex);
- Value |= op;
-
- const MachineOperand &MO1 = MI.getOperand(OperandIndex + 1);
- const MachineOperand &MO2 = MI.getOperand(OperandIndex + 2);
- // identify it the instr is in immed or register shifts encoding
- bool IsShiftByRegister = MO1.getReg() > 0;
- // set shift operand (bit[6:4]).
- // ASR - 101 if it is in register shifts encoding; 100, otherwise.
- // LSL - 001 if it is in register shifts encoding; 000, otherwise.
- // LSR - 011 if it is in register shifts encoding; 010, otherwise.
- // ROR - 111 if it is in register shifts encoding; 110, otherwise.
- // RRX - 110 and bit[11:7] clear.
- switch(ARM_AM::getSORegShOp(MO2.getImm())) {
- default: assert(0 && "Unknown shift opc!");
- case ARM_AM::asr: {
- if(IsShiftByRegister)
- Value |= 0x5 << 4;
- else
- Value |= 0x1 << 6;
- break;
- }
- case ARM_AM::lsl: {
- if(IsShiftByRegister)
- Value |= 0x1 << 4;
- break;
- }
- case ARM_AM::lsr: {
- if(IsShiftByRegister)
- Value |= 0x3 << 4;
- else
- Value |= 0x1 << 5;
- break;
- }
- case ARM_AM::ror: {
- if(IsShiftByRegister)
- Value |= 0x7 << 4;
- else
- Value |= 0x3 << 5;
- break;
- }
- case ARM_AM::rrx: {
- Value |= 0x3 << 5;
- break;
- }
- }
- // set the field related to shift operations (except rrx).
- if(ARM_AM::getSORegShOp(MO2.getImm()) != ARM_AM::rrx)
- if(IsShiftByRegister) {
- // set the value of bit[11:8] (register Rs).
- assert(MRegisterInfo::isPhysicalRegister(MO1.getReg()));
- op = ARMRegisterInfo::getRegisterNumbering(MO1.getReg());
- assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
- Value |= op << ARMII::RegRsShift;
- } else {
- // set the value of bit [11:7] (shift_immed field).
- op = ARM_AM::getSORegOffset(MO2.getImm());
- Value |= op << 7;
- }
- break;
- }
- default: assert(false && "Unknown operand type!");
- break;
+ // Encode rotate_imm.
+ unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
+ << ARMII::SoRotImmShift;
+
+ // Encode immed_8.
+ Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
+ return Binary;
+}
+
+template<class CodeEmitter>
+unsigned Emitter<CodeEmitter>::getAddrModeSBit(const MachineInstr &MI,
+ const TargetInstrDesc &TID) const {
+ for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
+ const MachineOperand &MO = MI.getOperand(i-1);
+ if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
+ return 1 << ARMII::S_BitShift;
+ }
+ return 0;
+}
+
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitDataProcessingInstruction(
+ const MachineInstr &MI,
+ unsigned ImplicitRd,
+ unsigned ImplicitRn) {
+ const TargetInstrDesc &TID = MI.getDesc();
+
+ if (TID.Opcode == ARM::BFC) {
+ llvm_report_error("ERROR: ARMv6t2 JIT is not yet supported.");
+ }
+
+ // Part of binary is determined by TableGn.
+ unsigned Binary = getBinaryCodeForInstr(MI);
+
+ // Set the conditional execution predicate
+ Binary |= II->getPredicate(&MI) << ARMII::CondShift;
+
+ // Encode S bit if MI modifies CPSR.
+ Binary |= getAddrModeSBit(MI, TID);
+
+ // Encode register def if there is one.
+ unsigned NumDefs = TID.getNumDefs();
+ unsigned OpIdx = 0;
+ if (NumDefs)
+ Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
+ else if (ImplicitRd)
+ // Special handling for implicit use (e.g. PC).
+ Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
+ << ARMII::RegRdShift);
+
+ // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
+ if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
+ ++OpIdx;
+
+ // Encode first non-shifter register operand if there is one.
+ bool isUnary = TID.TSFlags & ARMII::UnaryDP;
+ if (!isUnary) {
+ if (ImplicitRn)
+ // Special handling for implicit use (e.g. PC).
+ Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
+ << ARMII::RegRnShift);
+ else {
+ Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
+ ++OpIdx;
}
+ }
- break;
+ // Encode shifter operand.
+ const MachineOperand &MO = MI.getOperand(OpIdx);
+ if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
+ // Encode SoReg.
+ emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
+ return;
}
- case ARMII::AddrMode2: {
- // bit 26 is always 1
- Value |= 1 << 26;
- unsigned Index = (Desc->TSFlags & ARMII::IndexModeMask);
- // if the instruction uses offset addressing or pre-indexed addressing,
- // set bit P(24) to 1
- if (Index == ARMII::IndexModePre || Index == 0)
- Value |= 1 << ARMII::IndexShift;
- // if the instruction uses post-indexed addressing, set bit W(21) to 1
- if (Index == ARMII::IndexModePre)
- Value |= 1 << 21;
+ if (MO.isReg()) {
+ // Encode register Rm.
+ emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
+ return;
+ }
- unsigned Format = (Desc->TSFlags & ARMII::FormMask);
- // If it is a load instruction (except LDRD), set bit L(20) to 1
- if (Format == ARMII::LdFrm)
- Value |= 1 << ARMII::L_BitShift;
+ // Encode so_imm.
+ Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
- // set bit B(22)
- unsigned BitByte = getBaseOpcodeFor(Desc);
- Value |= BitByte << 22;
+ emitWordLE(Binary);
+}
- // set first operand
- op = getMachineOpValue(MI,0);
- Value |= op << ARMII::RegRdShift;
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitLoadStoreInstruction(
+ const MachineInstr &MI,
+ unsigned ImplicitRd,
+ unsigned ImplicitRn) {
+ const TargetInstrDesc &TID = MI.getDesc();
+ unsigned Form = TID.TSFlags & ARMII::FormMask;
+ bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
+
+ // Part of binary is determined by TableGn.
+ unsigned Binary = getBinaryCodeForInstr(MI);
+
+ // Set the conditional execution predicate
+ Binary |= II->getPredicate(&MI) << ARMII::CondShift;
+
+ unsigned OpIdx = 0;
+
+ // Operand 0 of a pre- and post-indexed store is the address base
+ // writeback. Skip it.
+ bool Skipped = false;
+ if (IsPrePost && Form == ARMII::StFrm) {
+ ++OpIdx;
+ Skipped = true;
+ }
- // set second operand
- op = getMachineOpValue(MI,1);
- Value |= op << ARMII::RegRnShift;
+ // Set first operand
+ if (ImplicitRd)
+ // Special handling for implicit use (e.g. PC).
+ Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
+ << ARMII::RegRdShift);
+ else
+ Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
+
+ // Set second operand
+ if (ImplicitRn)
+ // Special handling for implicit use (e.g. PC).
+ Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
+ << ARMII::RegRnShift);
+ else
+ Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
+
+ // If this is a two-address operand, skip it. e.g. LDR_PRE.
+ if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
+ ++OpIdx;
+
+ const MachineOperand &MO2 = MI.getOperand(OpIdx);
+ unsigned AM2Opc = (ImplicitRn == ARM::PC)
+ ? 0 : MI.getOperand(OpIdx+1).getImm();
+
+ // Set bit U(23) according to sign of immed value (positive or negative).
+ Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
+ ARMII::U_BitShift);
+ if (!MO2.getReg()) { // is immediate
+ if (ARM_AM::getAM2Offset(AM2Opc))
+ // Set the value of offset_12 field
+ Binary |= ARM_AM::getAM2Offset(AM2Opc);
+ emitWordLE(Binary);
+ return;
+ }
- const MachineOperand &MO2 = MI.getOperand(2);
- const MachineOperand &MO3 = MI.getOperand(3);
+ // Set bit I(25), because this is not in immediate enconding.
+ Binary |= 1 << ARMII::I_BitShift;
+ assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
+ // Set bit[3:0] to the corresponding Rm register
+ Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
+
+ // If this instr is in scaled register offset/index instruction, set
+ // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
+ if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
+ Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
+ Binary |= ShImm << ARMII::ShiftShift; // shift_immed
+ }
- // set bit U(23) according to signal of immed value (positive or negative)
- Value |= (ARM_AM::getAM2Op(MO3.getImm()) == ARM_AM::add ? 1 : 0) <<
- ARMII::U_BitShift;
- if (!MO2.getReg()) { // is immediate
- if (ARM_AM::getAM2Offset(MO3.getImm()))
- // set the value of offset_12 field
- Value |= ARM_AM::getAM2Offset(MO3.getImm());
- break;
- }
+ emitWordLE(Binary);
+}
- // set bit I(25), because this is not in immediate enconding.
- Value |= 1 << ARMII::I_BitShift;
- assert(MRegisterInfo::isPhysicalRegister(MO2.getReg()));
- // set bit[3:0] to the corresponding Rm register
- Value |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
-
- // if this instr is in scaled register offset/index instruction, set
- // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
- if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm())) {
- unsigned ShiftOp = getShiftOp(MO3);
- Value |= ShiftOp << 5; // shift
- Value |= ShImm << 7; // shift_immed
- }
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitMiscLoadStoreInstruction(const MachineInstr &MI,
+ unsigned ImplicitRn) {
+ const TargetInstrDesc &TID = MI.getDesc();
+ unsigned Form = TID.TSFlags & ARMII::FormMask;
+ bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
- break;
+ // Part of binary is determined by TableGn.
+ unsigned Binary = getBinaryCodeForInstr(MI);
+
+ // Set the conditional execution predicate
+ Binary |= II->getPredicate(&MI) << ARMII::CondShift;
+
+ unsigned OpIdx = 0;
+
+ // Operand 0 of a pre- and post-indexed store is the address base
+ // writeback. Skip it.
+ bool Skipped = false;
+ if (IsPrePost && Form == ARMII::StMiscFrm) {
+ ++OpIdx;
+ Skipped = true;
}
- case ARMII::AddrMode3: {
- unsigned Index = (Desc->TSFlags & ARMII::IndexModeMask);
- // if the instruction uses offset addressing or pre-indexed addressing,
- // set bit P(24) to 1
- if (Index == ARMII::IndexModePre || Index == 0)
- Value |= 1 << ARMII::IndexShift;
+ // Set first operand
+ Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
+
+ // Skip LDRD and STRD's second operand.
+ if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
+ ++OpIdx;
+
+ // Set second operand
+ if (ImplicitRn)
+ // Special handling for implicit use (e.g. PC).
+ Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
+ << ARMII::RegRnShift);
+ else
+ Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
+
+ // If this is a two-address operand, skip it. e.g. LDRH_POST.
+ if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
+ ++OpIdx;
+
+ const MachineOperand &MO2 = MI.getOperand(OpIdx);
+ unsigned AM3Opc = (ImplicitRn == ARM::PC)
+ ? 0 : MI.getOperand(OpIdx+1).getImm();
+
+ // Set bit U(23) according to sign of immed value (positive or negative)
+ Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
+ ARMII::U_BitShift);
+
+ // If this instr is in register offset/index encoding, set bit[3:0]
+ // to the corresponding Rm register.
+ if (MO2.getReg()) {
+ Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
+ emitWordLE(Binary);
+ return;
+ }
- unsigned Format = (Desc->TSFlags & ARMII::FormMask);
- // If it is a load instruction (except LDRD), set bit L(20) to 1
- if (Format == ARMII::LdFrm && opcode != ARM::LDRD)
- Value |= 1 << ARMII::L_BitShift;
+ // This instr is in immediate offset/index encoding, set bit 22 to 1.
+ Binary |= 1 << ARMII::AM3_I_BitShift;
+ if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
+ // Set operands
+ Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
+ Binary |= (ImmOffs & 0xF); // immedL
+ }
+
+ emitWordLE(Binary);
+}
+
+static unsigned getAddrModeUPBits(unsigned Mode) {
+ unsigned Binary = 0;
+
+ // Set addressing mode by modifying bits U(23) and P(24)
+ // IA - Increment after - bit U = 1 and bit P = 0
+ // IB - Increment before - bit U = 1 and bit P = 1
+ // DA - Decrement after - bit U = 0 and bit P = 0
+ // DB - Decrement before - bit U = 0 and bit P = 1
+ switch (Mode) {
+ default: LLVM_UNREACHABLE("Unknown addressing sub-mode!");
+ case ARM_AM::da: break;
+ case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
+ case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
+ case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
+ }
- // bit[7:4] is the opcode of this instruction class (bits S and H).
- unsigned char BaseOpcode = getBaseOpcodeFor(Desc);
- Value |= BaseOpcode << 4;
+ return Binary;
+}
+
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitLoadStoreMultipleInstruction(
+ const MachineInstr &MI) {
+ // Part of binary is determined by TableGn.
+ unsigned Binary = getBinaryCodeForInstr(MI);
- // set first operand
- op = getMachineOpValue(MI,0);
- Value |= op << ARMII::RegRdShift;
+ // Set the conditional execution predicate
+ Binary |= II->getPredicate(&MI) << ARMII::CondShift;
- // set second operand
- op = getMachineOpValue(MI,1);
- Value |= op << ARMII::RegRnShift;
+ // Set base address operand
+ Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
- const MachineOperand &MO2 = MI.getOperand(2);
- const MachineOperand &MO3 = MI.getOperand(3);
+ // Set addressing mode by modifying bits U(23) and P(24)
+ const MachineOperand &MO = MI.getOperand(1);
+ Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
- // set bit U(23) according to signal of immed value (positive or negative)
- Value |= (ARM_AM::getAM2Op(MO3.getImm()) == ARM_AM::add ? 1 : 0) <<
- ARMII::U_BitShift;
+ // Set bit W(21)
+ if (ARM_AM::getAM4WBFlag(MO.getImm()))
+ Binary |= 0x1 << ARMII::W_BitShift;
- // if this instr is in register offset/index encoding, set bit[3:0]
- // to the corresponding Rm register.
- if (MO2.getReg()) {
- Value |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
+ // Set registers
+ for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
+ const MachineOperand &MO = MI.getOperand(i);
+ if (!MO.isReg() || MO.isImplicit())
break;
- }
+ unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
+ assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
+ RegNum < 16);
+ Binary |= 0x1 << RegNum;
+ }
- // if this instr is in immediate offset/index encoding, set bit 22 to 1
- if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm())) {
- Value |= 1 << 22;
- // set operands
- Value |= (ImmOffs >> 4) << 8; // immedH
- Value |= (ImmOffs & ~0xF); // immedL
- }
+ emitWordLE(Binary);
+}
- break;
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitMulFrmInstruction(const MachineInstr &MI) {
+ const TargetInstrDesc &TID = MI.getDesc();
+
+ // Part of binary is determined by TableGn.
+ unsigned Binary = getBinaryCodeForInstr(MI);
+
+ // Set the conditional execution predicate
+ Binary |= II->getPredicate(&MI) << ARMII::CondShift;
+
+ // Encode S bit if MI modifies CPSR.
+ Binary |= getAddrModeSBit(MI, TID);
+
+ // 32x32->64bit operations have two destination registers. The number
+ // of register definitions will tell us if that's what we're dealing with.
+ unsigned OpIdx = 0;
+ if (TID.getNumDefs() == 2)
+ Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
+
+ // Encode Rd
+ Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
+
+ // Encode Rm
+ Binary |= getMachineOpValue(MI, OpIdx++);
+
+ // Encode Rs
+ Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
+
+ // Many multiple instructions (e.g. MLA) have three src operands. Encode
+ // it as Rn (for multiply, that's in the same offset as RdLo.
+ if (TID.getNumOperands() > OpIdx &&
+ !TID.OpInfo[OpIdx].isPredicate() &&
+ !TID.OpInfo[OpIdx].isOptionalDef())
+ Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
+
+ emitWordLE(Binary);
+}
+
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitExtendInstruction(const MachineInstr &MI) {
+ const TargetInstrDesc &TID = MI.getDesc();
+
+ // Part of binary is determined by TableGn.
+ unsigned Binary = getBinaryCodeForInstr(MI);
+
+ // Set the conditional execution predicate
+ Binary |= II->getPredicate(&MI) << ARMII::CondShift;
+
+ unsigned OpIdx = 0;
+
+ // Encode Rd
+ Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
+
+ const MachineOperand &MO1 = MI.getOperand(OpIdx++);
+ const MachineOperand &MO2 = MI.getOperand(OpIdx);
+ if (MO2.isReg()) {
+ // Two register operand form.
+ // Encode Rn.
+ Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
+
+ // Encode Rm.
+ Binary |= getMachineOpValue(MI, MO2);
+ ++OpIdx;
+ } else {
+ Binary |= getMachineOpValue(MI, MO1);
}
- case ARMII::AddrMode4: {
- // bit 27 is always 1
- Value |= 1 << 27;
- unsigned Format = (Desc->TSFlags & ARMII::FormMask);
- // if it is a load instr, set bit L(20) to 1
- if (Format == ARMII::LdFrm)
- Value |= 1 << ARMII::L_BitShift;
+ // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
+ if (MI.getOperand(OpIdx).isImm() &&
+ !TID.OpInfo[OpIdx].isPredicate() &&
+ !TID.OpInfo[OpIdx].isOptionalDef())
+ Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
- unsigned OpIndex = 0;
+ emitWordLE(Binary);
+}
- // set first operand
- op = getMachineOpValue(MI,OpIndex);
- Value |= op << ARMII::RegRnShift;
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitMiscArithInstruction(const MachineInstr &MI) {
+ const TargetInstrDesc &TID = MI.getDesc();
- // set addressing mode by modifying bits U(23) and P(24)
- // IA - Increment after - bit U = 1 and bit P = 0
- // IB - Increment before - bit U = 1 and bit P = 1
- // DA - Decrement after - bit U = 0 and bit P = 0
- // DB - Decrement before - bit U = 0 and bit P = 1
- const MachineOperand &MO = MI.getOperand(OpIndex + 1);
- ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO.getImm());
- switch(Mode) {
- default: assert(0 && "Unknown addressing sub-mode!");
- case ARM_AM::ia: Value |= 0x1 << 23; break;
- case ARM_AM::ib: Value |= 0x3 << 23; break;
- case ARM_AM::da: break;
- case ARM_AM::db: Value |= 0x1 << 24; break;
- }
+ // Part of binary is determined by TableGn.
+ unsigned Binary = getBinaryCodeForInstr(MI);
- // set bit W(21)
- if (ARM_AM::getAM4WBFlag(MO.getImm()))
- Value |= 0x1 << 21;
+ // Set the conditional execution predicate
+ Binary |= II->getPredicate(&MI) << ARMII::CondShift;
- // set registers
- for (unsigned i = OpIndex + 4, e = MI.getNumOperands(); i != e; ++i) {
- const MachineOperand &MOR = MI.getOperand(i);
- unsigned RegNumber = ARMRegisterInfo::getRegisterNumbering(MOR.getReg());
- assert(MRegisterInfo::isPhysicalRegister(MOR.getReg()) && RegNumber < 16);
- Value |= 0x1 << RegNumber;
- }
+ unsigned OpIdx = 0;
+
+ // Encode Rd
+ Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
+
+ const MachineOperand &MO = MI.getOperand(OpIdx++);
+ if (OpIdx == TID.getNumOperands() ||
+ TID.OpInfo[OpIdx].isPredicate() ||
+ TID.OpInfo[OpIdx].isOptionalDef()) {
+ // Encode Rm and it's done.
+ Binary |= getMachineOpValue(MI, MO);
+ emitWordLE(Binary);
+ return;
+ }
+
+ // Encode Rn.
+ Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
+
+ // Encode Rm.
+ Binary |= getMachineOpValue(MI, OpIdx++);
+ // Encode shift_imm.
+ unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
+ assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
+ Binary |= ShiftAmt << ARMII::ShiftShift;
+
+ emitWordLE(Binary);
+}
+
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitBranchInstruction(const MachineInstr &MI) {
+ const TargetInstrDesc &TID = MI.getDesc();
+
+ if (TID.Opcode == ARM::TPsoft) {
+ LLVM_UNREACHABLE("ARM::TPsoft FIXME"); // FIXME
+ }
+
+ // Part of binary is determined by TableGn.
+ unsigned Binary = getBinaryCodeForInstr(MI);
+
+ // Set the conditional execution predicate
+ Binary |= II->getPredicate(&MI) << ARMII::CondShift;
+
+ // Set signed_immed_24 field
+ Binary |= getMachineOpValue(MI, 0);
+
+ emitWordLE(Binary);
+}
+
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitInlineJumpTable(unsigned JTIndex) {
+ // Remember the base address of the inline jump table.
+ uintptr_t JTBase = MCE.getCurrentPCValue();
+ JTI->addJumpTableBaseAddr(JTIndex, JTBase);
+ DOUT << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase << '\n';
+
+ // Now emit the jump table entries.
+ const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
+ for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
+ if (IsPIC)
+ // DestBB address - JT base.
+ emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
+ else
+ // Absolute DestBB address.
+ emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
+ emitWordLE(0);
+ }
+}
+
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitMiscBranchInstruction(const MachineInstr &MI) {
+ const TargetInstrDesc &TID = MI.getDesc();
+
+ // Handle jump tables.
+ if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd ||
+ TID.Opcode == ARM::t2BR_JTr || TID.Opcode == ARM::t2BR_JTadd) {
+ // First emit a ldr pc, [] instruction.
+ emitDataProcessingInstruction(MI, ARM::PC);
+
+ // Then emit the inline jump table.
+ unsigned JTIndex =
+ (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::t2BR_JTr)
+ ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
+ emitInlineJumpTable(JTIndex);
+ return;
+ } else if (TID.Opcode == ARM::BR_JTm || TID.Opcode == ARM::t2BR_JTm) {
+ // First emit a ldr pc, [] instruction.
+ emitLoadStoreInstruction(MI, ARM::PC);
+
+ // Then emit the inline jump table.
+ emitInlineJumpTable(MI.getOperand(3).getIndex());
+ return;
+ }
+
+ // Part of binary is determined by TableGn.
+ unsigned Binary = getBinaryCodeForInstr(MI);
+
+ // Set the conditional execution predicate
+ Binary |= II->getPredicate(&MI) << ARMII::CondShift;
+
+ if (TID.Opcode == ARM::BX_RET)
+ // The return register is LR.
+ Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
+ else
+ // otherwise, set the return register
+ Binary |= getMachineOpValue(MI, 0);
+
+ emitWordLE(Binary);
+}
+
+static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
+ unsigned RegD = MI.getOperand(OpIdx).getReg();
+ unsigned Binary = 0;
+ bool isSPVFP = false;
+ RegD = ARMRegisterInfo::getRegisterNumbering(RegD, isSPVFP);
+ if (!isSPVFP)
+ Binary |= RegD << ARMII::RegRdShift;
+ else {
+ Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
+ Binary |= (RegD & 0x01) << ARMII::D_BitShift;
+ }
+ return Binary;
+}
+
+static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
+ unsigned RegN = MI.getOperand(OpIdx).getReg();
+ unsigned Binary = 0;
+ bool isSPVFP = false;
+ RegN = ARMRegisterInfo::getRegisterNumbering(RegN, isSPVFP);
+ if (!isSPVFP)
+ Binary |= RegN << ARMII::RegRnShift;
+ else {
+ Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
+ Binary |= (RegN & 0x01) << ARMII::N_BitShift;
+ }
+ return Binary;
+}
+
+static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
+ unsigned RegM = MI.getOperand(OpIdx).getReg();
+ unsigned Binary = 0;
+ bool isSPVFP = false;
+ RegM = ARMRegisterInfo::getRegisterNumbering(RegM, isSPVFP);
+ if (!isSPVFP)
+ Binary |= RegM;
+ else {
+ Binary |= ((RegM & 0x1E) >> 1);
+ Binary |= (RegM & 0x01) << ARMII::M_BitShift;
+ }
+ return Binary;
+}
+
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitVFPArithInstruction(const MachineInstr &MI) {
+ const TargetInstrDesc &TID = MI.getDesc();
+
+ // Part of binary is determined by TableGn.
+ unsigned Binary = getBinaryCodeForInstr(MI);
+
+ // Set the conditional execution predicate
+ Binary |= II->getPredicate(&MI) << ARMII::CondShift;
+
+ unsigned OpIdx = 0;
+ assert((Binary & ARMII::D_BitShift) == 0 &&
+ (Binary & ARMII::N_BitShift) == 0 &&
+ (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
+
+ // Encode Dd / Sd.
+ Binary |= encodeVFPRd(MI, OpIdx++);
+
+ // If this is a two-address operand, skip it, e.g. FMACD.
+ if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
+ ++OpIdx;
+
+ // Encode Dn / Sn.
+ if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
+ Binary |= encodeVFPRn(MI, OpIdx++);
+
+ if (OpIdx == TID.getNumOperands() ||
+ TID.OpInfo[OpIdx].isPredicate() ||
+ TID.OpInfo[OpIdx].isOptionalDef()) {
+ // FCMPEZD etc. has only one operand.
+ emitWordLE(Binary);
+ return;
+ }
+
+ // Encode Dm / Sm.
+ Binary |= encodeVFPRm(MI, OpIdx);
+
+ emitWordLE(Binary);
+}
+
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitVFPConversionInstruction(
+ const MachineInstr &MI) {
+ const TargetInstrDesc &TID = MI.getDesc();
+ unsigned Form = TID.TSFlags & ARMII::FormMask;
+
+ // Part of binary is determined by TableGn.
+ unsigned Binary = getBinaryCodeForInstr(MI);
+
+ // Set the conditional execution predicate
+ Binary |= II->getPredicate(&MI) << ARMII::CondShift;
+
+ switch (Form) {
+ default: break;
+ case ARMII::VFPConv1Frm:
+ case ARMII::VFPConv2Frm:
+ case ARMII::VFPConv3Frm:
+ // Encode Dd / Sd.
+ Binary |= encodeVFPRd(MI, 0);
+ break;
+ case ARMII::VFPConv4Frm:
+ // Encode Dn / Sn.
+ Binary |= encodeVFPRn(MI, 0);
+ break;
+ case ARMII::VFPConv5Frm:
+ // Encode Dm / Sm.
+ Binary |= encodeVFPRm(MI, 0);
break;
}
+
+ switch (Form) {
+ default: break;
+ case ARMII::VFPConv1Frm:
+ // Encode Dm / Sm.
+ Binary |= encodeVFPRm(MI, 1);
+ break;
+ case ARMII::VFPConv2Frm:
+ case ARMII::VFPConv3Frm:
+ // Encode Dn / Sn.
+ Binary |= encodeVFPRn(MI, 1);
+ break;
+ case ARMII::VFPConv4Frm:
+ case ARMII::VFPConv5Frm:
+ // Encode Dd / Sd.
+ Binary |= encodeVFPRd(MI, 1);
+ break;
}
- return Value;
+ if (Form == ARMII::VFPConv5Frm)
+ // Encode Dn / Sn.
+ Binary |= encodeVFPRn(MI, 2);
+ else if (Form == ARMII::VFPConv3Frm)
+ // Encode Dm / Sm.
+ Binary |= encodeVFPRm(MI, 2);
+
+ emitWordLE(Binary);
}
+
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
+ // Part of binary is determined by TableGn.
+ unsigned Binary = getBinaryCodeForInstr(MI);
+
+ // Set the conditional execution predicate
+ Binary |= II->getPredicate(&MI) << ARMII::CondShift;
+
+ unsigned OpIdx = 0;
+
+ // Encode Dd / Sd.
+ Binary |= encodeVFPRd(MI, OpIdx++);
+
+ // Encode address base.
+ const MachineOperand &Base = MI.getOperand(OpIdx++);
+ Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
+
+ // If there is a non-zero immediate offset, encode it.
+ if (Base.isReg()) {
+ const MachineOperand &Offset = MI.getOperand(OpIdx);
+ if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
+ if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
+ Binary |= 1 << ARMII::U_BitShift;
+ Binary |= ImmOffs;
+ emitWordLE(Binary);
+ return;
+ }
+ }
+
+ // If immediate offset is omitted, default to +0.
+ Binary |= 1 << ARMII::U_BitShift;
+
+ emitWordLE(Binary);
+}
+
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitVFPLoadStoreMultipleInstruction(
+ const MachineInstr &MI) {
+ // Part of binary is determined by TableGn.
+ unsigned Binary = getBinaryCodeForInstr(MI);
+
+ // Set the conditional execution predicate
+ Binary |= II->getPredicate(&MI) << ARMII::CondShift;
+
+ // Set base address operand
+ Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
+
+ // Set addressing mode by modifying bits U(23) and P(24)
+ const MachineOperand &MO = MI.getOperand(1);
+ Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
+
+ // Set bit W(21)
+ if (ARM_AM::getAM5WBFlag(MO.getImm()))
+ Binary |= 0x1 << ARMII::W_BitShift;
+
+ // First register is encoded in Dd.
+ Binary |= encodeVFPRd(MI, 4);
+
+ // Number of registers are encoded in offset field.
+ unsigned NumRegs = 1;
+ for (unsigned i = 5, e = MI.getNumOperands(); i != e; ++i) {
+ const MachineOperand &MO = MI.getOperand(i);
+ if (!MO.isReg() || MO.isImplicit())
+ break;
+ ++NumRegs;
+ }
+ Binary |= NumRegs * 2;
+
+ emitWordLE(Binary);
+}
+
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitMiscInstruction(const MachineInstr &MI) {
+ // Part of binary is determined by TableGn.
+ unsigned Binary = getBinaryCodeForInstr(MI);
+
+ // Set the conditional execution predicate
+ Binary |= II->getPredicate(&MI) << ARMII::CondShift;
+
+ emitWordLE(Binary);
+}
+
+#include "ARMGenCodeEmitter.inc"
+
projects / oota-llvm.git / blobdiff