Delete trailing whitespace; NFC

[oota-llvm.git] / lib / Target / AArch64 / Utils / AArch64BaseInfo.h

diff --git a/lib/Target/AArch64/Utils/AArch64BaseInfo.h b/lib/Target/AArch64/Utils/AArch64BaseInfo.h
index 659ea909d7d8ebd16fe2cd34395843fefcaf708f..e63627eae123b4eb71381d1f991260d25d3ea0f1 100644 (file)
--- a/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+++ b/lib/Target/AArch64/Utils/AArch64BaseInfo.h
@@ -22,6 +22,7 @@
 #include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends.
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends.
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/StringSwitch.h"

+#include "llvm/MC/SubtargetFeature.h"

 #include "llvm/Support/ErrorHandling.h"
 
 namespace llvm {
 #include "llvm/Support/ErrorHandling.h"
 
 namespace llvm {


@@ -280,15 +281,22 @@ struct AArch64NamedImmMapper {
   struct Mapping {
     const char *Name;
     uint32_t Value;
   struct Mapping {
     const char *Name;
     uint32_t Value;

-    uint64_t AvailableForFeatures;
-    // empty AvailableForFeatures means "always-on"
-    bool isNameEqual(std::string Other, uint64_t FeatureBits=~0ULL) const {
-      if (AvailableForFeatures && !(AvailableForFeatures & FeatureBits))
+    // Set of features this mapping is available for
+    // Zero value of FeatureBitSet means the mapping is always available
+    FeatureBitset FeatureBitSet;
+
+    bool isNameEqual(std::string Other,
+                     const FeatureBitset& FeatureBits) const {
+      if (FeatureBitSet.any() &&
+          (FeatureBitSet & FeatureBits).none())

         return false;
       return Name == Other;
     }
         return false;
       return Name == Other;
     }

-    bool isValueEqual(uint32_t Other, uint64_t FeatureBits=~0ULL) const {
-      if (AvailableForFeatures && !(AvailableForFeatures & FeatureBits))
+
+    bool isValueEqual(uint32_t Other,
+                      const FeatureBitset& FeatureBits) const {
+      if (FeatureBitSet.any() &&
+          (FeatureBitSet & FeatureBits).none())

         return false;
       return Value == Other;
     }
         return false;
       return Value == Other;
     }


@@ -298,8 +306,12 @@ struct AArch64NamedImmMapper {
   AArch64NamedImmMapper(const Mapping (&Mappings)[N], uint32_t TooBigImm)
     : Mappings(&Mappings[0]), NumMappings(N), TooBigImm(TooBigImm) {}
 
   AArch64NamedImmMapper(const Mapping (&Mappings)[N], uint32_t TooBigImm)
     : Mappings(&Mappings[0]), NumMappings(N), TooBigImm(TooBigImm) {}
 

-  StringRef toString(uint32_t Value, uint64_t FeatureBits, bool &Valid) const;
-  uint32_t fromString(StringRef Name, uint64_t FeatureBits, bool &Valid) const;
+  // Maps value to string, depending on availability for FeatureBits given
+  StringRef toString(uint32_t Value, const FeatureBitset& FeatureBits,
+                     bool &Valid) const;
+  // Maps string to value, depending on availability for FeatureBits given
+  uint32_t fromString(StringRef Name, const FeatureBitset& FeatureBits,
+                     bool &Valid) const;

 
   /// Many of the instructions allow an alternative assembly form consisting of
   /// a simple immediate. Currently the only valid forms are ranges [0, N) where
 
   /// Many of the instructions allow an alternative assembly form consisting of
   /// a simple immediate. Currently the only valid forms are ranges [0, N) where


@@ -325,7 +337,9 @@ namespace AArch64AT {
     S12E1R = 0x63c4, // 01  100  0111  1000  100
     S12E1W = 0x63c5, // 01  100  0111  1000  101
     S12E0R = 0x63c6, // 01  100  0111  1000  110
     S12E1R = 0x63c4, // 01  100  0111  1000  100
     S12E1W = 0x63c5, // 01  100  0111  1000  101
     S12E0R = 0x63c6, // 01  100  0111  1000  110

-    S12E0W = 0x63c7  // 01  100  0111  1000  111
+    S12E0W = 0x63c7, // 01  100  0111  1000  111
+    S1E1RP = 0x43c8, // 01  000  0111  1001  000
+    S1E1WP = 0x43c9  // 01  000  0111  1001  001

   };
 
   struct ATMapper : AArch64NamedImmMapper {
   };
 
   struct ATMapper : AArch64NamedImmMapper {


@@ -451,6 +465,9 @@ namespace AArch64PState {
 
     // v8.1a "Privileged Access Never" extension-specific PStates
     PAN = 0x04,
 
     // v8.1a "Privileged Access Never" extension-specific PStates
     PAN = 0x04,

+
+    // v8.2a "User Access Override" extension-specific PStates
+    UAO = 0x03

   };
 
   struct PStateMapper : AArch64NamedImmMapper {
   };
 
   struct PStateMapper : AArch64NamedImmMapper {


@@ -461,6 +478,21 @@ namespace AArch64PState {
 
 }
 
 
 }
 

+namespace AArch64PSBHint {
+  enum PSBHintValues {
+    Invalid = -1,
+    // v8.2a "Statistical Profiling" extension-specific PSB operands
+    CSync = 0x11,  // psb csync = hint #0x11
+  };
+
+  struct PSBHintMapper : AArch64NamedImmMapper {
+    const static Mapping PSBHintMappings[];
+
+    PSBHintMapper();
+  };
+
+}
+

 namespace AArch64SE {
     enum ShiftExtSpecifiers {
         Invalid = -1,
 namespace AArch64SE {
     enum ShiftExtSpecifiers {
         Invalid = -1,


@@ -582,6 +614,7 @@ namespace AArch64SysReg {
     ID_A64ISAR1_EL1   = 0xc031, // 11  000  0000  0110  001
     ID_A64MMFR0_EL1   = 0xc038, // 11  000  0000  0111  000
     ID_A64MMFR1_EL1   = 0xc039, // 11  000  0000  0111  001
     ID_A64ISAR1_EL1   = 0xc031, // 11  000  0000  0110  001
     ID_A64MMFR0_EL1   = 0xc038, // 11  000  0000  0111  000
     ID_A64MMFR1_EL1   = 0xc039, // 11  000  0000  0111  001

+    ID_A64MMFR2_EL1   = 0xc03a, // 11  000  0000  0111  010

     MVFR0_EL1         = 0xc018, // 11  000  0000  0011  000
     MVFR1_EL1         = 0xc019, // 11  000  0000  0011  001
     MVFR2_EL1         = 0xc01a, // 11  000  0000  0011  010
     MVFR0_EL1         = 0xc018, // 11  000  0000  0011  000
     MVFR1_EL1         = 0xc019, // 11  000  0000  0011  001
     MVFR2_EL1         = 0xc01a, // 11  000  0000  0011  010


@@ -591,6 +624,7 @@ namespace AArch64SysReg {
     ISR_EL1           = 0xc608, // 11  000  1100  0001  000
     CNTPCT_EL0        = 0xdf01, // 11  011  1110  0000  001
     CNTVCT_EL0        = 0xdf02,  // 11  011  1110  0000  010
     ISR_EL1           = 0xc608, // 11  000  1100  0001  000
     CNTPCT_EL0        = 0xdf01, // 11  011  1110  0000  001
     CNTVCT_EL0        = 0xdf02,  // 11  011  1110  0000  010

+    ID_MMFR4_EL1      = 0xc016,  // 11  000  0000  0010  110

 
     // Trace registers
     TRCSTATR          = 0x8818, // 10  001  0000  0011  000
 
     // Trace registers
     TRCSTATR          = 0x8818, // 10  001  0000  0011  000


@@ -1177,6 +1211,24 @@ namespace AArch64SysReg {
     SPSR_EL12         = 0xea00, // 11  101  0100  0000  000
     ELR_EL12          = 0xea01, // 11  101  0100  0000  001
 
     SPSR_EL12         = 0xea00, // 11  101  0100  0000  000
     ELR_EL12          = 0xea01, // 11  101  0100  0000  001
 

+    // v8.2a registers
+    UAO               = 0xc214, // 11  000  0100  0010  100
+
+    // v8.2a "Statistical Profiling extension" registers
+    PMBLIMITR_EL1     = 0xc4d0, // 11  000  1001  1010  000
+    PMBPTR_EL1        = 0xc4d1, // 11  000  1001  1010  001
+    PMBSR_EL1         = 0xc4d3, // 11  000  1001  1010  011
+    PMBIDR_EL1        = 0xc4d7, // 11  000  1001  1010  111
+    PMSCR_EL2         = 0xe4c8, // 11  100  1001  1001  000
+    PMSCR_EL12        = 0xecc8, // 11  101  1001  1001  000
+    PMSCR_EL1         = 0xc4c8, // 11  000  1001  1001  000
+    PMSICR_EL1        = 0xc4ca, // 11  000  1001  1001  010
+    PMSIRR_EL1        = 0xc4cb, // 11  000  1001  1001  011
+    PMSFCR_EL1        = 0xc4cc, // 11  000  1001  1001  100
+    PMSEVFR_EL1       = 0xc4cd, // 11  000  1001  1001  101
+    PMSLATFR_EL1      = 0xc4ce, // 11  000  1001  1001  110
+    PMSIDR_EL1        = 0xc4cf, // 11  000  1001  1001  111
+

     // Cyclone specific system registers
     CPM_IOACC_CTL_EL3 = 0xff90,
   };
     // Cyclone specific system registers
     CPM_IOACC_CTL_EL3 = 0xff90,
   };


@@ -1192,8 +1244,9 @@ namespace AArch64SysReg {
     size_t NumInstMappings;
 
     SysRegMapper() { }
     size_t NumInstMappings;
 
     SysRegMapper() { }

-    uint32_t fromString(StringRef Name, uint64_t FeatureBits, bool &Valid) const;
-    std::string toString(uint32_t Bits, uint64_t FeatureBits) const;
+    uint32_t fromString(StringRef Name, const FeatureBitset& FeatureBits,
+                        bool &Valid) const;
+    std::string toString(uint32_t Bits, const FeatureBitset& FeatureBits) const;

   };
 
   struct MSRMapper : SysRegMapper {
   };
 
   struct MSRMapper : SysRegMapper {


@@ -1269,7 +1322,7 @@ namespace AArch64TLBI {
       return true;
     }
   }
       return true;
     }
   }

-} 
+}

 
 namespace AArch64II {
   /// Target Operand Flag enum.
 
 namespace AArch64II {
   /// Target Operand Flag enum.