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[AArch64] Fix bug in prolog clobbering live reg when shrink wrapping.
[oota-llvm.git]
/
lib
/
Target
/
AArch64
/
AArch64SelectionDAGInfo.h
diff --git
a/lib/Target/AArch64/AArch64SelectionDAGInfo.h
b/lib/Target/AArch64/AArch64SelectionDAGInfo.h
index 8381f9916a8cfcc97e688cf8be48c1f94d6e0049..97421b45b122e9a06d398a33b23e18e45c123136 100644
(file)
--- a/
lib/Target/AArch64/AArch64SelectionDAGInfo.h
+++ b/
lib/Target/AArch64/AArch64SelectionDAGInfo.h
@@
-11,21
+11,15
@@
//
//===----------------------------------------------------------------------===//
//
//===----------------------------------------------------------------------===//
-#ifndef
AArch
64SELECTIONDAGINFO_H
-#define
AArch
64SELECTIONDAGINFO_H
+#ifndef
LLVM_LIB_TARGET_AARCH64_AARCH
64SELECTIONDAGINFO_H
+#define
LLVM_LIB_TARGET_AARCH64_AARCH
64SELECTIONDAGINFO_H
#include "llvm/Target/TargetSelectionDAGInfo.h"
namespace llvm {
class AArch64SelectionDAGInfo : public TargetSelectionDAGInfo {
#include "llvm/Target/TargetSelectionDAGInfo.h"
namespace llvm {
class AArch64SelectionDAGInfo : public TargetSelectionDAGInfo {
- /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
- /// make the right decision when generating code for different targets.
- const AArch64Subtarget *Subtarget;
-
public:
public:
- explicit AArch64SelectionDAGInfo(const TargetMachine &TM);
- ~AArch64SelectionDAGInfo();
SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl, SDValue Chain,
SDValue Dst, SDValue Src, SDValue Size,
SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl, SDValue Chain,
SDValue Dst, SDValue Src, SDValue Size,